Type Definition ambiq_apollo1_pac::adc::sl6cfg::R

type R = R<u32, SL6CFG>;

Reader of register SL6CFG

Methods

impl R

pub fn adsel6(&self) -> ADSEL6_R

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn thsel6(&self) -> THSEL6_R

Bits 16:18 - Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

pub fn chsel6(&self) -> CHSEL6_R

Bits 8:11 - Select one of the 13 channel inputs for this slot.

pub fn wcen6(&self) -> WCEN6_R

Bit 1 - This bit enables the window compare function for slot 6.

pub fn slen6(&self) -> SLEN6_R

Bit 0 - This bit enables slot 6 for ADC conversions.