[−][src]Enum ambiq_apollo1_pac::adc::sl4cfg::THSEL4_A
Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.
Value on reset: 0
Variants
0: 1 ADC clock cycle.
1: 2 ADC clock cycles.
2: 4 ADC clock cycles.
3: 8 ADC clock cycles.
4: 16 ADC clock cycles.
5: 32 ADC clock cycles.
6: 64 ADC clock cycles.
7: 128 ADC clock cycles.
Trait Implementations
impl Clone for THSEL4_A
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fn clone(&self) -> THSEL4_A
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fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl Copy for THSEL4_A
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impl Debug for THSEL4_A
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impl From<THSEL4_A> for u8
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impl PartialEq<THSEL4_A> for THSEL4_A
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impl StructuralPartialEq for THSEL4_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,