Type Definition ambiq_apollo1_pac::adc::sl2cfg::W

type W = W<u32, SL2CFG>;

Writer for register SL2CFG

Methods

impl W

pub fn adsel2(&mut self) -> ADSEL2_W

Bits 24:26 - Select the number of measurements to average in the accumulate divide module for this slot.

pub fn thsel2(&mut self) -> THSEL2_W

Bits 16:18 - Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

pub fn chsel2(&mut self) -> CHSEL2_W

Bits 8:11 - Select one of the 13 channel inputs for this slot.

pub fn wcen2(&mut self) -> WCEN2_W

Bit 1 - This bit enables the window compare function for slot 2.

pub fn slen2(&mut self) -> SLEN2_W

Bit 0 - This bit enables slot 2 for ADC conversions.