Enum ambiq_apollo1_pac::adc::sl1cfg::THSEL1_A

#[repr(u8)]
pub enum THSEL1_A {
    _1_ADC_CLK,
    _2_ADC_CLKS,
    _4_ADC_CLKS,
    _8_ADC_CLKS,
    _16_ADC_CLKS,
    _32_ADC_CLKS,
    _64_ADC_CLKS,
    _128_ADC_CLKS,
}

Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5 Mhz clock, the track and hold delay cannot exceed 64 clocks.

Value on reset: 0

Variants

_1_ADC_CLK

0: 1 ADC clock cycle.

_2_ADC_CLKS

1: 2 ADC clock cycles.

_4_ADC_CLKS

2: 4 ADC clock cycles.

_8_ADC_CLKS

3: 8 ADC clock cycles.

_16_ADC_CLKS

4: 16 ADC clock cycles.

_32_ADC_CLKS

5: 32 ADC clock cycles.

_64_ADC_CLKS

6: 64 ADC clock cycles.

_128_ADC_CLKS

7: 128 ADC clock cycles.

Trait Implementations

impl Clone for THSEL1_A

fn clone(&self) -> THSEL1_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for THSEL1_A

impl Debug for THSEL1_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<THSEL1_A> for u8

fn from(variant: THSEL1_A) -> Self

Performs the conversion.

impl PartialEq<THSEL1_A> for THSEL1_A

fn eq(&self, other: &THSEL1_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use] fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for THSEL1_A