pub enum TIM1SW_A {
PCLK2,
PLL,
}
Expand description
Timer1 clock source selection
Value on reset: 0
Variants
PCLK2
0: PCLK2 clock (doubled frequency when prescaled)
PLL
1: PLL vco output (running up to 144 MHz)
Trait Implementations
impl Copy for TIM1SW_A
impl StructuralPartialEq for TIM1SW_A
Auto Trait Implementations
impl RefUnwindSafe for TIM1SW_A
impl Send for TIM1SW_A
impl Sync for TIM1SW_A
impl Unpin for TIM1SW_A
impl UnwindSafe for TIM1SW_A
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more