[−][src]Type Definition alt_sam3x8e::uotghs::HSTDMACONTROL5
type HSTDMACONTROL5 = Reg<u32, _HSTDMACONTROL5>;
Host DMA Channel Control Register (n = 5)
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see hstdmacontrol5 module
Trait Implementations
impl Readable for HSTDMACONTROL5
[src]
read()
method returns hstdmacontrol5::R reader structure
impl ResetValue for HSTDMACONTROL5
[src]
Register HSTDMACONTROL5 reset()
's with value 0
impl Writable for HSTDMACONTROL5
[src]
write(|w| ..)
method takes hstdmacontrol5::W writer structure