Expand description
Tiny AArch64 multi-core simulator.
v0.1 — MOVZ, ADD (imm), LDR/STR (unsigned offset), B + MMIO UART. v0.2 — Stage-1 MMU translation walk (4 KiB granule, 39-bit VA). v0.3 — MSR/MRS + SCTLR_EL1.M=1 routes fetch/load/store through MMU. v0.4 — EL2 boot, ERET drops to EL1. v0.5 — SVC + ESR_EL1 (full EL0 ↔ EL1 syscall round trip). v0.6 — Two cores (P-core / E-core) sharing physical memory + UART. Per-core register file, EL state, and sysregs (incl. MPIDR_EL1).