Crate zynq7000_rt 

Rust bare metal run-time support for the AMD Zynq 7000 SoCs

This includes basic low-level startup code similar to the bare-metal boot routines provided by Xilinx. Some major differences:

• No L2 cache initialization is performed.
• MMU table is specified as Rust code.
• Modification to the stack setup code, because a different linker script is used.

Modules

mmu

The overview of translation table memory attributes is described below.

rtrt and arm_profile=a

Start-up code for Zynq 7000

Functions

_default_handlerrt and arm_profile=a

Our default exception handler.

mmu_l1_table_mutrt and arm_profile=a

Retrieves a mutable reference to the MMU L1 page table.

Attribute Macros

entryrt and arm_profile=a

Creates an unsafe program entry point (i.e. a kmain function).

exceptionrt and arm_profile=a

Creates an unsafe exception handler.

irqrt and arm_profile=a

Creates an unsafe interrupt handler.