Crate zynq7000_rt 

Rust bare metal run-time support for the AMD Zynq 7000 SoCs

Startup code and minimal runtime for the AMD Zynq7000 SoC to write bare metal Rust code. This run-time crate is strongly based on the startup code provided by AMD.

It mostly builds on aarch32-rt. It activates the fpu-d32 feature on that crate and overrides the _default_start method to add necessary setup code for the Zynq7000. It re-exports the aarch32-rt crate, including the attributes macros. The documentation specifies these in detail.

Some major differences to the startup code provided by AMD:

• No L2 cache initialization is performed.
• MMU table is specified as Rust code.
• Modification to the stack setup code, because a different linker script is used.

Modules

mmu

The overview of translation table memory attributes is described below.

rtrt and arm_profile=a

Start-up code for Zynq 7000

sectionsrt and arm_profile=a

Code to get the memory regions from the linker script

stacksrt and arm_profile=a

Code for examining linker allocated stacks

Macros

restore_fpu_contextrt and arm_profile=a and (target_abi=eabihf or eabi-fpu) and fpu-d32

This macro expands to code for restoring context on exit from an exception handler. It restores FPU state, assuming 32 DP registers (a ‘D32’ FPU configuration).

save_fpu_contextrt and arm_profile=a and (target_abi=eabihf or eabi-fpu) and fpu-d32

This macro expands to code for saving FPU context on entry to an exception handler. It pushes a multiple of eight bytes to preserve AAPCS alignment. It may damage R0-R3.

Structs

Framert and arm_profile=a

Arguments stacked on interrupt

Functions

_default_handlerrt and arm_profile=a

Our default exception handler.

mmu_l1_table_mutrt and arm_profile=a

Retrieves a mutable reference to the MMU L1 page table.

Attribute Macros

entryrt and arm_profile=a

Creates an unsafe program entry point (i.e. a kmain function).

exceptionrt and arm_profile=a

Creates an unsafe exception handler.

irqrt and arm_profile=a

Creates an unsafe interrupt handler.