zydis_rs/encoder/
types.rs

1//! Encoder types and enums
2//!
3//! This module contains shared type definitions for the encoder module.
4
5/// Encodable encoding types (corresponds to ZydisEncodableEncoding)
6///
7/// This enum represents the different instruction encoding formats
8/// that can be used to encode x86/x64 instructions.
9#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
10pub enum EncodableEncoding {
11    /// Legacy encoding - standard x86/x64 instruction encoding
12    #[default]
13    Legacy,
14    /// 3DNow! encoding - AMD 3DNow! instruction set
15    D3Now,
16    /// XOP encoding - AMD XOP (Extended Operations) instruction set
17    Xop,
18    /// VEX encoding - AVX/AVX2 SIMD instructions (128/256-bit)
19    Vex,
20    /// EVEX encoding - AVX-512 SIMD instructions (512-bit, mask registers)
21    Evex,
22    /// MVEX encoding - Intel Knights Corner (KNC) special encoding
23    Mvex,
24}
25
26/// Branch type for control flow instructions
27///
28/// Corresponds to ZydisBranchType
29#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
30pub enum BranchType {
31    /// No branch type specified
32    #[default]
33    None,
34    /// Short branch - 8-bit relative offset (±128 bytes)
35    Short,
36    /// Near branch - 32-bit relative offset (±2GB)
37    Near,
38    /// Far branch - absolute address with segment selector
39    Far,
40}
41
42/// Branch width for control flow instructions
43///
44/// Corresponds to ZydisBranchWidth
45#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
46pub enum BranchWidth {
47    /// Unknown branch width
48    Unknown,
49    /// No branch width (not a branch instruction)
50    #[default]
51    None,
52    /// 8-bit relative offset
53    B8,
54    /// 16-bit offset/absolute
55    B16,
56    /// 32-bit offset/absolute
57    B32,
58    /// 64-bit absolute (only in 64-bit mode)
59    B64,
60}
61
62/// Address size hint for encoding
63#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
64pub enum AddressSizeHint {
65    /// 16-bit address size
66    B16,
67    /// 32-bit address size
68    B32,
69    /// 64-bit address size
70    #[default]
71    B64,
72}
73
74/// Operand sizehint for encoding
75#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
76pub enum OperandSizeHint {
77    /// 16-bit operand size
78    B16,
79    /// 32-bit operand size
80    B32,
81    /// 64-bit operand size
82    #[default]
83    B64,
84}
85
86/// AVX-512 broadcast mode
87#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
88pub enum BroadcastMode {
89    /// No broadcast
90    #[default]
91    None,
92    /// 1-to-2 broadcast (16-bit)
93    To2,
94    /// 1-to-4 broadcast (32-bit)
95    To4,
96    /// 1-to-8 broadcast (64-bit)
97    To8,
98    /// 1-to-16 broadcast (16-bit to ZMM)
99    To16,
100}
101
102/// AVX-512 rounding mode control
103#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
104pub enum RoundingMode {
105    /// Round to nearest (even)
106    #[default]
107    RN,
108    /// Round down (toward -∞)
109    RD,
110    /// Round up (toward +∞)
111    RU,
112    /// Round toward zero (truncate)
113    RZ,
114}
115
116/// Encoder hints for AVX-512 and advanced instruction encoding
117///
118/// This structure contains optional hints that control encoding behavior,
119/// particularly for AVX-512 instructions with mask registers, broadcast,
120/// rounding control, and exception suppression.
121#[derive(Debug, Clone, Copy, Default)]
122pub struct EncoderHints {
123    /// Address size hint (16/32/64 bits)
124    pub address_size: Option<AddressSizeHint>,
125    /// Operand size hint (16/32/64 bits)
126    pub operand_size: Option<OperandSizeHint>,
127    /// Broadcast mode for memory operands
128    pub broadcast_mode: BroadcastMode,
129    /// Rounding mode for EVEX instructions
130    pub rounding_mode: Option<RoundingMode>,
131    /// Suppress All Exceptions (SAE) flag
132    pub suppress_all_exceptions: bool,
133}
134
135/// Encoder mode configuration
136///
137/// Controls encoder behavior for generating optimal instruction encodings.
138#[derive(Debug, Clone, Copy, Default)]
139pub struct EncoderMode {
140    /// Generate minimal length encodings when possible
141    pub minimal: bool,
142    /// Enable AVX-512 optimizations (prefer EVEX over VEX when beneficial)
143    pub avx512: bool,
144    /// Enable branch optimization(automatic short/near selection)
145    pub branch_optimization: bool,
146    /// Preferred encoding type(None = auto-select)
147    pub preferred_encoding: Option<EncodableEncoding>,
148}
zydis_rs/encoder/types.rs

zydis_rs/encoder/
types.rs
