zydis_rs/encoder/

mod.rs

//! x86/x64 指令编码器模块 / x86/x64 instruction encoder module
//!
//! 本模块提供将结构化表示转换为 x86/x64 指令机器码的功能。
//!
//! This module provides functionality for encoding x86/x64 instructions
//! from a structured representation into raw bytes.
//!
//! ## 支持的指令编码 / Supported Instruction Encodings
//!
//! - Legacy encoding（传统编码）- 基础整数指令
//! - VEX encoding（AVX/AVX2）- 128/256 位向量指令
//! - EVEX encoding（AVX-512）- 512 位向量指令，掩码寄存器
//! - XOP encoding（AMD XOP）- AMD 扩展操作指令
//! - REX prefix（64 位扩展）
//!
//! ## 使用流程 / Usage Flow
//!
//! 1. 创建 `Encoder` 实例
//! 2. 创建 `EncoderRequest` 并添加操作数
//! 3. 调用 `encode()` 生成机器码
//!
//! ## 示例 / Example
//!
//! ```rust,ignore
//! use zydis_rs::{Encoder, EncoderRequest, Mnemonic, Register, MachineMode};
//!
//! let encoder = Encoder::new(MachineMode::Long64, 64)?;
//!
//! // 编码 MOV RAX, RBX
//! let request = EncoderRequest::new(Mnemonic::MOV)
//!     .with_reg(Register::RAX)
//!     .with_reg(Register::RBX);
//! let bytes = encoder.encode(&request)?;
//!
//! // 编码 AVX-512 指令带掩码
//! let request = EncoderRequest::new(Mnemonic::VADDPS)
//!     .with_reg(Register::ZMM1)
//!     .with_reg(Register::ZMM2)
//!     .with_reg(Register::ZMM3)
//!     .with_mask(Register::K1)
//!     .with_zeroing_enabled();
//! let bytes = encoder.encode(&request)?;
//! # Ok::<(), zydis_rs::Error>(())
//! ```

pub mod evex;
pub mod instruction_table;
pub mod opcode;
pub mod operand;
pub mod request;
pub mod types;
pub mod utils;
pub mod validation;
pub mod vex;
pub mod xop;

// Re-exports
pub use evex::{
    EvexBroadcast, EvexInfo, EvexOpcodeMap, EvexPrefix, EvexVectorLength, EvexZeroingMode,
};
pub use instruction_table::{
    EncodingPrefix, InstructionEncoding, OperandEncoding, OperandType, lookup_encoding,
};
pub use operand::{EncoderOperand, MemoryOperand};
pub use request::EncoderRequest;
pub use types::{
    AddressSizeHint, BranchType, BranchWidth, BroadcastMode, EncodableEncoding, EncoderHints,
    EncoderMode, OperandSizeHint, RoundingMode,
};
pub use validation::{EncoderValidator, ValidationError, ValidationErrorKind, ValidationResult};
pub use vex::{VexInfo, VexOpcodeMap, VexPrefix, VexVectorLength};
pub use xop::{XopEncoder, XopInfo, XopOpcodeMap, XopPrefix, XopVectorLength};

// Legacy types for backward compatibility
#[doc(hidden)]
pub use types::BranchType as ZydisBranchType;
#[doc(hidden)]
pub use types::BranchWidth as ZydisBranchWidth;
#[doc(hidden)]
pub use types::EncodableEncoding as ZydisEncodableEncoding;

use crate::error::{EncodeError, Error, Result};
use crate::isa::{MachineMode, Mnemonic, Register};

// Import utility functions
use opcode::{AvxOpcodeMap, get_avx_opcode, get_mov_imm_opcode, get_mov_imm8_opcode};
use utils::{
    displacement_size, encode_modrm, encode_rex, encode_sib, needs_rex_b as check_rex_b,
    needs_rex_for_8bit, needs_rex_r as check_rex_r, register_id, segment_override_prefix,
};

/// Get the ALU opcode extension for a mnemonic (used with 0x83 /n)
fn get_alu_opcode_extension(mnemonic: Mnemonic) -> Option<u8> {
    match mnemonic {
        Mnemonic::ADD => Some(0),
        Mnemonic::OR => Some(1),
        Mnemonic::AND => Some(4),
        Mnemonic::SUB => Some(5),
        Mnemonic::XOR => Some(6),
        Mnemonic::CMP => Some(7),
        _ => None,
    }
}

/// Get the ALU reg-reg opcode for "r/m, r" form
fn get_alu_reg_reg_opcode(mnemonic: Mnemonic) -> Option<u8> {
    match mnemonic {
        Mnemonic::ADD => Some(0x01), // ADD r/m, r
        Mnemonic::SUB => Some(0x29), // SUB r/m, r
        Mnemonic::AND => Some(0x21), // AND r/m, r
        Mnemonic::OR => Some(0x09),  // OR r/m, r
        Mnemonic::XOR => Some(0x31), // XOR r/m, r
        Mnemonic::CMP => Some(0x39), // CMP r/m, r
        _ => None,
    }
}

/// Check if a mnemonic is an AVX instruction
fn is_avx_instruction(mnemonic: Mnemonic) -> bool {
    matches!(
        mnemonic,
        Mnemonic::VMOVAPS
            | Mnemonic::VMOVAPD
            | Mnemonic::VMOVUPS
            | Mnemonic::VMOVUPD
            | Mnemonic::VADDPS
            | Mnemonic::VADDPD
            | Mnemonic::VSUBPS
            | Mnemonic::VSUBPD
            | Mnemonic::VMULPS
            | Mnemonic::VMULPD
            | Mnemonic::VDIVPS
            | Mnemonic::VDIVPD
            | Mnemonic::VXORPS
            | Mnemonic::VXORPD
            | Mnemonic::VSHUFPS
            | Mnemonic::VSHUFPD
            | Mnemonic::VPERM2I128
            | Mnemonic::VPERM2F128
            | Mnemonic::VPERMILPS
            | Mnemonic::VPERMILPD
            | Mnemonic::VPERMD
            | Mnemonic::VPERMQ
            | Mnemonic::VPERMPS
            | Mnemonic::VPERMPD
            | Mnemonic::VPSHUFB
            | Mnemonic::VPSHUFD
            | Mnemonic::VPSHUFHW
            | Mnemonic::VPSHUFLW
            | Mnemonic::VBROADCASTSS
            | Mnemonic::VEXTRACTF128
    )
}

/// Check if a mnemonic is an AVX instruction with imm8 operand
fn is_avx_instruction_with_imm8(mnemonic: Mnemonic) -> bool {
    matches!(
        mnemonic,
        Mnemonic::VSHUFPS
            | Mnemonic::VSHUFPD
            | Mnemonic::VPERM2I128
            | Mnemonic::VPERM2F128
            | Mnemonic::VPERMILPS
            | Mnemonic::VPERMILPD
            | Mnemonic::VPERMQ
            | Mnemonic::VPERMPD
            | Mnemonic::VPSHUFD
            | Mnemonic::VPSHUFHW
            | Mnemonic::VPSHUFLW
            | Mnemonic::VEXTRACTF128
    )
}

/// Check if a mnemonic is an AVX-512 capable instruction
/// These instructions can use EVEX prefix with ZMM registers
fn is_avx512_capable_instruction(mnemonic: Mnemonic) -> bool {
    matches!(
        mnemonic,
        Mnemonic::VMOVAPS
            | Mnemonic::VMOVAPD
            | Mnemonic::VMOVUPS
            | Mnemonic::VMOVUPD
            | Mnemonic::VADDPS
            | Mnemonic::VADDPD
            | Mnemonic::VSUBPS
            | Mnemonic::VSUBPD
            | Mnemonic::VMULPS
            | Mnemonic::VMULPD
            | Mnemonic::VDIVPS
            | Mnemonic::VDIVPD
            | Mnemonic::VXORPS
            | Mnemonic::VXORPD
    )
}

/// x86/x64 指令编码器
///
/// The `Encoder` struct is responsible for converting instruction requests
/// into raw bytes that can be executed by the CPU.
///
/// 编码器负责将指令请求转换为可执行的机器码。
///
/// # 支持的指令 / Supported Instructions
///
/// - 整数运算：ADD, SUB, AND, OR, XOR, CMP, TEST
/// - 数据传送：MOV, LEA, MOVSX, MOVZX
/// - 跳转指令：JMP, JE, JNE, JL, JG, JLE, JGE, CALL, RET
/// - 栈操作：PUSH, POP
/// - AVX 指令：VMOVAPS, VADDPS, VSUBPS, VMULPS, VDIVPS, VXORPS 等
/// - AVX-512 指令：VPADDD, VPSUBD, VPANDD, VPORD 等
///
/// # 示例 / Example
///
/// ```rust,ignore
/// use zydis_rs::{Encoder, EncoderRequest, Mnemonic, Register, MachineMode};
///
/// let encoder = Encoder::new(MachineMode::Long64, 64)?;
///
/// // 编码 MOV RAX, 0x123456789ABCDEF0
/// let request = EncoderRequest::new(Mnemonic::MOV)
///     .with_reg(Register::RAX)
///     .with_imm(0x123456789ABCDEF0u64);
/// let bytes = encoder.encode(&request)?;
///
/// // 编码 ADD RAX, RBX
/// let request2 = EncoderRequest::new(Mnemonic::ADD)
///     .with_reg(Register::RAX)
///     .with_reg(Register::RBX);
/// let bytes2 = encoder.encode(&request2)?;
/// # Ok::<(), zydis_rs::Error>(())
/// ```
///
/// # 注意事项 / Notes
///
/// - 单条指令最大长度为 15 字节
/// - 64 位模式下某些指令需要 REX 前缀
/// - AVX 指令使用 VEX 前缀
/// - AVX-512 指令使用 EVEX 前缀
#[derive(Debug, Clone, Copy)]
pub struct Encoder {
    /// The machine mode (16-bit, 32-bit, or 64-bit) / 机器模式
    machine_mode: MachineMode,
    /// The stack width in bits / 栈宽度（位）
    stack_width: u8,
}

impl Encoder {
    /// 创建指定机器模式的编码器
    ///
    /// Create a new encoder with the specified machine mode and stack width.
    ///
    /// # 参数 / Arguments
    ///
    /// * `mode` - 机器模式 / The machine mode (Long64, Protected32, etc.)
    /// * `stack_width` - 栈宽度（16, 32 或 64 位）/ The stack width in bits (16, 32, or 64)
    ///
    /// # 返回 / Returns
    ///
    /// 返回编码器实例或错误
    ///
    /// # 错误 / Errors
    ///
    /// - `Error::InvalidStackWidth` - 如果栈宽度不是 16、32 或 64
    ///
    /// # 示例 / Example
    ///
    /// ```rust,ignore
    /// use zydis_rs::{Encoder, MachineMode};
    ///
    /// let encoder = Encoder::new(MachineMode::Long64, 64)?;
    /// # Ok::<(), zydis_rs::Error>(())
    /// ```
    pub fn new(mode: MachineMode, stack_width: u8) -> Result<Self> {
        // Validate stack width
        match stack_width {
            16 | 32 | 64 => {}
            _ => return Err(Error::InvalidStackWidth),
        }

        Ok(Self {
            machine_mode: mode,
            stack_width,
        })
    }

    /// 获取机器模式 / Get the machine mode
    #[must_use]
    pub const fn machine_mode(&self) -> MachineMode {
        self.machine_mode
    }

    /// 获取栈宽度 / Get the stack width
    #[must_use]
    pub const fn stack_width(&self) -> u8 {
        self.stack_width
    }

    /// 编码指令请求为字节序列
    ///
    /// Encode an instruction request to bytes.
    ///
    /// # 参数 / Arguments
    ///
    /// * `request` - 要编码的指令请求 / The instruction request to encode
    ///
    /// # 返回 / Returns
    ///
    /// 包含编码后指令字节的向量
    ///
    /// # 错误 / Errors
    ///
    /// - `Error::UnsupportedInstruction` - 不支持的指令
    /// - `Error::InvalidOperand` - 无效的操作数
    /// - `Error::EncodeError` - 编码过程中的其他错误
    ///
    /// # 示例 / Example
    ///
    /// ```rust,ignore
    /// use zydis_rs::{Encoder, MachineMode, EncoderRequest, Mnemonic, Register};
    ///
    /// let encoder = Encoder::new(MachineMode::Long64, 64)?;
    /// let request = EncoderRequest::new(Mnemonic::MOV)
    ///     .with_reg(Register::RAX)
    ///     .with_reg(Register::RBX);
    ///
    /// let bytes = encoder.encode(&request)?;
    /// # Ok::<(), zydis_rs::Error>(())
    /// ```
    pub fn encode(&self, request: &EncoderRequest) -> Result<alloc::vec::Vec<u8>> {
        let mut buffer = [0u8; 15]; // Maximum instruction length is 15 bytes
        let len = self.encode_to_buffer(request, &mut buffer)?;
        Ok(buffer[..len].to_vec())
    }

    /// 编码指令到预分配的缓冲区
    ///
    /// Encode an instruction to a pre-allocated buffer.
    ///
    /// # 参数 / Arguments
    ///
    /// * `request` - 要编码的指令请求 / The instruction request to encode
    /// * `buffer` - 写入编码字节的缓冲区（至少 15 字节）/ The buffer to write the encoded bytes to
    ///
    /// # 返回 / Returns
    ///
    /// 写入缓冲区的字节数
    ///
    /// # 错误 / Errors
    ///
    /// - `Error::BufferTooSmall` - 缓冲区太小（< 15 字节）
    /// - `Error::UnsupportedInstruction` - 不支持的指令
    /// - `Error::InvalidOperand` - 无效的操作数
    ///
    /// # 示例 / Example
    ///
    /// ```rust,ignore
    /// use zydis_rs::{Encoder, EncoderRequest, Mnemonic, Register, MachineMode};
    ///
    /// let encoder = Encoder::new(MachineMode::Long64, 64)?;
    /// let request = EncoderRequest::new(Mnemonic::NOP);
    ///
    /// let mut buffer = [0u8; 15];
    /// let len = encoder.encode_to_buffer(&request, &mut buffer)?;
    /// assert_eq!(len, 1);  // NOP is 0x90
    /// assert_eq!(buffer[0], 0x90);
    /// # Ok::<(), zydis_rs::Error>(())
    /// ```
    pub fn encode_to_buffer(&self, request: &EncoderRequest, buffer: &mut [u8]) -> Result<usize> {
        // Validate buffer size (max instruction length is 15 bytes)
        if buffer.len() < 15 {
            return Err(Error::BufferTooSmall);
        }

        let offset = 0usize;

        // Handle special cases first
        match request.mnemonic {
            Mnemonic::NOP => {
                // NOP is simple: just 0x90
                buffer[offset] = 0x90;
                return Ok(1);
            }
            Mnemonic::RET => {
                // Near return: 0xC3
                buffer[offset] = 0xC3;
                return Ok(1);
            }
            Mnemonic::INT3 => {
                // INT3: 0xCC
                buffer[offset] = 0xCC;
                return Ok(1);
            }
            Mnemonic::HLT => {
                // HLT: 0xF4
                buffer[offset] = 0xF4;
                return Ok(1);
            }
            Mnemonic::CLC => {
                buffer[offset] = 0xF8;
                return Ok(1);
            }
            Mnemonic::STC => {
                buffer[offset] = 0xF9;
                return Ok(1);
            }
            Mnemonic::CLI => {
                buffer[offset] = 0xFA;
                return Ok(1);
            }
            Mnemonic::STI => {
                buffer[offset] = 0xFB;
                return Ok(1);
            }
            Mnemonic::CLD => {
                buffer[offset] = 0xFC;
                return Ok(1);
            }
            Mnemonic::STD => {
                buffer[offset] = 0xFD;
                return Ok(1);
            }
            _ => {}
        }

        // Handle MOV reg, imm
        if request.mnemonic == Mnemonic::MOV && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Imm(imm))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_mov_reg_imm(*dst_reg, *imm, buffer);
            }
        }

        // Handle reg-reg MOV
        if request.mnemonic == Mnemonic::MOV && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Reg(src_reg))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_mov_reg_reg(*dst_reg, *src_reg, buffer);
            }
        }

        // Handle simple jumps
        if request.mnemonic == Mnemonic::JMP && request.operand_count == 1 {
            if let Some(EncoderOperand::Rel(offset)) = request.operand(0) {
                return self.encode_jmp_rel(*offset, buffer);
            }
        }

        // Handle conditional jumps
        if is_conditional_jump(request.mnemonic) && request.operand_count == 1 {
            if let Some(EncoderOperand::Rel(offset)) = request.operand(0) {
                return self.encode_jcc_rel(request.mnemonic, *offset, buffer);
            }
        }

        // Handle LEA
        if request.mnemonic == Mnemonic::LEA && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Mem(mem))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_lea(*dst_reg, mem, buffer);
            }
        }

        // Handle ALU reg, imm8 (sign-extended): ADD/SUB/CMP/AND/OR/XOR reg, imm
        if get_alu_opcode_extension(request.mnemonic).is_some() && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Imm(imm))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_alu_reg_imm(*dst_reg, *imm, request.mnemonic, buffer);
            }
        }

        // Handle ALU reg, reg: ADD/SUB/CMP/AND/OR/XOR reg, reg
        if get_alu_reg_reg_opcode(request.mnemonic).is_some() && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Reg(src_reg))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_alu_reg_reg(*dst_reg, *src_reg, request.mnemonic, buffer);
            }
        }

        // Handle PUSH reg (50+rd)
        if request.mnemonic == Mnemonic::PUSH && request.operand_count == 1 {
            if let Some(EncoderOperand::Reg(reg)) = request.operand(0) {
                return self.encode_push_pop_reg(*reg, true, buffer);
            }
        }

        // Handle POP reg (58+rd)
        if request.mnemonic == Mnemonic::POP && request.operand_count == 1 {
            if let Some(EncoderOperand::Reg(reg)) = request.operand(0) {
                return self.encode_push_pop_reg(*reg, false, buffer);
            }
        }

        // Handle shift instructions with CL: SHL/SHR/SAR reg, CL
        if matches!(
            request.mnemonic,
            Mnemonic::SHL | Mnemonic::SHR | Mnemonic::SAR | Mnemonic::SAL
        ) && request.operand_count == 2
        {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Reg(src_reg))) =
                (request.operand(0), request.operand(1))
            {
                // Check if src is CL
                if *src_reg == Register::CL {
                    return self.encode_shift_cl(*dst_reg, request.mnemonic, buffer);
                }
            }
        }

        // Handle AVX-512 instructions (EVEX prefix)
        // Check if this is an AVX-512 capable instruction with ZMM registers or mask/zeroing
        if is_avx512_capable_instruction(request.mnemonic) && request.operand_count == 3 {
            let has_zmm = request.has_zmm_operand();
            let has_mask = request.has_mask();
            let is_zeroing = request.is_zeroing();

            // Use EVEX if we have ZMM registers, mask register, or zeroing mode
            if has_zmm || has_mask || is_zeroing {
                if let (
                    Some(EncoderOperand::Reg(dst_reg)),
                    Some(EncoderOperand::Reg(src1_reg)),
                    Some(EncoderOperand::Reg(src2_reg)),
                ) = (request.operand(0), request.operand(1), request.operand(2))
                {
                    // AVX-512 reg, reg, reg form
                    return self.encode_avx512_reg_reg(
                        *dst_reg,
                        *src1_reg,
                        *src2_reg,
                        request.mnemonic,
                        request.mask_reg,
                        request.zeroing_mode,
                        buffer,
                    );
                }

                if let (
                    Some(EncoderOperand::Reg(dst_reg)),
                    Some(EncoderOperand::Reg(src1_reg)),
                    Some(EncoderOperand::Mem(mem)),
                ) = (request.operand(0), request.operand(1), request.operand(2))
                {
                    // AVX-512 reg, reg, mem form
                    return self.encode_avx512_reg_mem(
                        *dst_reg,
                        *src1_reg,
                        mem,
                        request.mnemonic,
                        request.mask_reg,
                        request.zeroing_mode,
                        buffer,
                    );
                }
            }
        }

        // Handle AVX instructions: VADDPS/VADDPD/VSUBPS/VSUBPD/VMULPS/VMULPD/VXORPS/VXORPD
        // Format: VEX.128.0F.WIG opcode /r
        // dst, src1, src2 (reg, reg, reg) or (reg, reg, mem)
        if is_avx_instruction(request.mnemonic) && request.operand_count == 3 {
            if let (
                Some(EncoderOperand::Reg(dst_reg)),
                Some(EncoderOperand::Reg(src1_reg)),
                Some(EncoderOperand::Reg(src2_reg)),
            ) = (request.operand(0), request.operand(1), request.operand(2))
            {
                // reg, reg, reg form
                return self.encode_avx_reg_reg(
                    *dst_reg,
                    *src1_reg,
                    *src2_reg,
                    request.mnemonic,
                    buffer,
                );
            }

            if let (
                Some(EncoderOperand::Reg(dst_reg)),
                Some(EncoderOperand::Reg(src1_reg)),
                Some(EncoderOperand::Mem(mem)),
            ) = (request.operand(0), request.operand(1), request.operand(2))
            {
                // reg, reg, mem form
                return self.encode_avx_reg_mem(*dst_reg, *src1_reg, mem, request.mnemonic, buffer);
            }
        }

        // Handle AVX instructions with 4 operands (reg, reg, reg/mem, imm8):
        // VSHUFPS, VSHUFPD, VPERM2I128
        if is_avx_instruction_with_imm8(request.mnemonic) && request.operand_count == 4 {
            if let (
                Some(EncoderOperand::Reg(dst_reg)),
                Some(EncoderOperand::Reg(src1_reg)),
                Some(EncoderOperand::Reg(src2_reg)),
                Some(EncoderOperand::Imm(imm8)),
            ) = (
                request.operand(0),
                request.operand(1),
                request.operand(2),
                request.operand(3),
            ) {
                // reg, reg, reg, imm8 form
                return self.encode_avx_reg_reg_imm8(
                    *dst_reg,
                    *src1_reg,
                    *src2_reg,
                    *imm8 as u8,
                    request.mnemonic,
                    buffer,
                );
            }

            if let (
                Some(EncoderOperand::Reg(dst_reg)),
                Some(EncoderOperand::Reg(src1_reg)),
                Some(EncoderOperand::Mem(mem)),
                Some(EncoderOperand::Imm(imm8)),
            ) = (
                request.operand(0),
                request.operand(1),
                request.operand(2),
                request.operand(3),
            ) {
                // reg, reg, mem, imm8 form
                return self.encode_avx_reg_mem_imm8(
                    *dst_reg,
                    *src1_reg,
                    mem,
                    *imm8 as u8,
                    request.mnemonic,
                    buffer,
                );
            }
        }

        // Handle VBROADCASTSS: dst, mem (2 operands)
        // VEX.128.0F38.WIG 18 /r
        if request.mnemonic == Mnemonic::VBROADCASTSS && request.operand_count == 2 {
            if let (Some(EncoderOperand::Reg(dst_reg)), Some(EncoderOperand::Mem(mem))) =
                (request.operand(0), request.operand(1))
            {
                return self.encode_avx_broadcast_mem(*dst_reg, mem, request.mnemonic, buffer);
            }
        }

        // Handle VEXTRACTF128: mem/xmm, ymm, imm8 (3 operands)
        // VEX.256.66.0F3A.WIG 19 /r ib
        if request.mnemonic == Mnemonic::VEXTRACTF128 && request.operand_count == 3 {
            if let (
                Some(EncoderOperand::Reg(dst_reg)),
                Some(EncoderOperand::Reg(src_reg)),
                Some(EncoderOperand::Imm(imm8)),
            ) = (request.operand(0), request.operand(1), request.operand(2))
            {
                // xmm/mem, ymm, imm8 form (here: reg, reg, imm8)
                return self.encode_avx_extractf128(*dst_reg, *src_reg, *imm8 as u8, buffer);
            }
        }

        // Not yet implemented
        Err(Error::NotYetImplemented(
            alloc::format!("encoding for {:?}", request.mnemonic).leak(),
        ))
    }

    /// Encode MOV reg, imm
    fn encode_mov_reg_imm(&self, reg: Register, imm: u64, buffer: &mut [u8]) -> Result<usize> {
        let mut offset = 0usize;
        let reg_size = reg.size();

        // Check for 8-bit register with 8-bit immediate
        if reg_size == 8 {
            let needs_rex = needs_rex_for_8bit(reg);

            if needs_rex {
                buffer[offset] = encode_rex(false, false, false, check_rex_b(reg));
                offset += 1;
            }

            buffer[offset] = get_mov_imm8_opcode(register_id(reg));
            offset += 1;
            buffer[offset] = imm as u8;
            offset += 1;

            return Ok(offset);
        }

        // For 16/32/64-bit registers
        // Determine if we need REX.W for 64-bit
        let needs_rex_w = reg_size == 64 && self.machine_mode == MachineMode::Long64;

        // Determine if we need 66h prefix for 16-bit
        let needs_66 = reg_size == 16;

        // Determine if we need REX.B for extended registers
        let needs_rex_b = check_rex_b(reg);

        // Emit prefix
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix if needed
        if needs_rex_w || needs_rex_b {
            buffer[offset] = encode_rex(needs_rex_w, false, false, needs_rex_b);
            offset += 1;
        }

        // Emit opcode
        buffer[offset] = get_mov_imm_opcode(register_id(reg), reg_size == 64);
        offset += 1;

        // Emit immediate
        let imm_size = if reg_size == 64 {
            8
        } else {
            (reg_size / 8) as usize
        };
        for i in 0..imm_size {
            buffer[offset + i] = ((imm >> (i * 8)) & 0xFF) as u8;
        }
        offset += imm_size;

        Ok(offset)
    }

    /// Encode MOV reg, reg
    fn encode_mov_reg_reg(&self, dst: Register, src: Register, buffer: &mut [u8]) -> Result<usize> {
        let mut offset = 0usize;
        let op_size = dst.size().max(src.size());

        // Validate operands have same size
        if dst.size() != src.size() {
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        // Prefixes
        let needs_66 = op_size == 16;
        let needs_rex_w = op_size == 64 && self.machine_mode == MachineMode::Long64;
        let rex_r = check_rex_r(src);
        let rex_b = check_rex_b(dst);

        // For 8-bit registers that need REX (SPL, BPL, SIL, DIL, R8B-R15B)
        let rex_for_8bit = op_size == 8 && (needs_rex_for_8bit(dst) || needs_rex_for_8bit(src));

        // Emit 66h prefix for 16-bit
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix
        if needs_rex_w || rex_r || rex_b || rex_for_8bit {
            buffer[offset] = encode_rex(needs_rex_w, rex_r, false, rex_b);
            offset += 1;
        }

        // Opcode: MOV r64, r/m64 is 8B /r
        buffer[offset] = 0x8B;
        offset += 1;

        // ModRM: mod=11 (register), reg=src, rm=dst
        buffer[offset] = encode_modrm(3, register_id(src), register_id(dst));
        offset += 1;

        Ok(offset)
    }

    /// Encode JMP rel
    fn encode_jmp_rel(&self, offset: i32, buffer: &mut [u8]) -> Result<usize> {
        let mut len = 0usize;

        // Use short jump if possible (-128 to +127)
        if (-128..=127).contains(&offset) {
            buffer[len] = 0xEB; // JMP rel8
            len += 1;
            buffer[len] = offset as i8 as u8;
            len += 1;
        } else {
            buffer[len] = 0xE9; // JMP rel32
            len += 1;
            buffer[len..len + 4].copy_from_slice(&offset.to_le_bytes());
            len += 4;
        }

        Ok(len)
    }

    /// Encode conditional jump (Jcc)
    fn encode_jcc_rel(&self, mnemonic: Mnemonic, offset: i32, buffer: &mut [u8]) -> Result<usize> {
        let condition = get_jcc_condition(mnemonic);
        let mut len = 0usize;

        // Use short jump if possible (-128 to +127)
        if (-128..=127).contains(&offset) {
            buffer[len] = 0x70 + condition; // Jcc rel8
            len += 1;
            buffer[len] = offset as i8 as u8;
            len += 1;
        } else {
            buffer[len] = 0x0F; // Two-byte Jcc
            len += 1;
            buffer[len] = 0x80 + condition;
            len += 1;
            buffer[len..len + 4].copy_from_slice(&offset.to_le_bytes());
            len += 4;
        }

        Ok(len)
    }

    /// Encode ALU reg, imm8 (sign-extended): ADD/SUB/CMP/AND/OR/XOR reg, imm
    /// Uses opcode 83 /n ib
    fn encode_alu_reg_imm(
        &self,
        reg: Register,
        imm: u64,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_size = reg.size();

        // Get the opcode extension for this ALU operation
        let opcode_ext = get_alu_opcode_extension(mnemonic)
            .ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Check if immediate fits in signed 8-bit
        // First truncate to u8, then check if it can be sign-extended properly
        // For the 83 /n ib form, the immediate is sign-extended to operand size
        // So we need to check if the value fits in a signed byte when interpreted as such
        let imm8 = imm as u8;
        let signed_imm = imm8 as i8 as i64;
        // The original value should be representable as a sign-extended imm8
        // This means imm should equal the sign-extended value when truncated to operand size
        // For simplicity, just check if imm's low byte gives the right sign extension
        if imm > 255 && imm != (signed_imm as u64) {
            // Value is too large and cannot be represented by sign-extending imm8
            return Err(Error::EncodeFailed(EncodeError::ImmediateOutOfRange));
        }

        // For 8-bit registers, we would need a different encoding (80 /n ib)
        if reg_size == 8 {
            // 80 /n ib for 8-bit operands
            let needs_rex = needs_rex_for_8bit(reg);

            if needs_rex {
                buffer[offset] = encode_rex(false, false, false, check_rex_b(reg));
                offset += 1;
            }

            buffer[offset] = 0x80; // 8-bit operand, no sign extension needed
            offset += 1;
            buffer[offset] = encode_modrm(3, opcode_ext, register_id(reg));
            offset += 1;
            buffer[offset] = imm as u8;
            offset += 1;

            return Ok(offset);
        }

        // For 16/32/64-bit registers
        let needs_rex_w = reg_size == 64 && self.machine_mode == MachineMode::Long64;
        let needs_66 = reg_size == 16;
        let needs_rex_b = check_rex_b(reg);

        // Emit 66h prefix for 16-bit
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix
        if needs_rex_w || needs_rex_b {
            buffer[offset] = encode_rex(needs_rex_w, false, false, needs_rex_b);
            offset += 1;
        }

        // Opcode: 83 /n ib (sign-extended imm8 to operand size)
        buffer[offset] = 0x83;
        offset += 1;

        // ModRM: mod=11 (register), reg=opcode_ext, rm=dst
        buffer[offset] = encode_modrm(3, opcode_ext, register_id(reg));
        offset += 1;

        // Immediate (imm8, sign-extended)
        buffer[offset] = imm as u8;
        offset += 1;

        Ok(offset)
    }

    /// Encode ALU reg, reg: ADD/SUB/CMP/AND/OR/XOR reg, reg
    /// Uses opcodes: ADD=01, SUB=29, AND=21, OR=09, XOR=31, CMP=39
    fn encode_alu_reg_reg(
        &self,
        dst: Register,
        src: Register,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let op_size = dst.size().max(src.size());

        // Validate operands have same size
        if dst.size() != src.size() {
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        // Get the opcode for this ALU operation
        let opcode = get_alu_reg_reg_opcode(mnemonic)
            .ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Prefixes
        let needs_66 = op_size == 16;
        let needs_rex_w = op_size == 64 && self.machine_mode == MachineMode::Long64;
        let rex_r = check_rex_r(src);
        let rex_b = check_rex_b(dst);

        // For 8-bit registers that need REX (SPL, BPL, SIL, DIL, R8B-R15B)
        let rex_for_8bit = op_size == 8 && (needs_rex_for_8bit(dst) || needs_rex_for_8bit(src));

        // Emit 66h prefix for 16-bit
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix
        if needs_rex_w || rex_r || rex_b || rex_for_8bit {
            buffer[offset] = encode_rex(needs_rex_w, rex_r, false, rex_b);
            offset += 1;
        }

        // Emit opcode
        buffer[offset] = opcode;
        offset += 1;

        // ModRM: mod=11 (register), reg=src, rm=dst
        buffer[offset] = encode_modrm(3, register_id(src), register_id(dst));
        offset += 1;

        Ok(offset)
    }

    /// Encode PUSH reg (50+rd for 64-bit, FF /6 for others)
    fn encode_push_pop_reg(
        &self,
        reg: Register,
        is_push: bool,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_size = reg.size();

        // For 64-bit registers in 64-bit mode, use short form (50+rd for push, 58+rd for pop)
        if reg_size == 64 && self.machine_mode == MachineMode::Long64 {
            let needs_rex_b = check_rex_b(reg);

            // Emit REX.B prefix if needed for R8-R15
            if needs_rex_b {
                buffer[offset] = encode_rex(false, false, false, true);
                offset += 1;
            }

            // Opcode: 50+rd for PUSH, 58+rd for POP
            buffer[offset] = if is_push {
                0x50 + register_id(reg)
            } else {
                0x58 + register_id(reg)
            };
            offset += 1;

            return Ok(offset);
        }

        // For other sizes, use FF /6 (PUSH) or 8F /0 (POP)
        let needs_66 = reg_size == 16;
        let needs_rex_w = reg_size == 64;
        let needs_rex_b = check_rex_b(reg);

        // Emit 66h prefix for 16-bit
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix
        if needs_rex_w || needs_rex_b {
            buffer[offset] = encode_rex(needs_rex_w, false, false, needs_rex_b);
            offset += 1;
        }

        // Opcode and ModRM
        if is_push {
            buffer[offset] = 0xFF; // PUSH r/m
            offset += 1;
            buffer[offset] = encode_modrm(3, 6, register_id(reg)); // /6
            offset += 1;
        } else {
            buffer[offset] = 0x8F; // POP r/m
            offset += 1;
            buffer[offset] = encode_modrm(3, 0, register_id(reg)); // /0
            offset += 1;
        }

        Ok(offset)
    }

    /// Encode shift instructions with CL: SHL/SHR/SAR reg, CL
    /// Uses opcode D3 /n (for 16/32/64-bit) or D2 /n (for 8-bit)
    fn encode_shift_cl(
        &self,
        reg: Register,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_size = reg.size();

        // Get the opcode extension for shift operations
        let opcode_ext = match mnemonic {
            Mnemonic::SHL | Mnemonic::SAL => 4,
            Mnemonic::SHR => 5,
            Mnemonic::SAR => 7,
            _ => return Err(Error::EncodeFailed(EncodeError::InvalidMnemonic)),
        };

        let needs_66 = reg_size == 16;
        let needs_rex_w = reg_size == 64 && self.machine_mode == MachineMode::Long64;
        let needs_rex_b = check_rex_b(reg);

        // For 8-bit registers that need REX
        let rex_for_8bit = reg_size == 8 && needs_rex_for_8bit(reg);

        // Emit 66h prefix for 16-bit
        if needs_66 {
            buffer[offset] = 0x66;
            offset += 1;
        }

        // Emit REX prefix
        if needs_rex_w || needs_rex_b || rex_for_8bit {
            buffer[offset] = encode_rex(needs_rex_w, false, false, needs_rex_b);
            offset += 1;
        }

        // Opcode: D0 (8-bit, 1), D1 (16/32/64-bit, 1), D2 (8-bit, CL), D3 (16/32/64-bit, CL)
        buffer[offset] = if reg_size == 8 { 0xD2 } else { 0xD3 };
        offset += 1;

        // ModRM: mod=11 (register), reg=opcode_ext, rm=dst
        buffer[offset] = encode_modrm(3, opcode_ext, register_id(reg));
        offset += 1;

        Ok(offset)
    }

    /// Encode LEA
    fn encode_lea(&self, dst: Register, mem: &MemoryOperand, buffer: &mut [u8]) -> Result<usize> {
        let mut offset = 0usize;

        // Determine address size
        let addr_size = if mem.base != Register::None {
            mem.base.size()
        } else if mem.index != Register::None {
            mem.index.size()
        } else {
            64 // Default to 64-bit addressing
        };

        // Segment override prefix (must come before other prefixes)
        if mem.segment != Register::None && mem.segment != Register::DS {
            let seg_prefix = segment_override_prefix(mem.segment);
            if seg_prefix != 0 {
                buffer[offset] = seg_prefix;
                offset += 1;
            }
        }

        // REX prefix calculation
        let needs_rex_w = dst.size() == 64;
        let rex_r = check_rex_r(dst);
        let rex_b = mem.base != Register::None && check_rex_b(mem.base);
        let rex_x = mem.index != Register::None && check_rex_r(mem.index);

        // Address size override for 32-bit addressing in 64-bit mode
        if addr_size == 32 && self.machine_mode == MachineMode::Long64 {
            buffer[offset] = 0x67;
            offset += 1;
        }

        // REX prefix
        if needs_rex_w || rex_r || rex_x || rex_b {
            buffer[offset] = encode_rex(needs_rex_w, rex_r, rex_x, rex_b);
            offset += 1;
        }

        // Opcode: LEA r64, m
        buffer[offset] = 0x8D;
        offset += 1;

        // Encode ModRM and SIB
        offset += self.encode_memory_operand(dst, mem, &mut buffer[offset..])?;

        Ok(offset)
    }

    /// Encode a memory operand (ModRM + SIB + displacement)
    ///
    /// Supports:
    /// - Base + disp8/disp32
    /// - Base + Index + Scale + disp
    /// - RIP-relative addressing
    /// - Absolute addressing via SIB
    /// - Segment override (must be added before calling this method)
    fn encode_memory_operand(
        &self,
        reg: Register,
        mem: &MemoryOperand,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_id = register_id(reg);
        let base_id = if mem.base != Register::None {
            register_id(mem.base)
        } else {
            0
        };
        let index_id = if mem.index != Register::None {
            register_id(mem.index)
        } else {
            0
        };

        // RIP-relative addressing: [RIP + disp32]
        if mem.is_rip_relative() {
            buffer[offset] = encode_modrm(0, reg_id, 5);
            offset += 1;
            buffer[offset..offset + 4].copy_from_slice(&(mem.displacement as i32).to_le_bytes());
            offset += 4;
            return Ok(offset);
        }

        // No base register - absolute addressing
        if mem.base == Register::None {
            if mem.index != Register::None {
                // [index*scale + disp32] - SIB with no base
                // Check for invalid index (RSP/ESP/SP/R12/R12D/R12W cannot be index)
                if is_stack_register(mem.index) {
                    return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
                }
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(mem.scale, index_id, 5); // base=5 means disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            } else {
                // Pure displacement [disp32] - use SIB with no index, base=5
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(1, 4, 5); // no index (index=4), base=5 for disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            return Ok(offset);
        }

        // Has base register
        // Check for invalid index (RSP/ESP/SP/R12/R12D/R12W cannot be used as index)
        if mem.index != Register::None && is_stack_register(mem.index) {
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        let needs_sib = mem.requires_sib();
        let disp_size = displacement_size(mem.displacement);

        // Check if base is RBP/R13 family (requires displacement)
        let base_is_rbp = is_rbp_family(mem.base);

        // For RBP/R13 without displacement, we need to add a disp8 of 0
        let effective_disp_size = if base_is_rbp && disp_size == 0 {
            1 // Force disp8 with value 0
        } else {
            disp_size
        };

        // Determine mod field
        let mod_val = match effective_disp_size {
            0 => 0,
            1 => 1,
            _ => 2,
        };

        if needs_sib {
            // ModRM with SIB
            buffer[offset] = encode_modrm(mod_val, reg_id, 4); // rm=4 means SIB follows
            offset += 1;

            // SIB byte
            // Special case: if base is RBP/R13 and no displacement, use base=5 in SIB
            // but the actual displacement will be encoded as disp8=0
            let sib_base = if base_is_rbp && disp_size == 0 {
                5 // Will use disp8 encoded below
            } else {
                base_id
            };
            buffer[offset] = encode_sib(mem.scale, index_id, sib_base);
            offset += 1;
        } else {
            // Simple ModRM without SIB
            // Special case: [RBP/R13] is encoded as mod=01, rm=101 with disp8
            if base_is_rbp && disp_size == 0 {
                buffer[offset] = encode_modrm(1, reg_id, 5); // mod=01, rm=101
            } else {
                buffer[offset] = encode_modrm(mod_val, reg_id, base_id);
            }
            offset += 1;
        }

        // Displacement
        match effective_disp_size {
            1 => {
                buffer[offset] = mem.displacement as i8 as u8;
                offset += 1;
            }
            2 => {
                buffer[offset..offset + 2]
                    .copy_from_slice(&(mem.displacement as i16).to_le_bytes());
                offset += 2;
            }
            4 | 8 => {
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            _ => {}
        }

        Ok(offset)
    }

    /// Encode AVX reg, reg instruction (VEX.128.0F.WIG opcode /r)
    ///
    /// Format: VEX + opcode + ModRM
    /// For instructions like VADDPS xmm1, xmm2, xmm3:
    /// - xmm1 is encoded in vvvv field (inverted)
    /// - xmm2 is encoded in ModRM.reg field
    /// - xmm3 is encoded in ModRM.rm field (mod=11)
    fn encode_avx_reg_reg(
        &self,
        dst: Register,
        src1: Register,
        src2: Register,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Convert opcode map
        let vex_map = match avx_info.opcode_map {
            AvxOpcodeMap::Map0F => vex::VexOpcodeMap::Map0F,
            AvxOpcodeMap::Map0F38 => vex::VexOpcodeMap::Map0F38,
            AvxOpcodeMap::Map0F3A => vex::VexOpcodeMap::Map0F3A,
        };

        // Build VEX info
        let vex_info = VexInfo::new()
            .with_map(vex_map)
            .with_prefix(avx_info.vex_prefix)
            .with_128bit()
            .with_vvvv(dst); // dst goes into vvvv field

        // Encode VEX prefix
        let vex_bytes = vex::encode_vex(&vex_info, Some(src1), Some(src2), None);
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Emit ModRM: mod=11 (register), reg=src1, rm=src2
        buffer[offset] = encode_modrm(3, register_id(src1), register_id(src2));
        offset += 1;

        // Emit imm8 if required
        if avx_info.has_imm8 {
            // For 3-operand AVX instructions with imm8, we don't emit here
            // This is handled by encode_avx_reg_reg_imm8
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        Ok(offset)
    }

    /// Encode AVX reg, mem instruction (VEX.128.0F.WIG opcode /r)
    ///
    /// Format: VEX + opcode + ModRM [+ SIB + displacement]
    fn encode_avx_reg_mem(
        &self,
        dst: Register,
        src1: Register,
        mem: &MemoryOperand,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Convert opcode map
        let vex_map = match avx_info.opcode_map {
            AvxOpcodeMap::Map0F => vex::VexOpcodeMap::Map0F,
            AvxOpcodeMap::Map0F38 => vex::VexOpcodeMap::Map0F38,
            AvxOpcodeMap::Map0F3A => vex::VexOpcodeMap::Map0F3A,
        };

        // Build VEX info
        let vex_info = VexInfo::new()
            .with_map(vex_map)
            .with_prefix(avx_info.vex_prefix)
            .with_128bit()
            .with_vvvv(dst); // dst goes into vvvv field

        // Encode VEX prefix
        let vex_bytes = vex::encode_vex(&vex_info, Some(src1), Some(mem.base), Some(mem.index));
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Encode ModRM and memory operand
        // src1 goes into ModRM.reg field, mem operand into rm field
        offset += self.encode_avx_memory_operand(src1, mem, &mut buffer[offset..])?;

        Ok(offset)
    }

    /// Encode AVX reg, reg, reg, imm8 instruction
    /// For instructions like VSHUFPS xmm1, xmm2, xmm3, imm8
    fn encode_avx_reg_reg_imm8(
        &self,
        dst: Register,
        src1: Register,
        src2: Register,
        imm8: u8,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Convert opcode map
        let vex_map = match avx_info.opcode_map {
            AvxOpcodeMap::Map0F => vex::VexOpcodeMap::Map0F,
            AvxOpcodeMap::Map0F38 => vex::VexOpcodeMap::Map0F38,
            AvxOpcodeMap::Map0F3A => vex::VexOpcodeMap::Map0F3A,
        };

        // Determine vector length based on register type and instruction
        let vector_length = if matches!(mnemonic, Mnemonic::VPERM2I128) {
            // VPERM2I128 requires 256-bit (YMM) registers
            vex::VexVectorLength::L256
        } else {
            vex::VexVectorLength::L128
        };

        // Build VEX info
        let vex_info = VexInfo::new()
            .with_map(vex_map)
            .with_prefix(avx_info.vex_prefix)
            .with_vector_length(vector_length)
            .with_vvvv(dst);

        // Encode VEX prefix
        let vex_bytes = vex::encode_vex(&vex_info, Some(src1), Some(src2), None);
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Emit ModRM: mod=11 (register), reg=src1, rm=src2
        buffer[offset] = encode_modrm(3, register_id(src1), register_id(src2));
        offset += 1;

        // Emit imm8
        buffer[offset] = imm8;
        offset += 1;

        Ok(offset)
    }

    /// Encode AVX reg, reg, mem, imm8 instruction
    /// For instructions like VSHUFPS xmm1, xmm2, [mem], imm8
    fn encode_avx_reg_mem_imm8(
        &self,
        dst: Register,
        src1: Register,
        mem: &MemoryOperand,
        imm8: u8,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Convert opcode map
        let vex_map = match avx_info.opcode_map {
            AvxOpcodeMap::Map0F => vex::VexOpcodeMap::Map0F,
            AvxOpcodeMap::Map0F38 => vex::VexOpcodeMap::Map0F38,
            AvxOpcodeMap::Map0F3A => vex::VexOpcodeMap::Map0F3A,
        };

        // Build VEX info
        let vex_info = VexInfo::new()
            .with_map(vex_map)
            .with_prefix(avx_info.vex_prefix)
            .with_128bit()
            .with_vvvv(dst);

        // Encode VEX prefix
        let vex_bytes = vex::encode_vex(&vex_info, Some(src1), Some(mem.base), Some(mem.index));
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Encode ModRM and memory operand
        offset += self.encode_avx_memory_operand(src1, mem, &mut buffer[offset..])?;

        // Emit imm8
        buffer[offset] = imm8;
        offset += 1;

        Ok(offset)
    }

    /// Encode VBROADCASTSS instruction
    /// VEX.128.0F38.WIG 18 /r
    fn encode_avx_broadcast_mem(
        &self,
        dst: Register,
        mem: &MemoryOperand,
        mnemonic: Mnemonic,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Build VEX info - VBROADCASTSS uses Map0F38
        let vex_info = VexInfo::new()
            .with_map(vex::VexOpcodeMap::Map0F38)
            .with_prefix(avx_info.vex_prefix)
            .with_128bit();
        // No vvvv field for VBROADCASTSS

        // Encode VEX prefix
        let vex_bytes = vex::encode_vex(&vex_info, Some(dst), Some(mem.base), Some(mem.index));
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Encode ModRM and memory operand
        // dst goes into ModRM.reg field
        offset += self.encode_avx_memory_operand(dst, mem, &mut buffer[offset..])?;

        Ok(offset)
    }

    /// Encode VEXTRACTF128 instruction
    /// VEX.256.66.0F3A.WIG 19 /r ib
    fn encode_avx_extractf128(
        &self,
        dst: Register,
        src: Register,
        imm8: u8,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info = get_avx_opcode(Mnemonic::VEXTRACTF128)
            .ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Build VEX info - VEXTRACTF128 uses Map0F3A with 256-bit source
        let vex_info = VexInfo::new()
            .with_map(vex::VexOpcodeMap::Map0F3A)
            .with_prefix(avx_info.vex_prefix)
            .with_256bit();
        // No vvvv field for VEXTRACTF128

        // Encode VEX prefix - src (YMM) goes in reg field
        let vex_bytes = vex::encode_vex(&vex_info, Some(src), Some(dst), None);
        buffer[offset..offset + vex_bytes.len()].copy_from_slice(&vex_bytes);
        offset += vex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Emit ModRM: mod=11 (register), reg=src (YMM), rm=dst (XMM)
        buffer[offset] = encode_modrm(3, register_id(src), register_id(dst));
        offset += 1;

        // Emit imm8
        buffer[offset] = imm8;
        offset += 1;

        Ok(offset)
    }

    /// Encode AVX memory operand (ModRM + SIB + displacement)
    /// Similar to encode_memory_operand but for AVX instructions
    fn encode_avx_memory_operand(
        &self,
        reg: Register,
        mem: &MemoryOperand,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_id = register_id(reg);
        let base_id = if mem.base != Register::None {
            register_id(mem.base)
        } else {
            0
        };
        let index_id = if mem.index != Register::None {
            register_id(mem.index)
        } else {
            0
        };

        // RIP-relative addressing: [RIP + disp32]
        if mem.is_rip_relative() {
            buffer[offset] = encode_modrm(0, reg_id, 5);
            offset += 1;
            buffer[offset..offset + 4].copy_from_slice(&(mem.displacement as i32).to_le_bytes());
            offset += 4;
            return Ok(offset);
        }

        // No base register - absolute addressing
        if mem.base == Register::None {
            if mem.index != Register::None {
                // [index*scale + disp32] - SIB with no base
                if is_stack_register(mem.index) {
                    return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
                }
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(mem.scale, index_id, 5); // base=5 means disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            } else {
                // Pure displacement [disp32] - use SIB with no index, base=5
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(1, 4, 5); // no index (index=4), base=5 for disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            return Ok(offset);
        }

        // Has base register
        if mem.index != Register::None && is_stack_register(mem.index) {
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        let needs_sib = mem.requires_sib();
        let disp_size = displacement_size(mem.displacement);

        // Check if base is RBP/R13 family (requires displacement)
        let base_is_rbp = is_rbp_family(mem.base);

        // For RBP/R13 without displacement, we need to add a disp8 of 0
        let effective_disp_size = if base_is_rbp && disp_size == 0 {
            1 // Force disp8 with value 0
        } else {
            disp_size
        };

        // Determine mod field
        let mod_val = match effective_disp_size {
            0 => 0,
            1 => 1,
            _ => 2,
        };

        if needs_sib {
            // ModRM with SIB
            buffer[offset] = encode_modrm(mod_val, reg_id, 4); // rm=4 means SIB follows
            offset += 1;

            let sib_base = if base_is_rbp && disp_size == 0 {
                5 // Will use disp8 encoded below
            } else {
                base_id
            };
            buffer[offset] = encode_sib(mem.scale, index_id, sib_base);
            offset += 1;
        } else {
            // Simple ModRM without SIB
            if base_is_rbp && disp_size == 0 {
                buffer[offset] = encode_modrm(1, reg_id, 5); // mod=01, rm=101
            } else {
                buffer[offset] = encode_modrm(mod_val, reg_id, base_id);
            }
            offset += 1;
        }

        // Displacement
        match effective_disp_size {
            1 => {
                buffer[offset] = mem.displacement as i8 as u8;
                offset += 1;
            }
            2 => {
                buffer[offset..offset + 2]
                    .copy_from_slice(&(mem.displacement as i16).to_le_bytes());
                offset += 2;
            }
            4 | 8 => {
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            _ => {}
        }

        Ok(offset)
    }

    /// Encode AVX-512 reg, reg instruction (EVEX-encoded)
    ///
    /// Format: EVEX + opcode + ModRM
    /// For instructions like VADDPS.Z zmm1, zmm2, zmm3:
    /// - zmm1 is encoded in vvvv field
    /// - zmm2 is encoded in ModRM.reg field
    /// - zmm3 is encoded in ModRM.rm field (mod=11)
    #[allow(clippy::too_many_arguments)]
    fn encode_avx512_reg_reg(
        &self,
        dst: Register,
        src1: Register,
        src2: Register,
        mnemonic: Mnemonic,
        mask_reg: Option<Register>,
        zeroing: evex::EvexZeroingMode,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info (EVEX uses same opcodes as VEX for these instructions)
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Determine vector length based on register type
        let vector_length = if dst.is_zmm() || src1.is_zmm() || src2.is_zmm() {
            EvexVectorLength::L512
        } else if dst.is_ymm() || src1.is_ymm() || src2.is_ymm() {
            EvexVectorLength::L256
        } else {
            EvexVectorLength::L128
        };

        // Convert VEX prefix to EVEX prefix
        let evex_prefix = match avx_info.vex_prefix {
            vex::VexPrefix::None => EvexPrefix::None,
            vex::VexPrefix::Prefix66 => EvexPrefix::Prefix66,
            vex::VexPrefix::PrefixF3 => EvexPrefix::PrefixF3,
            vex::VexPrefix::PrefixF2 => EvexPrefix::PrefixF2,
        };

        // Build EVEX info
        let evex_info = EvexInfo::new()
            .with_map(EvexOpcodeMap::Map0F)
            .with_prefix(evex_prefix)
            .with_vvvv(dst)
            .with_mask_opt(mask_reg)
            .with_zeroing(zeroing);

        // Set vector length
        let evex_info = match vector_length {
            EvexVectorLength::L128 => evex_info.with_128bit(),
            EvexVectorLength::L256 => evex_info.with_256bit(),
            EvexVectorLength::L512 => evex_info.with_512bit(),
        };

        // Encode EVEX prefix
        let evex_bytes = evex::encode_evex(&evex_info, Some(src1), None, Some(src2));
        buffer[offset..offset + evex_bytes.len()].copy_from_slice(&evex_bytes);
        offset += evex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Emit ModRM: mod=11 (register), reg=src1, rm=src2
        // For EVEX, we use evex_register_id to handle extended registers
        buffer[offset] = encode_modrm(
            3,
            evex::evex_register_id(src1),
            evex::evex_register_id(src2),
        );
        offset += 1;

        Ok(offset)
    }

    /// Encode AVX-512 reg, mem instruction (EVEX-encoded)
    ///
    /// Format: EVEX + opcode + ModRM [+ SIB + displacement]
    #[allow(clippy::too_many_arguments)]
    fn encode_avx512_reg_mem(
        &self,
        dst: Register,
        src1: Register,
        mem: &MemoryOperand,
        mnemonic: Mnemonic,
        mask_reg: Option<Register>,
        zeroing: evex::EvexZeroingMode,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;

        // Get AVX opcode info
        let avx_info =
            get_avx_opcode(mnemonic).ok_or(Error::EncodeFailed(EncodeError::InvalidMnemonic))?;

        // Determine vector length based on register type
        let vector_length = if dst.is_zmm() || src1.is_zmm() {
            EvexVectorLength::L512
        } else if dst.is_ymm() || src1.is_ymm() {
            EvexVectorLength::L256
        } else {
            EvexVectorLength::L128
        };

        // Convert VEX prefix to EVEX prefix
        let evex_prefix = match avx_info.vex_prefix {
            vex::VexPrefix::None => EvexPrefix::None,
            vex::VexPrefix::Prefix66 => EvexPrefix::Prefix66,
            vex::VexPrefix::PrefixF3 => EvexPrefix::PrefixF3,
            vex::VexPrefix::PrefixF2 => EvexPrefix::PrefixF2,
        };

        // Build EVEX info
        let evex_info = EvexInfo::new()
            .with_map(EvexOpcodeMap::Map0F)
            .with_prefix(evex_prefix)
            .with_vvvv(dst)
            .with_mask_opt(mask_reg)
            .with_zeroing(zeroing);

        // Set vector length
        let evex_info = match vector_length {
            EvexVectorLength::L128 => evex_info.with_128bit(),
            EvexVectorLength::L256 => evex_info.with_256bit(),
            EvexVectorLength::L512 => evex_info.with_512bit(),
        };

        // Encode EVEX prefix
        let evex_bytes = evex::encode_evex(&evex_info, Some(src1), Some(mem.index), Some(mem.base));
        buffer[offset..offset + evex_bytes.len()].copy_from_slice(&evex_bytes);
        offset += evex_bytes.len();

        // Emit opcode
        buffer[offset] = avx_info.opcode;
        offset += 1;

        // Encode ModRM and memory operand
        offset += self.encode_avx512_memory_operand(src1, mem, &mut buffer[offset..])?;

        Ok(offset)
    }

    /// Encode AVX-512 memory operand (ModRM + SIB + displacement)
    /// Similar to encode_avx_memory_operand but uses EVEX register encoding
    fn encode_avx512_memory_operand(
        &self,
        reg: Register,
        mem: &MemoryOperand,
        buffer: &mut [u8],
    ) -> Result<usize> {
        let mut offset = 0usize;
        let reg_id = evex::evex_register_id(reg);
        let base_id = if mem.base != Register::None {
            evex::evex_register_id(mem.base)
        } else {
            0
        };
        let index_id = if mem.index != Register::None {
            evex::evex_register_id(mem.index)
        } else {
            0
        };

        // RIP-relative addressing: [RIP + disp32]
        if mem.is_rip_relative() {
            buffer[offset] = encode_modrm(0, reg_id, 5);
            offset += 1;
            buffer[offset..offset + 4].copy_from_slice(&(mem.displacement as i32).to_le_bytes());
            offset += 4;
            return Ok(offset);
        }

        // No base register - absolute addressing
        if mem.base == Register::None {
            if mem.index != Register::None {
                // [index*scale + disp32] - SIB with no base
                if is_stack_register(mem.index) {
                    return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
                }
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(mem.scale, index_id, 5); // base=5 means disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            } else {
                // Pure displacement [disp32] - use SIB with no index, base=5
                buffer[offset] = encode_modrm(0, reg_id, 4); // rm=4 means SIB follows
                offset += 1;
                buffer[offset] = encode_sib(1, 4, 5); // no index (index=4), base=5 for disp32
                offset += 1;
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            return Ok(offset);
        }

        // Has base register
        if mem.index != Register::None && is_stack_register(mem.index) {
            return Err(Error::EncodeFailed(EncodeError::InvalidOperandCombination));
        }

        let needs_sib = mem.requires_sib();
        let disp_size = displacement_size(mem.displacement);

        // Check if base is RBP/R13 family (requires displacement)
        let base_is_rbp = is_rbp_family(mem.base);

        // For RBP/R13 without displacement, we need to add a disp8 of 0
        let effective_disp_size = if base_is_rbp && disp_size == 0 {
            1 // Force disp8 with value 0
        } else {
            disp_size
        };

        // Determine mod field
        let mod_val = match effective_disp_size {
            0 => 0,
            1 => 1,
            _ => 2,
        };

        if needs_sib {
            // ModRM with SIB
            buffer[offset] = encode_modrm(mod_val, reg_id, 4); // rm=4 means SIB follows
            offset += 1;

            let sib_base = if base_is_rbp && disp_size == 0 {
                5 // Will use disp8 encoded below
            } else {
                base_id
            };
            buffer[offset] = encode_sib(mem.scale, index_id, sib_base);
            offset += 1;
        } else {
            // Simple ModRM without SIB
            if base_is_rbp && disp_size == 0 {
                buffer[offset] = encode_modrm(1, reg_id, 5); // mod=01, rm=101
            } else {
                buffer[offset] = encode_modrm(mod_val, reg_id, base_id);
            }
            offset += 1;
        }

        // Displacement
        match effective_disp_size {
            1 => {
                buffer[offset] = mem.displacement as i8 as u8;
                offset += 1;
            }
            2 => {
                buffer[offset..offset + 2]
                    .copy_from_slice(&(mem.displacement as i16).to_le_bytes());
                offset += 2;
            }
            4 | 8 => {
                buffer[offset..offset + 4]
                    .copy_from_slice(&(mem.displacement as i32).to_le_bytes());
                offset += 4;
            }
            _ => {}
        }

        Ok(offset)
    }
}

/// Check if a register is a stack pointer register (cannot be used as index)
fn is_stack_register(reg: Register) -> bool {
    matches!(
        reg,
        Register::RSP
            | Register::ESP
            | Register::SP
            | Register::R12
            | Register::R12D
            | Register::R12W
    )
}

/// Check if a register is RBP/R13 family (requires displacement)
fn is_rbp_family(reg: Register) -> bool {
    matches!(
        reg,
        Register::RBP
            | Register::R13
            | Register::EBP
            | Register::R13D
            | Register::BP
            | Register::R13W
    )
}

/// Check if a mnemonic is a conditional jump
fn is_conditional_jump(mnemonic: Mnemonic) -> bool {
    matches!(
        mnemonic,
        Mnemonic::JO
            | Mnemonic::JNO
            | Mnemonic::JB
            | Mnemonic::JNB
            | Mnemonic::JAE
            | Mnemonic::JZ
            | Mnemonic::JE
            | Mnemonic::JNZ
            | Mnemonic::JNE
            | Mnemonic::JBE
            | Mnemonic::JNG
            | Mnemonic::JS
            | Mnemonic::JNS
            | Mnemonic::JP
            | Mnemonic::JNP
            | Mnemonic::JPE
            | Mnemonic::JPO
            | Mnemonic::JC
            | Mnemonic::JNC
            | Mnemonic::JL
            | Mnemonic::JGE
            | Mnemonic::JLE
            | Mnemonic::JG
            | Mnemonic::JNL
    )
}

/// Get the condition code for a conditional jump
fn get_jcc_condition(mnemonic: Mnemonic) -> u8 {
    match mnemonic {
        Mnemonic::JO => 0,
        Mnemonic::JNO => 1,
        Mnemonic::JB | Mnemonic::JC => 2, // JB = JC = JNAE
        Mnemonic::JNB | Mnemonic::JAE | Mnemonic::JNC | Mnemonic::JNL => 3, // JNB = JAE = JNC
        Mnemonic::JZ | Mnemonic::JE => 4,
        Mnemonic::JNZ | Mnemonic::JNE => 5,
        Mnemonic::JBE | Mnemonic::JNG => 6, // JBE = JNG
        // JA not in enum, use 7 for "above" condition
        Mnemonic::JS => 8,
        Mnemonic::JNS => 9,
        Mnemonic::JP | Mnemonic::JPE => 10,
        Mnemonic::JNP | Mnemonic::JPO => 11,
        Mnemonic::JL => 12,
        Mnemonic::JGE => 13,
        Mnemonic::JLE => 14,
        Mnemonic::JG => 15,
        _ => 0,
    }
}

impl Default for Encoder {
    fn default() -> Self {
        Self::new(MachineMode::Long64, 64).unwrap()
    }
}

#[cfg(test)]
mod tests {
    use super::*;
    use alloc::vec;

    #[test]
    fn test_encoder_new() {
        let encoder = Encoder::new(MachineMode::Long64, 64);
        assert!(encoder.is_ok());

        let encoder = encoder.unwrap();
        assert_eq!(encoder.machine_mode(), MachineMode::Long64);
        assert_eq!(encoder.stack_width(), 64);
    }

    #[test]
    fn test_encoder_invalid_stack_width() {
        let encoder = Encoder::new(MachineMode::Long64, 128);
        assert!(encoder.is_err());
    }

    #[test]
    fn test_encoder_default() {
        let encoder = Encoder::default();
        assert_eq!(encoder.machine_mode(), MachineMode::Long64);
        assert_eq!(encoder.stack_width(), 64);
    }

    // ========================================
    // Memory operand encoding tests
    // ========================================

    #[test]
    fn test_encode_lea_rip_relative() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RIP + 0x1000]
        let mem = MemoryOperand::base_disp(Register::RIP, 0x1000);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Should be: 48 8D 05 00 10 00 00
        assert_eq!(bytes[0], 0x48); // REX.W
        assert_eq!(bytes[1], 0x8D); // LEA
        // ModRM: mod=00, reg=000 (RAX), rm=101 (RIP-relative)
        assert_eq!(bytes[2] & 0xC7, 0x05); // mod=00, reg=000, rm=101
        // Check displacement (little-endian)
        assert_eq!(bytes[3], 0x00);
        assert_eq!(bytes[4], 0x10);
        assert_eq!(bytes[5], 0x00);
        assert_eq!(bytes[6], 0x00);
    }

    #[test]
    fn test_encode_lea_sib() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RAX + RCX*4 + 0x10]
        let mem = MemoryOperand::full(Register::DS, Register::RAX, Register::RCX, 4, 0x10);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Verify encoding contains SIB byte
        assert!(bytes.len() >= 5); // REX + opcode + ModRM + SIB + disp8
        assert_eq!(bytes[0], 0x48); // REX.W
        assert_eq!(bytes[1], 0x8D); // LEA
        // ModRM should indicate SIB follows
        assert_eq!(bytes[2] & 0x07, 0x04); // rm=4 means SIB
    }

    #[test]
    fn test_encode_lea_base_disp() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RBP - 16]
        let mem = MemoryOperand::base_disp(Register::RBP, -16);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // RBP requires SIB in 64-bit mode
        assert!(bytes.len() >= 4); // REX + opcode + ModRM + SIB + disp8
        assert_eq!(bytes[0], 0x48); // REX.W
        assert_eq!(bytes[1], 0x8D); // LEA
    }

    #[test]
    fn test_encode_lea_rsp_base() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RSP + 8]
        let mem = MemoryOperand::base_disp(Register::RSP, 8);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // RSP requires SIB
        assert!(bytes.len() >= 5); // REX + opcode + ModRM + SIB + disp8
        assert_eq!(bytes[0], 0x48); // REX.W
        assert_eq!(bytes[1], 0x8D); // LEA
        // ModRM should indicate SIB follows
        assert_eq!(bytes[2] & 0x07, 0x04); // rm=4 means SIB
    }

    #[test]
    fn test_encode_segment_override() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, FS:[0x1000] - using segment override
        let mem = MemoryOperand::base_disp(Register::None, 0x1000).with_segment(Register::FS);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Should start with FS segment override prefix (0x64)
        assert_eq!(bytes[0], 0x64); // FS segment override
    }

    #[test]
    fn test_encode_lea_gs_segment() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, GS:[RCX]
        let mem = MemoryOperand::base(Register::RCX).with_segment(Register::GS);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Should start with GS segment override prefix (0x65)
        assert_eq!(bytes[0], 0x65); // GS segment override
    }

    #[test]
    fn test_encode_absolute_addressing() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [0x12345678] - absolute address
        let mem = MemoryOperand::base_disp(Register::None, 0x12345678);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Should use SIB with base=5 for absolute addressing
        assert!(bytes.len() >= 8); // REX + opcode + ModRM + SIB + disp32
        assert_eq!(bytes[2] & 0x07, 0x04); // rm=4 means SIB follows
    }

    #[test]
    fn test_encode_index_scale_no_base() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RCX*4 + 0x1000] - index with scale, no base
        let mem = MemoryOperand::full(Register::DS, Register::None, Register::RCX, 4, 0x1000);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        // Should use SIB with base=5 for disp32
        assert!(bytes.len() >= 8); // REX + opcode + ModRM + SIB + disp32
    }

    #[test]
    fn test_encode_invalid_rsp_index() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // LEA RAX, [RAX + RSP*4] - RSP cannot be index, should fail
        let mem = MemoryOperand::full(Register::DS, Register::RAX, Register::RSP, 4, 0);
        let request = EncoderRequest::new(Mnemonic::LEA)
            .with_reg(Register::RAX)
            .with_mem(mem);
        let result = encoder.encode(&request);

        // Should return error for invalid operand combination
        assert!(result.is_err());
    }

    #[test]
    fn test_is_stack_register() {
        assert!(is_stack_register(Register::RSP));
        assert!(is_stack_register(Register::ESP));
        assert!(is_stack_register(Register::SP));
        assert!(is_stack_register(Register::R12));
        assert!(is_stack_register(Register::R12D));
        assert!(is_stack_register(Register::R12W));
        assert!(!is_stack_register(Register::RAX));
        assert!(!is_stack_register(Register::RCX));
    }

    #[test]
    fn test_is_rbp_family() {
        assert!(is_rbp_family(Register::RBP));
        assert!(is_rbp_family(Register::R13));
        assert!(is_rbp_family(Register::EBP));
        assert!(is_rbp_family(Register::R13D));
        assert!(is_rbp_family(Register::BP));
        assert!(is_rbp_family(Register::R13W));
        assert!(!is_rbp_family(Register::RAX));
        assert!(!is_rbp_family(Register::RSP));
    }

    // ========================================
    // ALU instruction encoding tests
    // ========================================

    #[test]
    fn test_encode_add_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // ADD RAX, 1
        let request = EncoderRequest::new(Mnemonic::ADD)
            .with_reg(Register::RAX)
            .with_imm(1);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /0 ib => 48 83 C0 01
        assert_eq!(bytes, vec![0x48, 0x83, 0xC0, 0x01]);
    }

    #[test]
    fn test_encode_sub_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SUB RAX, 5
        let request = EncoderRequest::new(Mnemonic::SUB)
            .with_reg(Register::RAX)
            .with_imm(5);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /5 ib => 48 83 E8 05
        assert_eq!(bytes, vec![0x48, 0x83, 0xE8, 0x05]);
    }

    #[test]
    fn test_encode_cmp_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // CMP RBX, 0
        let request = EncoderRequest::new(Mnemonic::CMP)
            .with_reg(Register::RBX)
            .with_imm(0);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /7 ib => 48 83 FB 00
        assert_eq!(bytes, vec![0x48, 0x83, 0xFB, 0x00]);
    }

    #[test]
    fn test_encode_xor_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // XOR RCX, 0xFF
        let request = EncoderRequest::new(Mnemonic::XOR)
            .with_reg(Register::RCX)
            .with_imm(0xFF);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /6 ib => 48 83 F1 FF
        assert_eq!(bytes, vec![0x48, 0x83, 0xF1, 0xFF]);
    }

    #[test]
    fn test_encode_and_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // AND RDX, 0x0F
        let request = EncoderRequest::new(Mnemonic::AND)
            .with_reg(Register::RDX)
            .with_imm(0x0F);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /4 ib => 48 83 E2 0F
        assert_eq!(bytes, vec![0x48, 0x83, 0xE2, 0x0F]);
    }

    #[test]
    fn test_encode_or_reg_imm() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // OR RSI, 0x80
        let request = EncoderRequest::new(Mnemonic::OR)
            .with_reg(Register::RSI)
            .with_imm(0x80);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 83 /1 ib => 48 83 CE 80
        assert_eq!(bytes, vec![0x48, 0x83, 0xCE, 0x80]);
    }

    #[test]
    fn test_encode_add_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // ADD RAX, RBX
        let request = EncoderRequest::new(Mnemonic::ADD)
            .with_reg(Register::RAX)
            .with_reg(Register::RBX);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 01 /r => 48 01 D8
        assert_eq!(bytes, vec![0x48, 0x01, 0xD8]);
    }

    #[test]
    fn test_encode_sub_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SUB RAX, RBX
        let request = EncoderRequest::new(Mnemonic::SUB)
            .with_reg(Register::RAX)
            .with_reg(Register::RBX);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 29 /r => 48 29 D8
        assert_eq!(bytes, vec![0x48, 0x29, 0xD8]);
    }

    #[test]
    fn test_encode_xor_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // XOR RAX, RCX
        let request = EncoderRequest::new(Mnemonic::XOR)
            .with_reg(Register::RAX)
            .with_reg(Register::RCX);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 31 /r => 48 31 C8
        assert_eq!(bytes, vec![0x48, 0x31, 0xC8]);
    }

    #[test]
    fn test_encode_and_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // AND RAX, RDX
        let request = EncoderRequest::new(Mnemonic::AND)
            .with_reg(Register::RAX)
            .with_reg(Register::RDX);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 21 /r => 48 21 D0
        assert_eq!(bytes, vec![0x48, 0x21, 0xD0]);
    }

    #[test]
    fn test_encode_or_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // OR RAX, RSI
        let request = EncoderRequest::new(Mnemonic::OR)
            .with_reg(Register::RAX)
            .with_reg(Register::RSI);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 09 /r => 48 09 F0
        assert_eq!(bytes, vec![0x48, 0x09, 0xF0]);
    }

    #[test]
    fn test_encode_cmp_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // CMP RAX, RBX
        let request = EncoderRequest::new(Mnemonic::CMP)
            .with_reg(Register::RAX)
            .with_reg(Register::RBX);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + 39 /r => 48 39 D8
        assert_eq!(bytes, vec![0x48, 0x39, 0xD8]);
    }

    #[test]
    fn test_encode_alu_extended_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // ADD R8, 1
        let request = EncoderRequest::new(Mnemonic::ADD)
            .with_reg(Register::R8)
            .with_imm(1);
        let bytes = encoder.encode(&request).unwrap();
        // REX.WB + 83 /0 ib => 49 83 C0 01
        assert_eq!(bytes, vec![0x49, 0x83, 0xC0, 0x01]);

        // ADD RAX, R8
        let request = EncoderRequest::new(Mnemonic::ADD)
            .with_reg(Register::RAX)
            .with_reg(Register::R8);
        let bytes = encoder.encode(&request).unwrap();
        // REX.WR + 01 /r => 4C 01 C0
        assert_eq!(bytes, vec![0x4C, 0x01, 0xC0]);
    }

    // ========================================
    // PUSH/POP instruction encoding tests
    // ========================================

    #[test]
    fn test_encode_push_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // PUSH RAX
        let request = EncoderRequest::new(Mnemonic::PUSH).with_reg(Register::RAX);
        let bytes = encoder.encode(&request).unwrap();
        // 50+rd => 50
        assert_eq!(bytes, vec![0x50]);

        // PUSH RBX
        let request = EncoderRequest::new(Mnemonic::PUSH).with_reg(Register::RBX);
        let bytes = encoder.encode(&request).unwrap();
        assert_eq!(bytes, vec![0x53]);
    }

    #[test]
    fn test_encode_push_extended_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // PUSH R8
        let request = EncoderRequest::new(Mnemonic::PUSH).with_reg(Register::R8);
        let bytes = encoder.encode(&request).unwrap();
        // REX.B + 50+rd => 41 50
        assert_eq!(bytes, vec![0x41, 0x50]);

        // PUSH R15
        let request = EncoderRequest::new(Mnemonic::PUSH).with_reg(Register::R15);
        let bytes = encoder.encode(&request).unwrap();
        // REX.B + 50+rd => 41 57
        assert_eq!(bytes, vec![0x41, 0x57]);
    }

    #[test]
    fn test_encode_pop_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // POP RAX
        let request = EncoderRequest::new(Mnemonic::POP).with_reg(Register::RAX);
        let bytes = encoder.encode(&request).unwrap();
        // 58+rd => 58
        assert_eq!(bytes, vec![0x58]);

        // POP RBX
        let request = EncoderRequest::new(Mnemonic::POP).with_reg(Register::RBX);
        let bytes = encoder.encode(&request).unwrap();
        assert_eq!(bytes, vec![0x5B]);
    }

    #[test]
    fn test_encode_pop_extended_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // POP R8
        let request = EncoderRequest::new(Mnemonic::POP).with_reg(Register::R8);
        let bytes = encoder.encode(&request).unwrap();
        // REX.B + 58+rd => 41 58
        assert_eq!(bytes, vec![0x41, 0x58]);

        // POP R15
        let request = EncoderRequest::new(Mnemonic::POP).with_reg(Register::R15);
        let bytes = encoder.encode(&request).unwrap();
        // REX.B + 58+rd => 41 5F
        assert_eq!(bytes, vec![0x41, 0x5F]);
    }

    // ========================================
    // Shift instruction encoding tests
    // ========================================

    #[test]
    fn test_encode_shl_cl() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SHL RAX, CL
        let request = EncoderRequest::new(Mnemonic::SHL)
            .with_reg(Register::RAX)
            .with_reg(Register::CL);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + D3 /4 => 48 D3 E0
        assert_eq!(bytes, vec![0x48, 0xD3, 0xE0]);
    }

    #[test]
    fn test_encode_shr_cl() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SHR RBX, CL
        let request = EncoderRequest::new(Mnemonic::SHR)
            .with_reg(Register::RBX)
            .with_reg(Register::CL);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + D3 /5 => 48 D3 EB
        assert_eq!(bytes, vec![0x48, 0xD3, 0xEB]);
    }

    #[test]
    fn test_encode_sar_cl() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SAR RCX, CL
        let request = EncoderRequest::new(Mnemonic::SAR)
            .with_reg(Register::RCX)
            .with_reg(Register::CL);
        let bytes = encoder.encode(&request).unwrap();
        // REX.W + D3 /7 => 48 D3 F9
        assert_eq!(bytes, vec![0x48, 0xD3, 0xF9]);
    }

    #[test]
    fn test_encode_shl_extended_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // SHL R8, CL
        let request = EncoderRequest::new(Mnemonic::SHL)
            .with_reg(Register::R8)
            .with_reg(Register::CL);
        let bytes = encoder.encode(&request).unwrap();
        // REX.WB + D3 /4 => 49 D3 E0
        assert_eq!(bytes, vec![0x49, 0xD3, 0xE0]);
    }

    // ========================================
    // AVX instruction encoding tests
    // ========================================

    #[test]
    fn test_encode_vaddps_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VADDPS xmm1, xmm2, xmm3
        // VEX.128.0F.WIG 58 /r
        // xmm1 = vvvv (inverted), xmm2 = reg, xmm3 = rm
        let request = EncoderRequest::new(Mnemonic::VADDPS)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        // VEX prefix: C5 (2-byte) since no extended registers
        // R~=1 (XMM2 not extended), vvvv~=~1=0xE, L=0, pp=00
        // Byte 2: 1 1110 0 00 = 0xF0
        // Opcode: 58
        // ModRM: mod=11, reg=2 (XMM2), rm=3 (XMM3) = 0xD3
        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5); // VEX 2-byte prefix
        // R~=1 -> 0x80, vvvv~=~1=0xE << 3 = 0x70, total 0xF0
        assert_eq!(bytes[1], 0xF0);
        assert_eq!(bytes[2], 0x58); // opcode
        assert_eq!(bytes[3], 0xD3); // ModRM: 11 010 011
    }

    #[test]
    fn test_encode_vaddpd_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VADDPD xmm1, xmm2, xmm3
        // VEX.128.66.0F.WIG 58 /r
        let request = EncoderRequest::new(Mnemonic::VADDPD)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        // VEX prefix with 66 prefix (pp=01)
        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5); // VEX 2-byte prefix
        // R~=1, vvvv~=~1=0xE, L=0, pp=01 => 1 1110 0 01 = 0xF1
        assert_eq!(bytes[1], 0xF1);
        assert_eq!(bytes[2], 0x58); // opcode
        assert_eq!(bytes[3], 0xD3); // ModRM
    }

    #[test]
    fn test_encode_vsubps_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VSUBPS xmm0, xmm1, xmm2
        // VEX.128.0F.WIG 5C /r
        let request = EncoderRequest::new(Mnemonic::VSUBPS)
            .with_reg(Register::XMM0)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5); // VEX prefix
        // R~=1, vvvv~=~0=0xF, L=0, pp=00 => 1 1111 0 00 = 0xF8
        assert_eq!(bytes[1], 0xF8);
        assert_eq!(bytes[2], 0x5C); // opcode
        // ModRM: mod=11, reg=1, rm=2 = 0xCA
        assert_eq!(bytes[3], 0xCA);
    }

    #[test]
    fn test_encode_vsubpd_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VSUBPD xmm0, xmm1, xmm2
        // VEX.128.66.0F.WIG 5C /r
        let request = EncoderRequest::new(Mnemonic::VSUBPD)
            .with_reg(Register::XMM0)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5);
        // R~=1, vvvv~=~0=0xF, L=0, pp=01 => 0xF9
        assert_eq!(bytes[1], 0xF9);
        assert_eq!(bytes[2], 0x5C);
        assert_eq!(bytes[3], 0xCA);
    }

    #[test]
    fn test_encode_vmulps_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VMULPS xmm1, xmm2, xmm3
        // VEX.128.0F.WIG 59 /r
        let request = EncoderRequest::new(Mnemonic::VMULPS)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5);
        assert_eq!(bytes[1], 0xF0); // vvvv~=~1=0xE
        assert_eq!(bytes[2], 0x59); // opcode
        assert_eq!(bytes[3], 0xD3);
    }

    #[test]
    fn test_encode_vmulpd_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VMULPD xmm1, xmm2, xmm3
        // VEX.128.66.0F.WIG 59 /r
        let request = EncoderRequest::new(Mnemonic::VMULPD)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5);
        assert_eq!(bytes[1], 0xF1); // pp=01
        assert_eq!(bytes[2], 0x59);
        assert_eq!(bytes[3], 0xD3);
    }

    #[test]
    fn test_encode_vxorps_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VXORPS xmm1, xmm2, xmm3
        // VEX.128.0F.WIG 57 /r
        let request = EncoderRequest::new(Mnemonic::VXORPS)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5);
        assert_eq!(bytes[1], 0xF0);
        assert_eq!(bytes[2], 0x57); // opcode
        assert_eq!(bytes[3], 0xD3);
    }

    #[test]
    fn test_encode_vxorpd_reg_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VXORPD xmm1, xmm2, xmm3
        // VEX.128.66.0F.WIG 57 /r
        let request = EncoderRequest::new(Mnemonic::VXORPD)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_reg(Register::XMM3);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5);
        assert_eq!(bytes[1], 0xF1); // pp=01
        assert_eq!(bytes[2], 0x57);
        assert_eq!(bytes[3], 0xD3);
    }

    #[test]
    fn test_encode_vaddps_extended_reg() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VADDPS xmm8, xmm9, xmm10
        // This uses 3-byte VEX due to extended registers
        let request = EncoderRequest::new(Mnemonic::VADDPS)
            .with_reg(Register::XMM8)
            .with_reg(Register::XMM9)
            .with_reg(Register::XMM10);
        let bytes = encoder.encode(&request).unwrap();

        // Should use 3-byte VEX since we have extended registers
        assert_eq!(bytes.len(), 5);
        assert_eq!(bytes[0], 0xC4); // 3-byte VEX prefix
        // R~=0 (XMM9 extended), X~=1 (no index), B~=0 (XMM10 extended), mmmmm=00001
        // Byte 2: 0 1 0 00001 = 0x41
        assert_eq!(bytes[1], 0x41);
        // W=0, vvvv~=~8=0x7, L=0, pp=00 => 0 0111 0 00 = 0x38
        assert_eq!(bytes[2], 0x38);
        assert_eq!(bytes[3], 0x58); // opcode
        // ModRM: mod=11, reg=1 (XMM9=9&7=1), rm=2 (XMM10=10&7=2) = 0xCA
        assert_eq!(bytes[4], 0xCA);
    }

    #[test]
    fn test_encode_vaddps_reg_mem() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VADDPS xmm1, xmm2, [rax]
        let mem = MemoryOperand::base(Register::RAX);
        let request = EncoderRequest::new(Mnemonic::VADDPS)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0], 0xC5); // 2-byte VEX
        assert_eq!(bytes[1], 0xF0); // R~=1, vvvv~=~1=0xE
        assert_eq!(bytes[2], 0x58); // opcode
        // ModRM: mod=00, reg=2, rm=0 (RAX) = 0x10
        assert_eq!(bytes[3], 0x10);
    }

    #[test]
    fn test_encode_vaddps_reg_mem_disp() {
        let encoder = Encoder::new(MachineMode::Long64, 64).unwrap();

        // VADDPS xmm1, xmm2, [rax+0x10]
        let mem = MemoryOperand::base_disp(Register::RAX, 0x10);
        let request = EncoderRequest::new(Mnemonic::VADDPS)
            .with_reg(Register::XMM1)
            .with_reg(Register::XMM2)
            .with_mem(mem);
        let bytes = encoder.encode(&request).unwrap();

        assert_eq!(bytes.len(), 5);
        assert_eq!(bytes[0], 0xC5);
        assert_eq!(bytes[1], 0xF0);
        assert_eq!(bytes[2], 0x58);
        // ModRM: mod=01, reg=2, rm=0 = 0x50
        assert_eq!(bytes[3], 0x50);
        assert_eq!(bytes[4], 0x10); // disp8
    }
}