[−][src]Crate zinc64_core
Structs
| Clock | |
| IoPort | |
| IrqControl | |
| IrqLine | |
| Pin | |
| Ram | |
| Rom | |
| SystemModel |
Enums
| Bank | Memory bank type used with MMU to determine how to map a memory address |
| SidModel | |
| VicModel |
Traits
| Addressable | Addressable represents a bank of memory. |
| AddressableFaded | Addressable represents a bank of memory that may be faded by RAM. |
| Chip | A chip represents a system component that is driven by clock signal. |
| ChipFactory | ChipFactory serves as the foundation of an extensible emulator architecture and
provides an interface to construct each chip/component within the system.
It allows for each component to be swapped out and replaced by different implementation.
To accomplish this, special considerations were made to model interactions between chips
without coupling them together. All interactions are managed through separate I/O state
provided as input to each of the chip constructors ( |
| Cpu | CPU is responsible for decoding and executing instructions. |
| Mmu | Represents memory management unit which controls visible memory banks. |
| SoundOutput | Sound output used by SID chip. |
| VideoOutput | Video output used by VIC chip. |
Functions
| make_noop | |
| new_shared | |
| new_shared_cell |
Type Definitions
| Shared | |
| SharedCell | |
| TickFn | A tick represents a callback invoked by the cpu for each clock cycle during instruction execution. |