Struct yaxpeax_x86::long_mode::InstDecoder

pub struct InstDecoder { /* private fields */ }

an x86_64 instruction decoder.

fundamentally this is one or two primitives with no additional state kept during decoding. it can be copied cheaply, hashed cheaply, compared cheaply. if you really want to share an InstDecoder between threads, you could - but you might want to clone it instead.

unless you’re using an Arc<Mutex<InstDecoder>>, which is fine but i’d be very curious about the design requiring that.

Implementations

impl InstDecoder

pub fn minimal() -> Self

instantiates an x86_64 decoder that decodes the bare minimum of x86_64.

pedantic and only decodes what the spec says is well-defined, rejecting undefined sequences and any instructions defined by extensions.

pub fn decode_slice(&self, data: &[u8]) -> Result<Instruction, DecodeError>

helper to decode an instruction directly from a byte slice.

this lets callers avoid the work of setting up a yaxpeax_arch::U8Reader for the slice to decode.

pub fn sse3(&self) -> bool

pub fn with_sse3(self) -> Self

pub fn ssse3(&self) -> bool

pub fn with_ssse3(self) -> Self

pub fn monitor(&self) -> bool

pub fn with_monitor(self) -> Self

pub fn vmx(&self) -> bool

pub fn with_vmx(self) -> Self

pub fn fma3(&self) -> bool

pub fn with_fma3(self) -> Self

pub fn cmpxchg16b(&self) -> bool

pub fn with_cmpxchg16b(self) -> Self

pub fn sse4_1(&self) -> bool

pub fn with_sse4_1(self) -> Self

pub fn sse4_2(&self) -> bool

pub fn with_sse4_2(self) -> Self

pub fn with_sse4(self) -> Self

pub fn movbe(&self) -> bool

pub fn with_movbe(self) -> Self

pub fn popcnt(&self) -> bool

pub fn with_popcnt(self) -> Self

pub fn aesni(&self) -> bool

pub fn with_aesni(self) -> Self

pub fn xsave(&self) -> bool

pub fn with_xsave(self) -> Self

pub fn rdrand(&self) -> bool

pub fn with_rdrand(self) -> Self

pub fn sgx(&self) -> bool

pub fn with_sgx(self) -> Self

pub fn bmi1(&self) -> bool

pub fn with_bmi1(self) -> Self

pub fn avx2(&self) -> bool

pub fn with_avx2(self) -> Self

pub fn bmi2(&self) -> bool

bmi2 indicates support for the BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX, and SHLX instructions. bmi2 is implemented in all x86_64 chips that implement bmi, except the amd piledriver and steamroller microarchitectures.

pub fn with_bmi2(self) -> Self

pub fn invpcid(&self) -> bool

pub fn with_invpcid(self) -> Self

pub fn mpx(&self) -> bool

pub fn with_mpx(self) -> Self

pub fn avx512_f(&self) -> bool

pub fn with_avx512_f(self) -> Self

pub fn avx512_dq(&self) -> bool

pub fn with_avx512_dq(self) -> Self

pub fn rdseed(&self) -> bool

pub fn with_rdseed(self) -> Self

pub fn adx(&self) -> bool

pub fn with_adx(self) -> Self

pub fn avx512_fma(&self) -> bool

pub fn with_avx512_fma(self) -> Self

pub fn pcommit(&self) -> bool

pub fn with_pcommit(self) -> Self

pub fn clflushopt(&self) -> bool

pub fn with_clflushopt(self) -> Self

pub fn clwb(&self) -> bool

pub fn with_clwb(self) -> Self

pub fn avx512_pf(&self) -> bool

pub fn with_avx512_pf(self) -> Self

pub fn avx512_er(&self) -> bool

pub fn with_avx512_er(self) -> Self

pub fn avx512_cd(&self) -> bool

pub fn with_avx512_cd(self) -> Self

pub fn sha(&self) -> bool

pub fn with_sha(self) -> Self

pub fn avx512_bw(&self) -> bool

pub fn with_avx512_bw(self) -> Self

pub fn avx512_vl(&self) -> bool

pub fn with_avx512_vl(self) -> Self

pub fn prefetchwt1(&self) -> bool

pub fn with_prefetchwt1(self) -> Self

pub fn avx512_vbmi(&self) -> bool

pub fn with_avx512_vbmi(self) -> Self

pub fn avx512_vbmi2(&self) -> bool

pub fn with_avx512_vbmi2(self) -> Self

pub fn gfni(&self) -> bool

pub fn with_gfni(self) -> Self

pub fn vaes(&self) -> bool

pub fn with_vaes(self) -> Self

pub fn pclmulqdq(&self) -> bool

pub fn with_pclmulqdq(self) -> Self

pub fn avx_vnni(&self) -> bool

pub fn with_avx_vnni(self) -> Self

pub fn avx512_bitalg(&self) -> bool

pub fn with_avx512_bitalg(self) -> Self

pub fn avx512_vpopcntdq(&self) -> bool

pub fn with_avx512_vpopcntdq(self) -> Self

pub fn avx512_4vnniw(&self) -> bool

pub fn with_avx512_4vnniw(self) -> Self

pub fn avx512_4fmaps(&self) -> bool

pub fn with_avx512_4fmaps(self) -> Self

pub fn avx512(&self) -> bool

returns true if this InstDecoder has all avx512 features enabled.

pub fn with_avx512(self) -> Self

enable all avx512 features on this InstDecoder. no real CPU, at time of writing, actually has such a feature combination, but this is a useful overestimate for avx512 generally.

pub fn cx8(&self) -> bool

pub fn with_cx8(self) -> Self

pub fn syscall(&self) -> bool

pub fn with_syscall(self) -> Self

pub fn rdtscp(&self) -> bool

pub fn with_rdtscp(self) -> Self

pub fn abm(&self) -> bool

pub fn with_abm(self) -> Self

pub fn sse4a(&self) -> bool

pub fn with_sse4a(self) -> Self

pub fn _3dnowprefetch(&self) -> bool

pub fn with_3dnowprefetch(self) -> Self

pub fn xop(&self) -> bool

pub fn with_xop(self) -> Self

pub fn skinit(&self) -> bool

pub fn with_skinit(self) -> Self

pub fn tbm(&self) -> bool

pub fn with_tbm(self) -> Self

pub fn intel_quirks(&self) -> bool

pub fn with_intel_quirks(self) -> Self

pub fn amd_quirks(&self) -> bool

pub fn with_amd_quirks(self) -> Self

pub fn avx(&self) -> bool

pub fn with_avx(self) -> Self

pub fn svm(&self) -> bool

pub fn with_svm(self) -> Self

pub fn lahfsahf(&self) -> bool

lahfsahf is only unset for early revisions of 64-bit amd and intel chips. unfortunately the clearest documentation on when these instructions were reintroduced into 64-bit architectures seems to be wikipedia:

Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD
introduced these instructions (also in 64-bit mode) with their Athlon 64, Opteron and
Turion 64 revision D processors in March 2005[48][49][50] while Intel introduced the
instructions with the Pentium 4 G1 stepping in December 2005. The 64-bit version of Windows
8.1 requires this feature.[47]

this puts reintroduction of these instructions somewhere in the middle of prescott and k8 lifecycles, for intel and amd respectively. because there is no specific uarch where these features become enabled, prescott and k8 default to not supporting these instructions, where later uarches support these instructions.

pub fn with_lahfsahf(self) -> Self

pub fn cmov(&self) -> bool

pub fn with_cmov(self) -> Self

pub fn f16c(&self) -> bool

pub fn with_f16c(self) -> Self

pub fn fma4(&self) -> bool

pub fn with_fma4(self) -> Self

pub fn prefetchw(&self) -> bool

pub fn with_prefetchw(self) -> Self

pub fn tsx(&self) -> bool

pub fn with_tsx(self) -> Self

pub fn lzcnt(&self) -> bool

pub fn with_lzcnt(self) -> Self

Trait Implementations

impl AnnotatingDecoder<Arch> for InstDecoder

type FieldDescription = FieldDescription

fn decode_with_annotation<T: Reader<<Arch as Arch>::Address, <Arch as Arch>::Word>, S: DescriptionSink<Self::FieldDescription>>( &self, instr: &mut Instruction, words: &mut T, sink: &mut S ) -> Result<(), <Arch as Arch>::DecodeError>

impl Clone for InstDecoder

fn clone(&self) -> InstDecoder

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Decoder<Arch> for InstDecoder

fn decode<T: Reader<<Arch as Arch>::Address, <Arch as Arch>::Word>>( &self, words: &mut T ) -> Result<Instruction, <Arch as Arch>::DecodeError>

decode one instruction for this architecture from the crate::Reader of this architecture’s Word.

fn decode_into<T: Reader<<Arch as Arch>::Address, <Arch as Arch>::Word>>( &self, instr: &mut Instruction, words: &mut T ) -> Result<(), <Arch as Arch>::DecodeError>

decode one instruction for this architecture from the crate::Reader of this architecture’s Word, writing into the provided inst.

impl Default for InstDecoder

fn default() -> Self

Instantiates an x86_64 decoder that probably decodes what you want.

Attempts to match real processors in interpretation of undefined sequences, and decodes any instruction defined in any extension.

impl Display for InstDecoder

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for InstDecoder

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for InstDecoder

fn cmp(&self, other: &InstDecoder) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized + PartialOrd,

Restrict a value to a certain interval.

impl PartialEq for InstDecoder

fn eq(&self, other: &InstDecoder) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for InstDecoder

fn partial_cmp(&self, other: &InstDecoder) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

This method tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

This method tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

This method tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

This method tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for InstDecoder

impl Eq for InstDecoder

impl StructuralEq for InstDecoder

impl StructuralPartialEq for InstDecoder