Enum yaxpeax_x86::real_mode::Operand

#[non_exhaustive]
pub enum Operand {
    ImmediateI8(i8),
    ImmediateU8(u8),
    ImmediateI16(i16),
    ImmediateU16(u16),
    ImmediateI32(i32),
    ImmediateU32(u32),
    Register(RegSpec),
    RegisterMaskMerge(RegSpec, RegSpec, MergeMode),
    RegisterMaskMergeSae(RegSpec, RegSpec, MergeMode, SaeMode),
    RegisterMaskMergeSaeNoround(RegSpec, RegSpec, MergeMode),
    DisplacementU16(u16),
    DisplacementU32(u32),
    RegDeref(RegSpec),
    RegDisp(RegSpec, i32),
    RegScale(RegSpec, u8),
    RegIndexBase(RegSpec, RegSpec),
    RegIndexBaseDisp(RegSpec, RegSpec, i32),
    RegScaleDisp(RegSpec, u8, i32),
    RegIndexBaseScale(RegSpec, RegSpec, u8),
    RegIndexBaseScaleDisp(RegSpec, RegSpec, u8, i32),
    RegDerefMasked(RegSpec, RegSpec),
    RegDispMasked(RegSpec, i32, RegSpec),
    RegScaleMasked(RegSpec, u8, RegSpec),
    RegIndexBaseMasked(RegSpec, RegSpec, RegSpec),
    RegIndexBaseDispMasked(RegSpec, RegSpec, i32, RegSpec),
    RegScaleDispMasked(RegSpec, u8, i32, RegSpec),
    RegIndexBaseScaleMasked(RegSpec, RegSpec, u8, RegSpec),
    RegIndexBaseScaleDispMasked(RegSpec, RegSpec, u8, i32, RegSpec),
    Nothing,
}

an operand for an x86 instruction.

Operand::Nothing should be unreachable in practice; any such instructions should have an operand count of 0 (or at least one fewer than the Nothing operand’s position).

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

ImmediateI8(i8)

a sign-extended byte

ImmediateU8(u8)

a zero-extended byte

ImmediateI16(i16)

a sign-extended word

ImmediateU16(u16)

a zero-extended word

ImmediateI32(i32)

a sign-extended dword

ImmediateU32(u32)

a zero-extended dword

Register(RegSpec)

a bare register operand, such as rcx.

RegisterMaskMerge(RegSpec, RegSpec, MergeMode)

an avx512 register operand with optional mask register and merge mode, such as zmm3{k4}{z}.

if the mask register is k0, there is no masking applied, and the default x86 operation is MergeMode::Merge.

RegisterMaskMergeSae(RegSpec, RegSpec, MergeMode, SaeMode)

an avx512 register operand with optional mask register, merge mode, and suppressed exceptions, such as zmm3{k4}{z}{rd-sae}.

if the mask register is k0, there is no masking applied, and the default x86 operation is MergeMode::Merge.

RegisterMaskMergeSaeNoround(RegSpec, RegSpec, MergeMode)

an avx512 register operand with optional mask register, merge mode, and suppressed exceptions, with no overridden rounding mode, such as zmm3{k4}{z}{sae}.

if the mask register is k0, there is no masking applied, and the default x86 operation is MergeMode::Merge.

DisplacementU16(u16)

a memory access to a literal word address. it’s extremely rare that a well-formed x86 instruction uses this mode. as an example, [0x1133]

DisplacementU32(u32)

a memory access to a literal qword address. it’s relatively rare that a well-formed x86 instruction uses this mode, but plausibe. for example, fs:[0x14]. segment overrides, however, are maintained on the instruction itself.

RegDeref(RegSpec)

a simple dereference of the address held in some register. for example: [esi].

RegDisp(RegSpec, i32)

a dereference of the address held in some register with offset. for example: [esi + 0x14].

RegScale(RegSpec, u8)

a dereference of the address held in some register scaled by 1, 2, 4, or 8. this is almost always used with the lea instruction. for example: [edx * 4].

RegIndexBase(RegSpec, RegSpec)

a dereference of the address from summing two registers. for example: [ebp + rax]

RegIndexBaseDisp(RegSpec, RegSpec, i32)

a dereference of the address from summing two registers with offset. for example: [edi + ecx + 0x40]

RegScaleDisp(RegSpec, u8, i32)

a dereference of the address held in some register scaled by 1, 2, 4, or 8 with offset. this is almost always used with the lea instruction. for example: [eax * 4 + 0x30].

RegIndexBaseScale(RegSpec, RegSpec, u8)

a dereference of the address from summing a register and index register scaled by 1, 2, 4, or 8. for example: [esi + ecx * 4]

RegIndexBaseScaleDisp(RegSpec, RegSpec, u8, i32)

a dereference of the address from summing a register and index register scaled by 1, 2, 4, or 8, with offset. for example: [esi + ecx * 4 + 0x1234]

RegDerefMasked(RegSpec, RegSpec)

an avx512 dereference of register with optional masking. for example: [edx]{k3}

RegDispMasked(RegSpec, i32, RegSpec)

an avx512 dereference of register plus offset, with optional masking. for example: [esp + 0x40]{k3}

RegScaleMasked(RegSpec, u8, RegSpec)

an avx512 dereference of a register scaled by 1, 2, 4, or 8, with optional masking. this seems extraordinarily unlikely to occur in practice. for example: [esi * 4]{k2}

RegIndexBaseMasked(RegSpec, RegSpec, RegSpec)

an avx512 dereference of a register plus index scaled by 1, 2, 4, or 8, with optional masking. for example: [esi + eax * 4]{k6}

RegIndexBaseDispMasked(RegSpec, RegSpec, i32, RegSpec)

an avx512 dereference of a register plus offset, with optional masking. for example: [esi + eax + 0x1313]{k6}

RegScaleDispMasked(RegSpec, u8, i32, RegSpec)

an avx512 dereference of a register scaled by 1, 2, 4, or 8 plus offset, with optional masking. this seems extraordinarily unlikely to occur in practice. for example: [esi * 4 + 0x1357]{k2}

RegIndexBaseScaleMasked(RegSpec, RegSpec, u8, RegSpec)

an avx512 dereference of a register plus index scaled by 1, 2, 4, or 8, with optional masking. for example: [esi + eax * 4]{k6}

RegIndexBaseScaleDispMasked(RegSpec, RegSpec, u8, i32, RegSpec)

an avx512 dereference of a register plus index scaled by 1, 2, 4, or 8 and offset, with optional masking. for example: [esi + eax * 4 + 0x1313]{k6}

Nothing

no operand. it is a bug for yaxpeax-x86 to construct an Operand of this kind for public use; the instruction’s operand_count should be reduced so as to make this invisible to library clients.

Implementations

impl Operand

pub fn is_memory(&self) -> bool

returns true if this operand implies a memory access, false otherwise.

notably, the lea instruction uses a memory operand without actually ever accessing memory.

pub fn width(&self) -> Option<u8>

return the width of this operand, in bytes. register widths are determined by the register’s class. the widths of memory operands are recorded on the instruction this Operand came from; None here means the authoritative width is instr.mem_size().

Trait Implementations

impl Clone for Operand

fn clone(&self) -> Operand

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Write, Y: YaxColors> Colorize<T, Y> for Operand

fn colorize(&self, colors: &Y, f: &mut T) -> Result

impl Debug for Operand

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for Operand

fn fmt(&self, fmt: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<Operand> for Operand

fn eq(&self, other: &Operand) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Operand) -> bool

This method tests for !=.

impl StructuralPartialEq for Operand