Crate yaxpeax_superh[−][src]

Expand description

SuperH disassembler with optional yaxpeax support.

Examples

To decode a byte stream with yaxpeax:

assert_eq!(SuperHDecoder::SH4.decode(&mut U8Reader::new(&[0b0101_0101, 0b1100_1010])),
           Ok(SuperHInstruction::XorImm(0x55)));
assert_eq!(SuperHDecoder::SH4.decode(&mut U8Reader::new(&[0b0101_1100, 0b1111_1010])),
           Ok(SuperHInstruction::FMovS(SuperHFloatRegister::Fr5, SuperHFloatRegister::Fr10)));
assert_eq!(SuperHDecoder::SH4.decode(&mut U8Reader::new(&[0b0011_1000, 0b0000_0000])),
           Ok(SuperHInstruction::Ldtlb));
assert_eq!(SuperHDecoder::SH4.decode(&mut U8Reader::new(&[0b0000_0001, 0b0000_0000])),
           Err(SuperHInstructionDecodeError::NotFound));

The same thing on a MMU-less processor booted in big-endian with FPSCR.SZ set:

let cpu = SuperHDecoder {
    little_endian: false,
    fpscr_sz: true,
    features: SuperHFeatures::FPU,
    ..SuperHDecoder::SH4
};

assert_eq!(cpu.decode(&mut U8Reader::new(&[0b1100_1010, 0b0101_0101])),
           Ok(SuperHInstruction::XorImm(0x55)));
assert_eq!(cpu.decode(&mut U8Reader::new(&[0b1111_1010, 0b0101_1100])),
           Ok(SuperHInstruction::FMovFromX(SuperHExtendedDoubleRegister::Xd4,
                                           SuperHDoubleRegister::Dr10)));
assert_eq!(cpu.decode(&mut U8Reader::new(&[0b0000_0000, 0b0011_1000])),
           Err(SuperHInstructionDecodeError::NotFound));
assert_eq!(cpu.decode(&mut U8Reader::new(&[0b0000_0000, 0b0000_0001])),
           Err(SuperHInstructionDecodeError::NotFound));

Simple instruction parsing is also available without yaxpeax:

assert_eq!(SuperHInstruction::parse(0b1100_1010_0101_0101, true),
           Some(SuperHInstruction::XorImm(0x55)));
assert_eq!(SuperHInstruction::parse(0b1111_1010_0101_1100, true),
           Some(SuperHInstruction::FMovFromX(SuperHExtendedDoubleRegister::Xd4,
                                             SuperHDoubleRegister::Dr10)));
assert_eq!(SuperHInstruction::parse(0b0000_0000_0011_1000, true),
           Some(SuperHInstruction::Ldtlb));
assert_eq!(SuperHInstruction::parse(0b0000_0000_0000_0001, true),
           None);

Normative documents

SH-2, and by extension SH-1, since SH-2-only instructions are marked accordingly there.

SH-4 (a.k.a. “cd00147165-sh-4-32-bit-cpu-core-architecture-stmicroelectronics.pdf”)

J-core, specifically the bit about SHAD/SHAL SH3 barrel shift ops and CAS.L.

SH-5, for which no hardware has shipped, was dropped in GCC 7, the link from the press release is dead, and the documentation kinda blows; no attempt is made to support it.

According to this J-core post, SH-DSP is incompatible with newer revisions; no attempt is made to support it.

Uncertainty so as to ISA revisions was resolved according to this page.