Enum yaxpeax_superh::SuperHInstruction[−][src]

pub enum SuperHInstruction {

Show variants    MovImm(u8, SuperHRegister),
    MovImmW(Displacement8, SuperHRegister),
    MovImmL(Displacement8, SuperHRegister),
    MovReg(SuperHRegister, SuperHRegister),
    MovToAtRegB(SuperHRegister, SuperHRegister),
    MovToAtRegW(SuperHRegister, SuperHRegister),
    MovToAtRegL(SuperHRegister, SuperHRegister),
    MovFromAtRegB(SuperHRegister, SuperHRegister),
    MovFromAtRegW(SuperHRegister, SuperHRegister),
    MovFromAtRegL(SuperHRegister, SuperHRegister),
    MovToAtRegPreDecrementB(SuperHRegister, SuperHRegister),
    MovToAtRegPreDecrementW(SuperHRegister, SuperHRegister),
    MovToAtRegPreDecrementL(SuperHRegister, SuperHRegister),
    MovFromAtRegPostIncrementB(SuperHRegister, SuperHRegister),
    MovFromAtRegPostIncrementW(SuperHRegister, SuperHRegister),
    MovFromAtRegPostIncrementL(SuperHRegister, SuperHRegister),
    MovToAtDisplacedRegisterB(Displacement4, SuperHRegister),
    MovToAtDisplacedRegisterW(Displacement4, SuperHRegister),
    MovToAtDisplacedRegisterL(SuperHRegister, Displacement4, SuperHRegister),
    MovFromAtDisplacedRegisterB(Displacement4, SuperHRegister),
    MovFromAtDisplacedRegisterW(Displacement4, SuperHRegister),
    MovFromAtDisplacedRegisterL(Displacement4, SuperHRegister, SuperHRegister),
    MovToAtIndexedRegisterB(SuperHRegister, SuperHRegister),
    MovToAtIndexedRegisterW(SuperHRegister, SuperHRegister),
    MovToAtIndexedRegisterL(SuperHRegister, SuperHRegister),
    MovFromAtIndexedRegisterB(SuperHRegister, SuperHRegister),
    MovFromAtIndexedRegisterW(SuperHRegister, SuperHRegister),
    MovFromAtIndexedRegisterL(SuperHRegister, SuperHRegister),
    MovToAtDisplacedGbrB(Displacement8),
    MovToAtDisplacedGbrW(Displacement8),
    MovToAtDisplacedGbrL(Displacement8),
    MovFromAtDisplacedGbrB(Displacement8),
    MovFromAtDisplacedGbrW(Displacement8),
    MovFromAtDisplacedGbrL(Displacement8),
    Mova(Displacement8),
    Movt(SuperHRegister),
    SwapB(SuperHRegister, SuperHRegister),
    SwapW(SuperHRegister, SuperHRegister),
    Xtrct(SuperHRegister, SuperHRegister),
    AddReg(SuperHRegister, SuperHRegister),
    AddImm(u8, SuperHRegister),
    AddC(SuperHRegister, SuperHRegister),
    AddV(SuperHRegister, SuperHRegister),
    CmpEqImm(u8),
    CmpEqReg(SuperHRegister, SuperHRegister),
    CmpHs(SuperHRegister, SuperHRegister),
    CmpGe(SuperHRegister, SuperHRegister),
    CmpHi(SuperHRegister, SuperHRegister),
    CmpGt(SuperHRegister, SuperHRegister),
    CmpPz(SuperHRegister),
    CmpPl(SuperHRegister),
    CmpStr(SuperHRegister, SuperHRegister),
    Div1(SuperHRegister, SuperHRegister),
    Div0S(SuperHRegister, SuperHRegister),
    Div0U,
    DmulsL(SuperHRegister, SuperHRegister),
    DmuluL(SuperHRegister, SuperHRegister),
    Dt(SuperHRegister),
    ExtsB(SuperHRegister, SuperHRegister),
    ExtsW(SuperHRegister, SuperHRegister),
    ExtuB(SuperHRegister, SuperHRegister),
    ExtuW(SuperHRegister, SuperHRegister),
    MacL(SuperHRegister, SuperHRegister),
    MacW(SuperHRegister, SuperHRegister),
    MulL(SuperHRegister, SuperHRegister),
    MulsW(SuperHRegister, SuperHRegister),
    MuluW(SuperHRegister, SuperHRegister),
    Neg(SuperHRegister, SuperHRegister),
    Negc(SuperHRegister, SuperHRegister),
    Sub(SuperHRegister, SuperHRegister),
    Subc(SuperHRegister, SuperHRegister),
    Subv(SuperHRegister, SuperHRegister),
    AndReg(SuperHRegister, SuperHRegister),
    AndImm(u8),
    AndB(u8),
    Not(SuperHRegister, SuperHRegister),
    OrReg(SuperHRegister, SuperHRegister),
    OrImm(u8),
    OrB(u8),
    TasB(SuperHRegister),
    TstReg(SuperHRegister, SuperHRegister),
    TstImm(u8),
    TstB(u8),
    XorReg(SuperHRegister, SuperHRegister),
    XorImm(u8),
    XorB(u8),
    RotL(SuperHRegister),
    RotR(SuperHRegister),
    RotcL(SuperHRegister),
    RotcR(SuperHRegister),
    ShaD(SuperHRegister, SuperHRegister),
    ShaL(SuperHRegister),
    ShaR(SuperHRegister),
    ShlD(SuperHRegister, SuperHRegister),
    ShlL(SuperHRegister),
    ShlR(SuperHRegister),
    ShlL2(SuperHRegister),
    ShlR2(SuperHRegister),
    ShlL8(SuperHRegister),
    ShlR8(SuperHRegister),
    ShlL16(SuperHRegister),
    ShlR16(SuperHRegister),
    Bf(Displacement8),
    BfS(Displacement8),
    Bt(Displacement8),
    BtS(Displacement8),
    Bra(Displacement12),
    BraF(SuperHRegister),
    Bsr(Displacement12),
    BsrF(SuperHRegister),
    Jmp(SuperHRegister),
    Jsr(SuperHRegister),
    Rts,
    ClrMac,
    ClrS,
    ClrT,
    LdcSr(SuperHRegister),
    LdcGbr(SuperHRegister),
    LdcVbr(SuperHRegister),
    LdcSsr(SuperHRegister),
    LdcSpc(SuperHRegister),
    LdcDbr(SuperHRegister),
    LdcRnBank(SuperHRegister, SuperHRegisterBank),
    LdcLSr(SuperHRegister),
    LdcLGbr(SuperHRegister),
    LdcLVbr(SuperHRegister),
    LdcLSsr(SuperHRegister),
    LdcLSpc(SuperHRegister),
    LdcLDbr(SuperHRegister),
    LdcLRnBank(SuperHRegister, SuperHRegisterBank),
    LdsMach(SuperHRegister),
    LdsMacl(SuperHRegister),
    LdsPr(SuperHRegister),
    LdsLMach(SuperHRegister),
    LdsLMacl(SuperHRegister),
    LdsLPr(SuperHRegister),
    Ldtlb,
    MovcaL(SuperHRegister),
    Nop,
    OcbI(SuperHRegister),
    OcbP(SuperHRegister),
    OcbWb(SuperHRegister),
    Pref(SuperHRegister),
    Rte,
    SetS,
    SetT,
    Sleep,
    StcSr(SuperHRegister),
    StcGbr(SuperHRegister),
    StcVbr(SuperHRegister),
    StcSsr(SuperHRegister),
    StcSpc(SuperHRegister),
    StcSgr(SuperHRegister),
    StcDbr(SuperHRegister),
    StcRmBank(SuperHRegisterBank, SuperHRegister),
    StcLSr(SuperHRegister),
    StcLGbr(SuperHRegister),
    StcLVbr(SuperHRegister),
    StcLSsr(SuperHRegister),
    StcLSpc(SuperHRegister),
    StcLSgr(SuperHRegister),
    StcLDbr(SuperHRegister),
    StcLRmBank(SuperHRegisterBank, SuperHRegister),
    StsMach(SuperHRegister),
    StsMacl(SuperHRegister),
    StsPr(SuperHRegister),
    StsLMach(SuperHRegister),
    StsLMacl(SuperHRegister),
    StsLPr(SuperHRegister),
    Trapa(u8),
    Fldi0(SuperHFloatRegister),
    Fldi1(SuperHFloatRegister),
    FMovS(SuperHFloatRegister, SuperHFloatRegister),
    FMovAtRegS(SuperHRegister, SuperHFloatRegister),
    FMovAtIndexedRegisterS(SuperHRegister, SuperHFloatRegister),
    FMovAtPostIncrementRegS(SuperHRegister, SuperHFloatRegister),
    FMovToAtRegS(SuperHFloatRegister, SuperHRegister),
    FMovToAtPreDecrementRegS(SuperHFloatRegister, SuperHRegister),
    FMovToAtIndexedRegisterS(SuperHFloatRegister, SuperHRegister),
    FMov(SuperHDoubleRegister, SuperHDoubleRegister),
    FMovAtReg(SuperHRegister, SuperHDoubleRegister),
    FMovAtIndexedRegister(SuperHRegister, SuperHDoubleRegister),
    FMovAtPostIncrementReg(SuperHRegister, SuperHDoubleRegister),
    FMovToAtReg(SuperHDoubleRegister, SuperHRegister),
    FMovToAtPreDecrementReg(SuperHDoubleRegister, SuperHRegister),
    FMovToAtIndexedRegister(SuperHDoubleRegister, SuperHRegister),
    Flds(SuperHFloatRegister),
    Fsts(SuperHFloatRegister),
    FabsS(SuperHFloatRegister),
    FaddS(SuperHFloatRegister, SuperHFloatRegister),
    FcmpEqS(SuperHFloatRegister, SuperHFloatRegister),
    FcmpGtS(SuperHFloatRegister, SuperHFloatRegister),
    FdivS(SuperHFloatRegister, SuperHFloatRegister),
    FloatS(SuperHFloatRegister),
    Fmac(SuperHFloatRegister, SuperHFloatRegister),
    FmulS(SuperHFloatRegister, SuperHFloatRegister),
    FnegS(SuperHFloatRegister),
    FsqrtS(SuperHFloatRegister),
    FsubS(SuperHFloatRegister, SuperHFloatRegister),
    FrtcS(SuperHFloatRegister),
    Fabs(SuperHDoubleRegister),
    Fadd(SuperHDoubleRegister, SuperHDoubleRegister),
    FcmpEq(SuperHDoubleRegister, SuperHDoubleRegister),
    FcmpGt(SuperHDoubleRegister, SuperHDoubleRegister),
    Fdiv(SuperHDoubleRegister, SuperHDoubleRegister),
    FcnvDs(SuperHDoubleRegister),
    FcnvSd(SuperHDoubleRegister),
    Float(SuperHDoubleRegister),
    Fmul(SuperHDoubleRegister, SuperHDoubleRegister),
    Fneg(SuperHDoubleRegister),
    Fsqrt(SuperHDoubleRegister),
    Fsub(SuperHDoubleRegister, SuperHDoubleRegister),
    Frtc(SuperHDoubleRegister),
    LdsFpscr(SuperHRegister),
    LdsFpul(SuperHRegister),
    LdsFpscrL(SuperHRegister),
    LdsFpulL(SuperHRegister),
    StsFpscr(SuperHRegister),
    StsFpul(SuperHRegister),
    StsFpscrL(SuperHRegister),
    StsFpulL(SuperHRegister),
    FMovToX(SuperHDoubleRegister, SuperHExtendedDoubleRegister),
    FMovFromX(SuperHExtendedDoubleRegister, SuperHDoubleRegister),
    FMovX(SuperHExtendedDoubleRegister, SuperHExtendedDoubleRegister),
    FMovAtRegX(SuperHRegister, SuperHExtendedDoubleRegister),
    FMovAtPostIncrementRegX(SuperHRegister, SuperHExtendedDoubleRegister),
    FMovAtIndexedRegisterX(SuperHRegister, SuperHExtendedDoubleRegister),
    FMovToAtRegX(SuperHExtendedDoubleRegister, SuperHRegister),
    FMovToAtPreDecrementRegX(SuperHExtendedDoubleRegister, SuperHRegister),
    FMovToAtIndexedRegisterX(SuperHExtendedDoubleRegister, SuperHRegister),
    Fipr(SuperHVectorFloatRegister, SuperHVectorFloatRegister),
    Xmrtx(SuperHVectorFloatRegister),
    FrChg,
    FsChg,
    CasL(SuperHRegister, SuperHRegister),

}

Variants

MovImm(u8, SuperHRegister)

MOV #imm,Rn (imm → sign extension → Rn) 1110nnnniiiiiiii

MOV.W @(disp,PC),Rn ((disp * 2 + PC + 4) → sign extension → Rn) 1001nnnndddddddd

MOV.L @(disp,PC),Rn ((disp * 2 + PC & 0xFFFF_FFFC + 4) → Rn) 1101nnnndddddddd

MOV Rm,Rn (Rm → Rn) 0110nnnnmmmm0011

MOV.B Rm,@Rn (Rm → sign extension → (Rn)) 0010nnnnmmmm0000

MOV.W Rm,@Rn (Rm → sign extension → (Rn)) 0010nnnnmmmm0001

MOV.L Rm,@Rn (Rm → (Rn)) 0010nnnnmmmm0010

MOV.B @Rm,Rn ((Rm) → sign extension → Rn) 0110nnnnmmmm0000

MOV.W @Rm,Rn ((Rm) → sign extension → Rn) 0110nnnnmmmm0001

MOV.L @Rm,Rn ((Rm) → Rn) 0110nnnnmmmm0010

MovToAtRegPreDecrementB(SuperHRegister, SuperHRegister)

MOV.B Rm,@-Rn (Rn - 1 → Rn, Rm → (Rn)) 0010nnnnmmmm0100

MovToAtRegPreDecrementW(SuperHRegister, SuperHRegister)

MOV.W Rm,@-Rn (Rn - 2 → Rn, Rm → (Rn)) 0010nnnnmmmm0101

MovToAtRegPreDecrementL(SuperHRegister, SuperHRegister)

MOV.L Rm,@-Rn (Rn - 4 → Rn, Rm → (Rn)) 0010nnnnmmmm0110

MovFromAtRegPostIncrementB(SuperHRegister, SuperHRegister)

MOV.B @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 1 → Rm) 0110nnnnmmmm0100

MovFromAtRegPostIncrementW(SuperHRegister, SuperHRegister)

MOV.W @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 2 → Rm) 0110nnnnmmmm0101

MovFromAtRegPostIncrementL(SuperHRegister, SuperHRegister)

MOV.L @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 4 → Rm) 0110nnnnmmmm0110

MovToAtDisplacedRegisterB(Displacement4, SuperHRegister)

MOV.B R0,@(disp,Rn) (R0 → (disp + Rn)) 10000000nnnndddd

MovToAtDisplacedRegisterW(Displacement4, SuperHRegister)

MOV.W R0,@(disp,Rn) (R0 → (disp * 2 + Rn)) 10000001nnnndddd

MovToAtDisplacedRegisterL(SuperHRegister, Displacement4, SuperHRegister)

MOV.L Rm,@(disp,Rn) (Rm → (disp * 4 + Rn)) 0001nnnnmmmmdddd

MovFromAtDisplacedRegisterB(Displacement4, SuperHRegister)

MOV.B @(disp,Rm),R0 ((disp + Rm) → sign extension → R0) 10000100mmmmdddd

MovFromAtDisplacedRegisterW(Displacement4, SuperHRegister)

MOV.W @(disp,Rm),R0 ((disp * 2 + Rm) → sign extension → R0) 10000101mmmmdddd

MovFromAtDisplacedRegisterL(Displacement4, SuperHRegister, SuperHRegister)

MOV.L @(disp,Rm),Rn ((disp * 4 + Rm) → Rn) 0101nnnnmmmmdddd

MovToAtIndexedRegisterB(SuperHRegister, SuperHRegister)

MOV.B Rm,@(R0,Rn) (Rm → (R0 + Rn)) 0000nnnnmmmm0100

MovToAtIndexedRegisterW(SuperHRegister, SuperHRegister)

MOV.W Rm,@(R0,Rn) (Rm → (R0 + Rn)) 0000nnnnmmmm0101

MovToAtIndexedRegisterL(SuperHRegister, SuperHRegister)

MOV.L Rm,@(R0,Rn) (Rm → (R0 + Rn)) 0000nnnnmmmm0110

MovFromAtIndexedRegisterB(SuperHRegister, SuperHRegister)

MOV.B @(R0,Rm),Rn ((R0 + Rm) → sign extension → Rn) 0000nnnnmmmm1100

MovFromAtIndexedRegisterW(SuperHRegister, SuperHRegister)

MOV.W @(R0,Rm),Rn ((R0 + Rm) → sign extension → Rn) 0000nnnnmmmm1101

MovFromAtIndexedRegisterL(SuperHRegister, SuperHRegister)

MOV.L @(R0,Rm),Rn ((R0 + Rm) → Rn) 0000nnnnmmmm1110

MovToAtDisplacedGbrB(Displacement8)

MOV.B R0,@(disp,GBR) (R0 → (disp + GBR)) 11000000dddddddd

MovToAtDisplacedGbrW(Displacement8)

MOV.W R0,@(disp,GBR) (R0 → (disp * 2 + GBR)) 11000001dddddddd

MovToAtDisplacedGbrL(Displacement8)

MOV.L R0,@(disp,GBR) (R0 → (disp * 4 + GBR)) 11000010dddddddd

MovFromAtDisplacedGbrB(Displacement8)

MOV.B @(disp,GBR),R0 ((disp + GBR) → sign extension → R0) 11000100dddddddd

MovFromAtDisplacedGbrW(Displacement8)

MOV.W @(disp,GBR),R0 ((disp * 2 + GBR) → sign extension → R0) 11000101dddddddd

MovFromAtDisplacedGbrL(Displacement8)

MOV.L @(disp,GBR),R0 ((disp * 4 + GBR) → R0) 11000110dddddddd

MOVA @(disp,PC),R0 (disp * 4 + PC & 0xFFFF_FFFC + 4 → R0) 11000111dddddddd

MOVT Rn (T → Rn) 0000nnnn00101001

SWAP.B Rm,Rn (Rm → swap lower 2 bytes → REG) 0110nnnnmmmm1000

SWAP.W Rm,Rn (Rm → swap upper/lower words → REG) 0110nnnnmmmm1001

XTRCT Rm,Rn (Rm:Rn middle 32 bits → Rn) 0010nnnnmmmm1101

ADD Rm,Rn (Rn + Rm → Rn) 0011nnnnmmmm1100

AddImm(u8, SuperHRegister)

ADD #imm,Rn (Rn + imm → Rn) 0111nnnniiiiiiii

ADDC Rm,Rn (Rn + Rm + T → Rn, carry → T) 0011nnnnmmmm1110 T = Carry

ADDV Rm,Rn (Rn + Rm → Rn, overflow → T) 0011nnnnmmmm1111 T = Overflow

CmpEqImm(u8)

CMP/EQ #imm,R0 (When R0 = imm, 1 → T; Otherwise, 0 → T) 10001000iiiiiiii T = Comparison result

CMP/EQ Rm,Rn (When Rn = Rm, 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0000 T = Comparison result

CMP/HS Rm,Rn (When Rn ≥ Rm (unsigned), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0010 T = Comparison result

CMP/GE Rm,Rn (When Rn ≥ Rm (signed), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0011 T = Comparison result

CMP/HI Rm,Rn (When Rn > Rm (unsigned), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0110 T = Comparison result

CMP/GT Rm,Rn (When Rn > Rm (signed), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0111 T = Comparison result

CMP/PZ Rn (When Rn ≥ 0, 1 → T; Otherwise, 0 → T) 0100nnnn00010001 T = Comparison result

CMP/PL Rn (When Rn > 0, 1 → T; Otherwise, 0 → T) 0100nnnn00010101 T = Comparison result

CMP/STR Rm,Rn (When any bytes are equal, 1 → T; Otherwise, 0 → T) 0010nnnnmmmm1100 T = Comparison result

DIV1 Rm,Rn (1-step division (Rn ÷ Rm)) 0011nnnnmmmm0100 T = Calculation result

DIV0S Rm,Rn (MSB of Rn → Q, MSB of Rm → M, M ^ Q → T) 0010nnnnmmmm0111 T = Calculation result

Div0U

DIV0U (0 → M/Q/T) 0000000000011001 T = 0

DMULS.L Rm,Rn (Signed, Rn * Rm → MAC, 32 * 32 → 64 bits) 0011nnnnmmmm1101

Level: Sh2

DMULU.L Rm,Rn (Unsigned, Rn * Rm → MAC, 32 * 32 → 64 bits) 0011nnnnmmmm0101

Level: Sh2

DT Rn (Rn - 1 → Rn; When Rn = 0, 1 → T; Otherwise Rn ≠ 0, 0 → T) 0100nnnn00010000 T = Comparison result

Level: Sh2

EXTS.B Rm,Rn (Rm sign-extended from byte → Rn) 0110nnnnmmmm1110

EXTS.W Rm,Rn (Rm sign-extended from word → Rn) 0110nnnnmmmm1111

EXTU.B Rm,Rn (Rm zero-extended from byte → Rn) 0110nnnnmmmm1100

EXTU.W Rm,Rn (Rm zero-extended from word → Rn) 0110nnnnmmmm1101

MAC.L @Rm+,@Rn+ (Signed, (Rn) * (Rm) + MAC → MAC, Rn + 4 → Rn, Rm + 4 → Rm; 32 * 32 + 64 → 64 bits) 0000nnnnmmmm1111`

Level: Sh2

MAC.L @Rm+,@Rn+ (Signed, (Rn) * (Rm) + MAC → MAC, Rn + 2 → Rn, Rm + 2 → Rm; 16 * 16 + 64 → 64 bits) 0100nnnnmmmm1111`

MAC.L Rm,Rn (Rn * Rm → MACL, 32 * 32→ 32 bits) 0000nnnnmmmm0111

Level: Sh2

MULS.W Rm,Rn (Signed, Rn * Rm → MACL, 16 * 16 → 32 bits) 0010nnnnmmmm1111

MULU.W Rm,Rn (Unsigned, Rn * Rm → MACL, 16 * 16 → 32 bits) 0010nnnnmmmm1110

NEG Rm,Rn (0 - Rm → Rn) 0110nnnnmmmm1011

NEGC Rm,Rn (0 - Rm - T → Rn, borrow → T) 0110nnnnmmmm1010 T = Borrow

SUB Rm,Rn (Rn - Rm → Rn) 0011nnnnmmmm1000

SUBC Rm,Rn (Rn - Rm - T → Rn, borrow → T) 0011nnnnmmmm1010 T = Borrow

SUBV Rm,Rn (Rn - Rm → Rn, underflow → T) 0011nnnnmmmm1011 T = Underflow

AND Rm,Rn (Rn & Rm → Rn) 0010nnnnmmmm1001

AndImm(u8)

AND #imm,R0 (R0 & imm → R0) 11001001iiiiiiii

AndB(u8)

AND.B #imm,@(R0,GBR) ((R0 + GBR) & imm → (R0 + GBR)) 11001101iiiiiiii

NOT Rm,Rn (~Rm → Rn) 0110nnnnmmmm0111

OR Rm,Rn (Rn | Rm → Rn) 0010nnnnmmmm1011

OrImm(u8)

OR #imm,R0 (R0 | imm → R0) 11001011iiiiiiii

OrB(u8)

OR.B #imm,@(R0,GBR) ((R0 + GBR) | imm → (R0 + GBR)) 11001111iiiiiiii

TAS.B @Rn (When (Rn) = 0, 1 → T; Otherwise, 0 → T; In both cases, 1 → MSB of (Rn)) 0100nnnn00011011 T = Test result

TST Rm,Rn (Rn & Rm; when result = 0, 1 → T; Otherwise, 0 → T) 0010nnnnmmmm1000 T = Test result

TstImm(u8)

TST #imm,R0 (R0 & imm; when result = 0, 1 → T; Otherwise, 0 → T) 11001000iiiiiiii T = Test result

TstB(u8)

TST.B #imm,@(R0,GBR) ((R0 + GBR) & imm, When result = 0, 1 → T; Otherwise, 0 → T) 11001100iiiiiiii T = Test result

XOR Rm,Rn (Rn ^ Rm → Rn) 0010nnnnmmmm1010 T = Test result

XorImm(u8)

XOR #imm,R0 (R0 ^ imm → R0) 11001010iiiiiiii T = Test result

XorB(u8)

XOR.B #imm,@(R0,GBR) ((R0 + GBR) ^ imm → R0) 11001110iiiiiiii T = Test result

ROTL Rn (T ← Rn ← MSB) 0100nnnn00000100 T = MSB

ROTR Rn (LSB → Rn → T) 0100nnnn00000101 T = LSB

ROTCL Rn (T ← Rn ← T) 0100nnnn00100100 T = MSB

ROTCR Rn (T → Rn → T) 0100nnnn00100101 T = LSB

SHAD Rm,Rn (When Rn ≥ 0, Rn << Rm → Rn, When Rn < 0, Rn >> Rm → [MSB → Rn]) 0100nnnnmmmm1100

Level: J2

SHAL Rn (T ← Rn ← 0) 0100nnnn00100000 T = MSB

SHAR Rn (MSB → Rn → T) 0100nnnn00100001 T = LSB

SHLD Rm,Rn (When Rn ≥ 0, Rn << Rm → Rn, When Rn < 0, Rn >> Rm → [0 → Rn]) 0100nnnnmmmm1101

Level: J2

SHLL Rn (T ← Rn ← 0) 0100nnnn00000000 T = MSB

SHLR Rn (0 → Rn → T) 0100nnnn00000001 T = LSB

SHLL2 Rn (Rn << 2 → Rn) 0100nnnn00001000

SHLR2 Rn (Rn >> 2 → Rn) 0100nnnn00001001

SHLL8 Rn (Rn << 8 → Rn) 0100nnnn00011000

SHLR8 Rn (Rn >> 8 → Rn) 0100nnnn00011001

SHLL16 Rn (Rn << 16 → Rn) 0100nnnn00101000

SHLR16 Rn (Rn >> 16 → Rn) 0100nnnn00101001

BF label (When T = 0, disp * 2 + PC + 4 → PC, When T = 1, nop) 10001011dddddddd

BF/S label (Delayed branch; When T = 0, disp * 2 + PC + 4 → PC, When T = 1, nop) 10001111dddddddd

Level: Sh2

BT label (When T = 1, disp * 2 + PC + 4 → PC, When T = 0, nop) 10001001dddddddd

BT/S label (Delayed branch; When T = 1, disp * 2 + PC + 4 → PC, When T = 0, nop) 10001101dddddddd

Level: Sh2

BRA label (Delayed branch; disp * 2 + PC + 4 → PC) 1010dddddddddddd

BRA Rn (Delayed branch; Rn + PC + 4 → PC) 0000nnnn00100011

Level: Sh2

BSR label (Delayed branch; PC + 4 → PR, disp * 2 + PC + 4 → PC) 1011dddddddddddd

BSR Rn (Delayed branch; PC + 4 → PR, Rn + PC + 4 → PC) 0000nnnn00000011

Level: Sh2

JMP @Rn (Delayed branch; Rn → PC) 0100nnnn00101011

JSR @Rn (Delayed branch; PC + 4 → PR, Rn → PC) 0100nnnn00001011

Rts

RTS (Delayed branch; PR → PC) 0000000000001011

ClrMac

CLRMAC (0 → MACH, MACL) 0000000000101000

ClrS

CLRS (0 → S) 0000000001001000

Level: Sh3

ClrT

CLRT (0 → T) 0000000000001000 T = 0

LDC Rm,SR (Rm → SR) 0100mmmm00001110 T = LSB

Privileged

LDC Rm,GBR (Rm → GBR) 0100mmmm00011110

LDC Rm,VBR (Rm → VBR) 0100mmmm00101110

Privileged

LDC Rm,SSR (Rm → SSR) 0100mmmm00111110

Privileged Level: Sh3

LDC Rm,SPC (Rm → SPC) 0100mmmm01001110

Privileged Level: Sh3

LDC Rm,DBR (Rm → DBR) 0100mmmm11111010

Privileged Level: Sh4

LDC Rm,Rn_BANK (Rm → Rn_BANK (n = 0 to 7)) 0100mmmm1nnn1110

Privileged Level: Sh3

LDC.L @Rm+,SR ((Rm) → SR, Rm + 4 → Rm) 0100mmmm00000111 T = LSB

Privileged

LDC.L @Rm+,GBR ((Rm) → GBR, Rm + 4 → Rm) 0100mmmm00010111

LDC.L @Rm+,VBR ((Rm) → VBR, Rm + 4 → Rm) 0100mmmm00100111

Privileged

LDC.L @Rm+,SSR ((Rm) → SSR, Rm + 4 → Rm) 0100mmmm00110111

Privileged Level: Sh3

LDC.L @Rm+,SPC ((Rm) → SPC, Rm + 4 → Rm) 0100mmmm01000111

Privileged Level: Sh3

LDC.L @Rm+,DBR ((Rm) → DBR, Rm + 4 → Rm) 0100mmmm11110110

Privileged Level: Sh4

LDC.L @Rm+,Rn_BANK ((Rm) → Rn_BANK (n = 0 to 7), Rm + 4 → Rm) 0100mmmm1nnn0111

Privileged Level: Sh3

LDS Rm,MACH (Rm → MACH) 0100mmmm00001010

LDS Rm,MACL (Rm → MACL) 0100mmmm00011010

LDS Rm,PR (Rm → PR) 0100mmmm00101010

LdsLMach(SuperHRegister)

LDS.L @Rm+,MACH ((Rm) → MACH, Rm + 4 → Rm) 0100mmmm00000110

LdsLMacl(SuperHRegister)

LDS.L @Rm+,MACL ((Rm) → MACL, Rm + 4 → Rm) 0100mmmm00010110

LDS.L @Rm+,PR ((Rm) → PR, Rm + 4 → Rm) 0100mmmm00100110

Ldtlb

LDTLB (PTEH/PTEL → TLB) 0000000000111000

Privileged Features: MMU Level: Sh3

MOVCA.L R0,@Rn (R0 → (Rn) (without fetchingcache block)) 0000nnnn11000011

Level: Sh4

Nop

NOP (No operation) 0000000000001001

OCBI @Rn (Invalidates operand cache block) 0000nnnn10010011

Level: Sh4

OCBP @Rn (Writes back and invalidates operand cache block) 0000nnnn10100011

Level: Sh4

OCBWB @Rn (Writes back operand cache block) 0000nnnn10110011

Level: Sh4

PREF @Rn ((Rn) → operand cache) 0000nnnn10000011

Level: Sh3

Rte

RTE (Delayed branch; SSR/SPC → SR/PC) 0000000000101011

Privileged

SetS

SETS (1 → S) 0000000001011000

Level: Sh3

SetT

SETT (1 → T) 0000000000011000 T = 0

Sleep

SLEEP (Sleep or standby) 0000000000011011

Privileged

STC SR,Rn (SR → Rn) 0000nnnn00000010

Privileged

STC GBR,Rn (GBR → Rn) 0000nnnn00010010

STC VBR,Rn (VBR → Rn) 0000nnnn00100010

Privileged

STC SSR,Rn (SSR → Rn) 0000nnnn00110010

Privileged Level: Sh3

STC SPC,Rn (SPC → Rn) 0000nnnn01000010

Privileged Level: Sh3

STC SGR,Rn (SGR → Rn) 0000nnnn00111010

Privileged Level: Sh4

STC DBR,Rn (DBR → Rn) 0000nnnn11111010

Privileged Level: Sh4

STC Rm_BANK,Rn (Rm_BANK → Rn (m = 0 to 7)) 0000nnnn1mmm0010

Privileged Level: Sh3

STC.L SR,@-Rn (Rn - 4 → Rn, SR → (Rn)) 0100nnnn00000011

Privileged

STC.L GBR,@-Rn (Rn - 4 → Rn, GBR → (Rn)) 0100nnnn00010011

STC.L VBR,@-Rn (Rn - 4 → Rn, VBR → (Rn)) 0100nnnn00100011

Privileged

STC.L SSR,@-Rn (Rn - 4 → Rn, SSR → (Rn)) 0100nnnn00110011

Privileged Level: Sh3

STC.L SPC,@-Rn (Rn - 4 → Rn, SPC → (Rn)) 0100nnnn01000011

Privileged Level: Sh3

STC.L SGR,@-Rn (Rn - 4 → Rn, SGR → (Rn)) 0100nnnn00110010

Privileged Level: Sh4

STC.L DBR,@-Rn (Rn - 4 → Rn, DBR → (Rn)) 0100nnnn11110010

Privileged Level: Sh4

STC.L Rm_BANK,@-Rn (Rn - 4 → Rn, Rm_BANK → (Rn) (m = 0 to 7)) 0100nnnn1mmm0011

Privileged Level: Sh3

STS MACH,Rn (MACH → Rn) 0000nnnn00001010

STS MACL,Rn (MACL → Rn) 0000nnnn00011010

STS PR,Rn (PR → Rn) 0000nnnn00101010

StsLMach(SuperHRegister)

STS.L MACH,@-Rn (Rn - 4 → Rn, MACH → (Rn)) 0100nnnn00000010

StsLMacl(SuperHRegister)

STS.L MACL,@-Rn (Rn - 4 → Rn, MACL → (Rn)) 0100nnnn00010010

STS.L PR,@-Rn (Rn - 4 → Rn, PR → (Rn)) 0100nnnn00100010

Trapa(u8)

TRAPA #imm (PC + 2 → SPC, SR → SSR, #imm << 2 → TRA, 0x160 → EXPEVT, VBR + 0x0100 → PC) 11000011iiiiiiii

FLDI0 FRn (0x00000000 → FRn) 1111nnnn10001101

Features: FPU Level: Sh4

FLDI1 FRn (0x3F800000 → FRn) 1111nnnn10011101

Features: FPU Level: Sh4

FMOV FRm,FRn (FRm → FRn) 1111nnnnmmmm1100

Features: FPU Level: Sh4

FMOV.S @Rm,FRn ((Rm) → FRn) 1111nnnnmmmm1000

Features: FPU Level: Sh4

FMovAtIndexedRegisterS(SuperHRegister, SuperHFloatRegister)

FMOV.S @(R0,Rm),FRn ((R0 + Rm) → FRn) 1111nnnnmmmm0110

Features: FPU Level: Sh4

FMovAtPostIncrementRegS(SuperHRegister, SuperHFloatRegister)

FMOV.S @Rm+,FRn ((Rm) → FRn, Rm + 4 → Rm) 1111nnnnmmmm1001

Features: FPU Level: Sh4

FMOV.S FRm,@Rn (FRm → (Rn)) 1111nnnnmmmm1010

Features: FPU Level: Sh4

FMovToAtPreDecrementRegS(SuperHFloatRegister, SuperHRegister)

FMOV.S FRm,@-Rn (Rn - 4 → Rn, FRm → (Rn)) 1111nnnnmmmm1011

Features: FPU Level: Sh4

FMovToAtIndexedRegisterS(SuperHFloatRegister, SuperHRegister)

FMOV.S FRm,@(R0,Rn) (FRm → (R0 + Rn)) 1111nnnnmmmm0111

Features: FPU Level: Sh4

FMOV DRm,DRn (DRm → DRn) 1111nnn0mmm01100

Features: FPU Level: Sh4

FMOV @Rm,DRn ((Rm) → DRn) 1111nnn0mmmm1000

Features: FPU Level: Sh4

FMovAtIndexedRegister(SuperHRegister, SuperHDoubleRegister)

FMOV @(R0,Rm),DRn ((R0 + Rm) → DRn) 1111nnn0mmmm0110

Features: FPU Level: Sh4

FMovAtPostIncrementReg(SuperHRegister, SuperHDoubleRegister)

FMOV @Rm+,DRn ((Rm) → DRn, Rm + 8 → Rm) 1111nnn0mmmm1001

Features: FPU Level: Sh4

FMOV DRm,@Rn (DRm → (Rn)) 1111nnnnmmm01010

Features: FPU Level: Sh4

FMovToAtPreDecrementReg(SuperHDoubleRegister, SuperHRegister)

FMOV DRm,@-Rn (Rn - 8 → Rn, DRm → (Rn)) 1111nnnnmmm01011

Features: FPU Level: Sh4

FMovToAtIndexedRegister(SuperHDoubleRegister, SuperHRegister)

FMOV DRm,@(R0,Rn) (DRm → (R0 + Rn)) 1111nnnnmmm00111

Features: FPU Level: Sh4

FLDS FRm,FPUL (FRm → FPUL) 1111mmmm00011101

Features: FPU Level: Sh4

FSTS FPUL,FRn (FPUL → FRn) 1111nnnn00001101

Features: FPU Level: Sh4

FABS FRn (FRn & 0x7FFF_FFFF → FRn) 1111nnnn01011101

Features: FPU Level: Sh4

FADD FRm,FRn (FRn + FRm → FRn) 1111nnnnmmmm0000

Features: FPU Level: Sh4

FCMP/EQ FRm,FRn (When FRn = FRm, 1 → T; Otherwise, 0 → T) 1111nnnnmmmm0100 T = Comparison result

Features: FPU Level: Sh4

FCMP/GT FRm,FRn (When FRn > FRm, 1 → T; Otherwise, 0 → T) 1111nnnnmmmm0101 T = Comparison result

Features: FPU Level: Sh4

FDIV FRm,FRn (FRn / FRm → FRn) 1111nnnnmmmm0011

Features: FPU Level: Sh4

FLOAT FPUL,FRn ((float)FPUL → FRn) 1111nnnn00101101

Features: FPU Level: Sh4

FMAC FR0,FRm,FRn (FR0 * FRm + FRn → FRn) 1111nnnnmmmm1110

Features: FPU Level: Sh4

FMUL FRm,FRn (FRn * FRm → FRn) 1111nnnnmmmm0010

Features: FPU Level: Sh4

FNEG FRn (FRn ^ 0x8000_0000 → FRn) 1111nnnn01001101

Features: FPU Level: Sh4

FSQRT FRn (√FRn → FRn) 1111nnnn01101101

Features: FPU Level: Sh4

FSUB FRm,FRn (FRn - FRm → FRn) 1111nnnnmmmm0001

Features: FPU Level: Sh4

FRTC FPUL,FRm ((long)FRm → FPUL) 1111mmmm00111101

Features: FPU Level: Sh4

FABS DRn (DRn & 0x7FFF_FFFF_FFFF_FFFF → DRn) 1111nnn001011101

Features: FPU Level: Sh4

FADD DRm,DRn (DRn + DRm → DRn) 1111nnn0mmm00000

Features: FPU Level: Sh4

FCMP/EQ DRm,DRn (When DRn = DRm, 1 → T; Otherwise, 0 → T) 1111nnn0mmm00100 T = Comparison result

Features: FPU Level: Sh4

FCMP/GT DRm,DRn (When DRn > DRm, 1 → T; Otherwise, 0 → T) 1111nnn0mmm00101 T = Comparison result

Features: FPU Level: Sh4

FDIV DRm,DRn (DRn / DRm → DRn) 1111nnn0mmm00011

Features: FPU Level: Sh4

FCNVDS DRm,FPUL (double_to_float[DRm] → FPUL) 1111mmm010111101

Features: FPU Level: Sh4

FCNVSD FPUL,DRn (float_to_double[FPUL] → DRn) 1111nnn010101101

Features: FPU Level: Sh4

FLOAT FPUL,DRn ((float)FPUL → DRn) 1111nnn000101101

Features: FPU Level: Sh4

FMUL DRm,DRn (DRn * DRm → DRn) 1111nnn0mmm00010

Features: FPU Level: Sh4

FNEG DRn (DRn ^ 0x8000_0000_0000_0000 → DRn) 1111nnn001001101

Features: FPU Level: Sh4

FSQRT DRn (√DRn → DRn) 1111nnn001101101

Features: FPU Level: Sh4

FSUB DRm,DRn (DRn - DRm → DRn) 1111nnn0mmm00001

Features: FPU Level: Sh4

FRTC FPUL,DRm ((long)DRm → FPUL) 1111mmm000111101

Features: FPU Level: Sh4

LdsFpscr(SuperHRegister)

LDS Rm,FPSCR (Rm → FPSCR) 0100mmmm01101010

Features: FPU Level: Sh4

LDS Rm,FPUL (Rm → FPUL) 0100mmmm01011010

Features: FPU Level: Sh4

LdsFpscrL(SuperHRegister)

LDS @Rm+,FPSCR (Rm → FPSCR, Rm + 4 → Rm) 0100mmmm01100110

Features: FPU Level: Sh4

LdsFpulL(SuperHRegister)

LDS @Rm+,FPUL (Rm → FPUL, Rm + 4 → Rm) 0100mmmm01010110

Features: FPU Level: Sh4

StsFpscr(SuperHRegister)

STS FPSCR,Rn (FPSCR → Rn) 0000nnnn01101010

Features: FPU Level: Sh4

STS FPUL,Rn (FPUL → Rn) 0000nnnn01011010

Features: FPU Level: Sh4

StsFpscrL(SuperHRegister)

STS FPSCR,@-Rn (Rn - 4 → Rn, FPSCR → Rn) 0100nnnn01100010

Features: FPU Level: Sh4

StsFpulL(SuperHRegister)

STS FPUL,@-Rn (Rn - 4 → Rn, FPUL → Rn) 0100nnnn01010010

Features: FPU Level: Sh4

FMOV DRm,XDn (DRm → XDn) 1111nnn1mmm01100

Features: FPU Level: Sh4

FMOV XDm,DRn (XDm → DRn) 1111nnn0mmm11100

Features: FPU Level: Sh4

FMOV XDm,XDn (XDm → XDn) 1111nnn1mmm11100

Features: FPU Level: Sh4

FMOV @Rm,XDn ((Rm) → XDn) 1111nnn1mmmm1000

Features: FPU Level: Sh4

FMovAtPostIncrementRegX(SuperHRegister, SuperHExtendedDoubleRegister)

FMOV @Rm+,XDn ((Rm) → XDn, Rm + 8 → Rm) 1111nnn1mmmm1001

Features: FPU Level: Sh4

FMOV @(R0,Rm),XDn ((R0 + Rm) → XDn) 1111nnn1mmmm0110

Features: FPU Level: Sh4

FMOV XDm,@Rn (XDm → (Rn)) 1111nnnnmmm11010

Features: FPU Level: Sh4

FMovToAtPreDecrementRegX(SuperHExtendedDoubleRegister, SuperHRegister)

FMOV XDm,@-Rn (Rn - 8 → Rn, XDm → (Rn)) 1111nnnnmmm11011

Features: FPU Level: Sh4

FMovToAtIndexedRegisterX(SuperHExtendedDoubleRegister, SuperHRegister)

FMOV XDm,@(R0,Rn) (XDm → (R0 + Rn)) 1111nnnnmmm10111

Features: FPU Level: Sh4

FIPR FVm,FVn (inner_product[FVm, FVn] → FR[n + 3]) 1111nnmm11101101

Features: FPU Level: Sh4

XMRTX FVn (transform_vector[XMTRX, FVn] → FVn) 1111nn0111111101

Features: FPU Level: Sh4

FrChg

FRCHG (~FPSCR.FR → SPFCR.FR) 1111101111111101

Features: FPU Level: Sh4

FsChg

FSCHG (~FPSCR.SZ → SPFCR.SZ) 1111001111111101

Features: FPU Level: Sh4

CAS.L Rm,Rn,@R0 (When a byte in Rn equals a byte in Rm, 1 → T) 0010nnnnmmmm0011

https://github.com/j-core/jcore-cpu/blob/00f398e/decode/decode_table_simple.vhd#L1919

Features: J2 Level: J2

Implementations

impl SuperHInstruction[src]

pub fn parse(ins: u16, fpscr_sz: bool) -> Option<SuperHInstruction>[src]

Parse a single instruction with the specified architectural state

This parses among all valid instructions; feature-gating must be performed separately

impl SuperHInstruction

pub fn features(self) -> &'static [SuperHFeature]

impl SuperHInstruction

pub fn level(self) -> SuperHLevel

impl SuperHInstruction

pub fn is_privileged(self) -> bool

Trait Implementations

impl Clone for SuperHInstruction[src]

fn clone(&self) -> SuperHInstruction[src]

Returns a copy of the value. Read more

fn clone_from(&mut self, source: &Self)1.0.0[src]

Performs copy-assignment from source. Read more

impl Debug for SuperHInstruction[src]

fn fmt(&self, f: &mut Formatter<'_>) -> Result[src]

Formats the value using the given formatter. Read more

impl Decoder<SuperHInstruction> for SuperHDecoder<'_>[src]

type Error = SuperHInstructionDecodeError

fn decode_into<T: IntoIterator<Item = u8>>(
    &self,
    inst: &mut SuperHInstruction,
    bytes: T
) -> Result<(), Self::Error>[src]

fn decode<T: IntoIterator<Item = u8>>(
    &self,
    bytes: T
) -> Result<SuperHInstruction, Self::Error>[src]

impl Default for SuperHInstruction[src]

fn default() -> SuperHInstruction[src]

Returns the “default value” for a type. Read more

impl Display for SuperHInstruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl Hash for SuperHInstruction[src]

fn hash<__H: Hasher>(&self, state: &mut __H)[src]

Feeds this value into the given Hasher. Read more

fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 1.3.0[src]

Feeds a slice of this type into the given Hasher. Read more

impl Instruction for SuperHInstruction[src]

fn well_defined(&self) -> bool[src]

impl Into<u16> for SuperHInstruction

fn into(self) -> u16

Performs the conversion.

impl LengthedInstruction for SuperHInstruction[src]

type Unit = AddressDiff<u32>

fn len(&self) -> Self::Unit[src]

fn min_size() -> Self::Unit[src]

impl Ord for SuperHInstruction[src]

fn cmp(&self, other: &SuperHInstruction) -> Ordering[src]

This method returns an Ordering between self and other. Read more

#[must_use]
fn max(self, other: Self) -> Self1.21.0[src]

Compares and returns the maximum of two values. Read more

#[must_use]
fn min(self, other: Self) -> Self1.21.0[src]

Compares and returns the minimum of two values. Read more

#[must_use]
fn clamp(self, min: Self, max: Self) -> Self1.50.0[src]

Restrict a value to a certain interval. Read more

impl PartialEq<SuperHInstruction> for SuperHInstruction[src]

fn eq(&self, other: &SuperHInstruction) -> bool[src]

This method tests for self and other values to be equal, and is used by ==. Read more

fn ne(&self, other: &SuperHInstruction) -> bool[src]

This method tests for !=.

impl PartialOrd<SuperHInstruction> for SuperHInstruction[src]

fn partial_cmp(&self, other: &SuperHInstruction) -> Option<Ordering>[src]

This method returns an ordering between self and other values if one exists. Read more

#[must_use]
fn lt(&self, other: &Rhs) -> bool1.0.0[src]

This method tests less than (for self and other) and is used by the < operator. Read more

#[must_use]
fn le(&self, other: &Rhs) -> bool1.0.0[src]

This method tests less than or equal to (for self and other) and is used by the <= operator. Read more

#[must_use]
fn gt(&self, other: &Rhs) -> bool1.0.0[src]

This method tests greater than (for self and other) and is used by the > operator. Read more

#[must_use]
fn ge(&self, other: &Rhs) -> bool1.0.0[src]

This method tests greater than or equal to (for self and other) and is used by the >= operator. Read more

impl Copy for SuperHInstruction[src]

impl Eq for SuperHInstruction[src]

impl StructuralEq for SuperHInstruction[src]

impl StructuralPartialEq for SuperHInstruction[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

pub fn type_id(&self) -> TypeId[src]

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

pub fn borrow(&self) -> &T[src]

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

pub fn borrow_mut(&mut self) -> &mut T[src]

Mutably borrows from an owned value. Read more

impl<T> From<T> for T[src]

pub fn from(t: T) -> T[src]

Performs the conversion.

impl<T, U> Into<U> for T where
    U: From<T>, [src]

pub fn into(self) -> U[src]

Performs the conversion.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]

Performs the conversion.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

pub fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]

Performs the conversion.