xwrl64xx_pac/app_ctrl/
wic_ctrl.rs

1#[doc = "Register `WIC_CTRL` reader"]
2pub type R = crate::R<WicCtrlSpec>;
3#[doc = "Register `WIC_CTRL` writer"]
4pub type W = crate::W<WicCtrlSpec>;
5#[doc = "Field `wicmask` reader - 31:0\\]
61 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
7pub type WicmaskR = crate::FieldReader<u32>;
8#[doc = "Field `wicmask` writer - 31:0\\]
91 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
10pub type WicmaskW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
11impl R {
12    #[doc = "Bits 0:31 - 31:0\\]
131 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
14    #[inline(always)]
15    pub fn wicmask(&self) -> WicmaskR {
16        WicmaskR::new(self.bits)
17    }
18}
19impl W {
20    #[doc = "Bits 0:31 - 31:0\\]
211 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved"]
22    #[inline(always)]
23    #[must_use]
24    pub fn wicmask(&mut self) -> WicmaskW<WicCtrlSpec> {
25        WicmaskW::new(self, 0)
26    }
27}
28#[doc = "WIC_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`wic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29pub struct WicCtrlSpec;
30impl crate::RegisterSpec for WicCtrlSpec {
31    type Ux = u32;
32}
33#[doc = "`read()` method returns [`wic_ctrl::R`](R) reader structure"]
34impl crate::Readable for WicCtrlSpec {}
35#[doc = "`write(|w| ..)` method takes [`wic_ctrl::W`](W) writer structure"]
36impl crate::Writable for WicCtrlSpec {
37    type Safety = crate::Unsafe;
38    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
39    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
40}
41#[doc = "`reset()` method sets WIC_CTRL to value 0"]
42impl crate::Resettable for WicCtrlSpec {
43    const RESET_VALUE: u32 = 0;
44}
xwrl64xx_pac/app_ctrl/wic_ctrl.rs

xwrl64xx_pac/app_ctrl/
wic_ctrl.rs
