xwrl64xx_pac/app_lin/
scisetint.rs

1#[doc = "Register `SCISETINT` reader"]
2pub type R = crate::R<ScisetintSpec>;
3#[doc = "Register `SCISETINT` writer"]
4pub type W = crate::W<ScisetintSpec>;
5#[doc = "Field `SETBRKDTINT` reader - 0:0\\]
6Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
7pub type SetbrkdtintR = crate::BitReader;
8#[doc = "Field `SETBRKDTINT` writer - 0:0\\]
9Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
10pub type SetbrkdtintW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `SETWAKEUPINT` reader - 1:1\\]
12Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
13pub type SetwakeupintR = crate::BitReader;
14#[doc = "Field `SETWAKEUPINT` writer - 1:1\\]
15Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
16pub type SetwakeupintW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SETTIMEOUTINT` reader - 4:4\\]
18Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
19pub type SettimeoutintR = crate::BitReader;
20#[doc = "Field `SETTIMEOUTINT` writer - 4:4\\]
21Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
22pub type SettimeoutintW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `Reserved1` reader - 5:5\\]
24Reserved"]
25pub type Reserved1R = crate::BitReader;
26#[doc = "Field `Reserved1` writer - 5:5\\]
27Reserved"]
28pub type Reserved1W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SETTOAWUSINT` reader - 6:6\\]
30Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
31pub type SettoawusintR = crate::BitReader;
32#[doc = "Field `SETTOAWUSINT` writer - 6:6\\]
33Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
34pub type SettoawusintW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `SETTOA3WUSINT` reader - 7:7\\]
36Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
37pub type Settoa3wusintR = crate::BitReader;
38#[doc = "Field `SETTOA3WUSINT` writer - 7:7\\]
39Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
40pub type Settoa3wusintW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SETTXINT` reader - 8:8\\]
42Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
43pub type SettxintR = crate::BitReader;
44#[doc = "Field `SETTXINT` writer - 8:8\\]
45Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
46pub type SettxintW<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `SETRXINT` reader - 9:9\\]
48Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
49pub type SetrxintR = crate::BitReader;
50#[doc = "Field `SETRXINT` writer - 9:9\\]
51Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
52pub type SetrxintW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `Reserved2` reader - 12:10\\]
54Reserved"]
55pub type Reserved2R = crate::FieldReader;
56#[doc = "Field `Reserved2` writer - 12:10\\]
57Reserved"]
58pub type Reserved2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
59#[doc = "Field `SETIDINT` reader - 13:13\\]
60Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
61pub type SetidintR = crate::BitReader;
62#[doc = "Field `SETIDINT` writer - 13:13\\]
63Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
64pub type SetidintW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `Reserved3` reader - 15:14\\]
66Reserved"]
67pub type Reserved3R = crate::FieldReader;
68#[doc = "Field `Reserved3` writer - 15:14\\]
69Reserved"]
70pub type Reserved3W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
71#[doc = "Field `SET_TX_DMA` reader - 16:16\\]
72Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
73pub type SetTxDmaR = crate::BitReader;
74#[doc = "Field `SET_TX_DMA` writer - 16:16\\]
75Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
76pub type SetTxDmaW<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `SET_RX_DMA` reader - 17:17\\]
78Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
79pub type SetRxDmaR = crate::BitReader;
80#[doc = "Field `SET_RX_DMA` writer - 17:17\\]
81Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
82pub type SetRxDmaW<'a, REG> = crate::BitWriter<'a, REG>;
83#[doc = "Field `SET_RX_DMA_ALL` reader - 18:18\\]
84Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
85pub type SetRxDmaAllR = crate::BitReader;
86#[doc = "Field `SET_RX_DMA_ALL` writer - 18:18\\]
87Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
88pub type SetRxDmaAllW<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `Reserved4` reader - 23:19\\]
90Reserved"]
91pub type Reserved4R = crate::FieldReader;
92#[doc = "Field `Reserved4` writer - 23:19\\]
93Reserved"]
94pub type Reserved4W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
95#[doc = "Field `SETPEINT` reader - 24:24\\]
96Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
97pub type SetpeintR = crate::BitReader;
98#[doc = "Field `SETPEINT` writer - 24:24\\]
99Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
100pub type SetpeintW<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `SETOEINT` reader - 25:25\\]
102Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
103pub type SetoeintR = crate::BitReader;
104#[doc = "Field `SETOEINT` writer - 25:25\\]
105Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
106pub type SetoeintW<'a, REG> = crate::BitWriter<'a, REG>;
107#[doc = "Field `SETFEINT` reader - 26:26\\]
108Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
109pub type SetfeintR = crate::BitReader;
110#[doc = "Field `SETFEINT` writer - 26:26\\]
111Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
112pub type SetfeintW<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `SETNREINT` reader - 27:27\\]
114Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
115pub type SetnreintR = crate::BitReader;
116#[doc = "Field `SETNREINT` writer - 27:27\\]
117Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
118pub type SetnreintW<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `SETISFEINT` reader - 28:28\\]
120Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
121pub type SetisfeintR = crate::BitReader;
122#[doc = "Field `SETISFEINT` writer - 28:28\\]
123Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
124pub type SetisfeintW<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `SETCEINT` reader - 29:29\\]
126Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
127pub type SetceintR = crate::BitReader;
128#[doc = "Field `SETCEINT` writer - 29:29\\]
129Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
130pub type SetceintW<'a, REG> = crate::BitWriter<'a, REG>;
131#[doc = "Field `SETPBEINT` reader - 30:30\\]
132Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
133pub type SetpbeintR = crate::BitReader;
134#[doc = "Field `SETPBEINT` writer - 30:30\\]
135Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
136pub type SetpbeintW<'a, REG> = crate::BitWriter<'a, REG>;
137#[doc = "Field `SETBEINT` reader - 31:31\\]
138Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
139pub type SetbeintR = crate::BitReader;
140#[doc = "Field `SETBEINT` writer - 31:31\\]
141Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
142pub type SetbeintW<'a, REG> = crate::BitWriter<'a, REG>;
143impl R {
144    #[doc = "Bit 0 - 0:0\\]
145Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
146    #[inline(always)]
147    pub fn setbrkdtint(&self) -> SetbrkdtintR {
148        SetbrkdtintR::new((self.bits & 1) != 0)
149    }
150    #[doc = "Bit 1 - 1:1\\]
151Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
152    #[inline(always)]
153    pub fn setwakeupint(&self) -> SetwakeupintR {
154        SetwakeupintR::new(((self.bits >> 1) & 1) != 0)
155    }
156    #[doc = "Bit 4 - 4:4\\]
157Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
158    #[inline(always)]
159    pub fn settimeoutint(&self) -> SettimeoutintR {
160        SettimeoutintR::new(((self.bits >> 4) & 1) != 0)
161    }
162    #[doc = "Bit 5 - 5:5\\]
163Reserved"]
164    #[inline(always)]
165    pub fn reserved1(&self) -> Reserved1R {
166        Reserved1R::new(((self.bits >> 5) & 1) != 0)
167    }
168    #[doc = "Bit 6 - 6:6\\]
169Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
170    #[inline(always)]
171    pub fn settoawusint(&self) -> SettoawusintR {
172        SettoawusintR::new(((self.bits >> 6) & 1) != 0)
173    }
174    #[doc = "Bit 7 - 7:7\\]
175Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
176    #[inline(always)]
177    pub fn settoa3wusint(&self) -> Settoa3wusintR {
178        Settoa3wusintR::new(((self.bits >> 7) & 1) != 0)
179    }
180    #[doc = "Bit 8 - 8:8\\]
181Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
182    #[inline(always)]
183    pub fn settxint(&self) -> SettxintR {
184        SettxintR::new(((self.bits >> 8) & 1) != 0)
185    }
186    #[doc = "Bit 9 - 9:9\\]
187Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
188    #[inline(always)]
189    pub fn setrxint(&self) -> SetrxintR {
190        SetrxintR::new(((self.bits >> 9) & 1) != 0)
191    }
192    #[doc = "Bits 10:12 - 12:10\\]
193Reserved"]
194    #[inline(always)]
195    pub fn reserved2(&self) -> Reserved2R {
196        Reserved2R::new(((self.bits >> 10) & 7) as u8)
197    }
198    #[doc = "Bit 13 - 13:13\\]
199Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
200    #[inline(always)]
201    pub fn setidint(&self) -> SetidintR {
202        SetidintR::new(((self.bits >> 13) & 1) != 0)
203    }
204    #[doc = "Bits 14:15 - 15:14\\]
205Reserved"]
206    #[inline(always)]
207    pub fn reserved3(&self) -> Reserved3R {
208        Reserved3R::new(((self.bits >> 14) & 3) as u8)
209    }
210    #[doc = "Bit 16 - 16:16\\]
211Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
212    #[inline(always)]
213    pub fn set_tx_dma(&self) -> SetTxDmaR {
214        SetTxDmaR::new(((self.bits >> 16) & 1) != 0)
215    }
216    #[doc = "Bit 17 - 17:17\\]
217Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
218    #[inline(always)]
219    pub fn set_rx_dma(&self) -> SetRxDmaR {
220        SetRxDmaR::new(((self.bits >> 17) & 1) != 0)
221    }
222    #[doc = "Bit 18 - 18:18\\]
223Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
224    #[inline(always)]
225    pub fn set_rx_dma_all(&self) -> SetRxDmaAllR {
226        SetRxDmaAllR::new(((self.bits >> 18) & 1) != 0)
227    }
228    #[doc = "Bits 19:23 - 23:19\\]
229Reserved"]
230    #[inline(always)]
231    pub fn reserved4(&self) -> Reserved4R {
232        Reserved4R::new(((self.bits >> 19) & 0x1f) as u8)
233    }
234    #[doc = "Bit 24 - 24:24\\]
235Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
236    #[inline(always)]
237    pub fn setpeint(&self) -> SetpeintR {
238        SetpeintR::new(((self.bits >> 24) & 1) != 0)
239    }
240    #[doc = "Bit 25 - 25:25\\]
241Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
242    #[inline(always)]
243    pub fn setoeint(&self) -> SetoeintR {
244        SetoeintR::new(((self.bits >> 25) & 1) != 0)
245    }
246    #[doc = "Bit 26 - 26:26\\]
247Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
248    #[inline(always)]
249    pub fn setfeint(&self) -> SetfeintR {
250        SetfeintR::new(((self.bits >> 26) & 1) != 0)
251    }
252    #[doc = "Bit 27 - 27:27\\]
253Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
254    #[inline(always)]
255    pub fn setnreint(&self) -> SetnreintR {
256        SetnreintR::new(((self.bits >> 27) & 1) != 0)
257    }
258    #[doc = "Bit 28 - 28:28\\]
259Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
260    #[inline(always)]
261    pub fn setisfeint(&self) -> SetisfeintR {
262        SetisfeintR::new(((self.bits >> 28) & 1) != 0)
263    }
264    #[doc = "Bit 29 - 29:29\\]
265Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
266    #[inline(always)]
267    pub fn setceint(&self) -> SetceintR {
268        SetceintR::new(((self.bits >> 29) & 1) != 0)
269    }
270    #[doc = "Bit 30 - 30:30\\]
271Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
272    #[inline(always)]
273    pub fn setpbeint(&self) -> SetpbeintR {
274        SetpbeintR::new(((self.bits >> 30) & 1) != 0)
275    }
276    #[doc = "Bit 31 - 31:31\\]
277Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
278    #[inline(always)]
279    pub fn setbeint(&self) -> SetbeintR {
280        SetbeintR::new(((self.bits >> 31) & 1) != 0)
281    }
282}
283impl W {
284    #[doc = "Bit 0 - 0:0\\]
285Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only."]
286    #[inline(always)]
287    #[must_use]
288    pub fn setbrkdtint(&mut self) -> SetbrkdtintW<ScisetintSpec> {
289        SetbrkdtintW::new(self, 0)
290    }
291    #[doc = "Bit 1 - 1:1\\]
292Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode."]
293    #[inline(always)]
294    #[must_use]
295    pub fn setwakeupint(&mut self) -> SetwakeupintW<ScisetintSpec> {
296        SetwakeupintW::new(self, 1)
297    }
298    #[doc = "Bit 4 - 4:4\\]
299Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only."]
300    #[inline(always)]
301    #[must_use]
302    pub fn settimeoutint(&mut self) -> SettimeoutintW<ScisetintSpec> {
303        SettimeoutintW::new(self, 4)
304    }
305    #[doc = "Bit 5 - 5:5\\]
306Reserved"]
307    #[inline(always)]
308    #[must_use]
309    pub fn reserved1(&mut self) -> Reserved1W<ScisetintSpec> {
310        Reserved1W::new(self, 5)
311    }
312    #[doc = "Bit 6 - 6:6\\]
313Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only."]
314    #[inline(always)]
315    #[must_use]
316    pub fn settoawusint(&mut self) -> SettoawusintW<ScisetintSpec> {
317        SettoawusintW::new(self, 6)
318    }
319    #[doc = "Bit 7 - 7:7\\]
320Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only."]
321    #[inline(always)]
322    #[must_use]
323    pub fn settoa3wusint(&mut self) -> Settoa3wusintW<ScisetintSpec> {
324        Settoa3wusintW::new(self, 7)
325    }
326    #[doc = "Bit 8 - 8:8\\]
327Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set."]
328    #[inline(always)]
329    #[must_use]
330    pub fn settxint(&mut self) -> SettxintW<ScisetintSpec> {
331        SettxintW::new(self, 8)
332    }
333    #[doc = "Bit 9 - 9:9\\]
334Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD."]
335    #[inline(always)]
336    #[must_use]
337    pub fn setrxint(&mut self) -> SetrxintW<ScisetintSpec> {
338        SetrxintW::new(self, 9)
339    }
340    #[doc = "Bits 10:12 - 12:10\\]
341Reserved"]
342    #[inline(always)]
343    #[must_use]
344    pub fn reserved2(&mut self) -> Reserved2W<ScisetintSpec> {
345        Reserved2W::new(self, 10)
346    }
347    #[doc = "Bit 13 - 13:13\\]
348Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received."]
349    #[inline(always)]
350    #[must_use]
351    pub fn setidint(&mut self) -> SetidintW<ScisetintSpec> {
352        SetidintW::new(self, 13)
353    }
354    #[doc = "Bits 14:15 - 15:14\\]
355Reserved"]
356    #[inline(always)]
357    #[must_use]
358    pub fn reserved3(&mut self) -> Reserved3W<ScisetintSpec> {
359        Reserved3W::new(self, 14)
360    }
361    #[doc = "Bit 16 - 16:16\\]
362Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT."]
363    #[inline(always)]
364    #[must_use]
365    pub fn set_tx_dma(&mut self) -> SetTxDmaW<ScisetintSpec> {
366        SetTxDmaW::new(self, 16)
367    }
368    #[doc = "Bit 17 - 17:17\\]
369Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT."]
370    #[inline(always)]
371    #[must_use]
372    pub fn set_rx_dma(&mut self) -> SetRxDmaW<ScisetintSpec> {
373        SetRxDmaW::new(self, 17)
374    }
375    #[doc = "Bit 18 - 18:18\\]
376Set receiver DMA for Address &amp; Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames."]
377    #[inline(always)]
378    #[must_use]
379    pub fn set_rx_dma_all(&mut self) -> SetRxDmaAllW<ScisetintSpec> {
380        SetRxDmaAllW::new(self, 18)
381    }
382    #[doc = "Bits 19:23 - 23:19\\]
383Reserved"]
384    #[inline(always)]
385    #[must_use]
386    pub fn reserved4(&mut self) -> Reserved4W<ScisetintSpec> {
387        Reserved4W::new(self, 19)
388    }
389    #[doc = "Bit 24 - 24:24\\]
390Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs."]
391    #[inline(always)]
392    #[must_use]
393    pub fn setpeint(&mut self) -> SetpeintW<ScisetintSpec> {
394        SetpeintW::new(self, 24)
395    }
396    #[doc = "Bit 25 - 25:25\\]
397Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs."]
398    #[inline(always)]
399    #[must_use]
400    pub fn setoeint(&mut self) -> SetoeintW<ScisetintSpec> {
401        SetoeintW::new(self, 25)
402    }
403    #[doc = "Bit 26 - 26:26\\]
404Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs."]
405    #[inline(always)]
406    #[must_use]
407    pub fn setfeint(&mut self) -> SetfeintW<ScisetintSpec> {
408        SetfeintW::new(self, 26)
409    }
410    #[doc = "Bit 27 - 27:27\\]
411Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only."]
412    #[inline(always)]
413    #[must_use]
414    pub fn setnreint(&mut self) -> SetnreintW<ScisetintSpec> {
415        SetnreintW::new(self, 27)
416    }
417    #[doc = "Bit 28 - 28:28\\]
418Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only."]
419    #[inline(always)]
420    #[must_use]
421    pub fn setisfeint(&mut self) -> SetisfeintW<ScisetintSpec> {
422        SetisfeintW::new(self, 28)
423    }
424    #[doc = "Bit 29 - 29:29\\]
425Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only."]
426    #[inline(always)]
427    #[must_use]
428    pub fn setceint(&mut self) -> SetceintW<ScisetintSpec> {
429        SetceintW::new(self, 29)
430    }
431    #[doc = "Bit 30 - 30:30\\]
432Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only."]
433    #[inline(always)]
434    #[must_use]
435    pub fn setpbeint(&mut self) -> SetpbeintW<ScisetintSpec> {
436        SetpbeintW::new(self, 30)
437    }
438    #[doc = "Bit 31 - 31:31\\]
439Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only."]
440    #[inline(always)]
441    #[must_use]
442    pub fn setbeint(&mut self) -> SetbeintW<ScisetintSpec> {
443        SetbeintW::new(self, 31)
444    }
445}
446#[doc = "The SCISETINT register is used to enable the various interrupts available in the LIN module.\n\nYou can [`read`](crate::Reg::read) this register and get [`scisetint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scisetint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
447pub struct ScisetintSpec;
448impl crate::RegisterSpec for ScisetintSpec {
449    type Ux = u32;
450}
451#[doc = "`read()` method returns [`scisetint::R`](R) reader structure"]
452impl crate::Readable for ScisetintSpec {}
453#[doc = "`write(|w| ..)` method takes [`scisetint::W`](W) writer structure"]
454impl crate::Writable for ScisetintSpec {
455    type Safety = crate::Unsafe;
456    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
457    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
458}
459#[doc = "`reset()` method sets SCISETINT to value 0"]
460impl crate::Resettable for ScisetintSpec {
461    const RESET_VALUE: u32 = 0;
462}
xwrl64xx_pac/app_lin/scisetint.rs

xwrl64xx_pac/app_lin/
scisetint.rs
