1#[doc = "Register `SCIIODCTRL` reader"]
2pub type R = crate::R<SciiodctrlSpec>;
3#[doc = "Register `SCIIODCTRL` writer"]
4pub type W = crate::W<SciiodctrlSpec>;
5#[doc = "Field `RXP_ENA` reader - 0:0\\]
6Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
7pub type RxpEnaR = crate::BitReader;
8#[doc = "Field `RXP_ENA` writer - 0:0\\]
9Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
10pub type RxpEnaW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `LBP_ENA` reader - 1:1\\]
12Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
13pub type LbpEnaR = crate::BitReader;
14#[doc = "Field `LBP_ENA` writer - 1:1\\]
15Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
16pub type LbpEnaW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RESERVED1` reader - 7:2\\]
18Reserved"]
19pub type Reserved1R = crate::FieldReader;
20#[doc = "Field `RESERVED1` writer - 7:2\\]
21Reserved"]
22pub type Reserved1W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
23#[doc = "Field `IODFTENA` reader - 11:8\\]
24These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
25pub type IodftenaR = crate::FieldReader;
26#[doc = "Field `IODFTENA` writer - 11:8\\]
27These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
28pub type IodftenaW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `RESERVED2` reader - 15:12\\]
30Reserved"]
31pub type Reserved2R = crate::FieldReader;
32#[doc = "Field `RESERVED2` writer - 15:12\\]
33Reserved"]
34pub type Reserved2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
35#[doc = "Field `TX_SHIFT` reader - 18:16\\]
36These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
37pub type TxShiftR = crate::FieldReader;
38#[doc = "Field `TX_SHIFT` writer - 18:16\\]
39These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
40pub type TxShiftW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41#[doc = "Field `PIN_SAMPLE_MASK` reader - 20:19\\]
42PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
43pub type PinSampleMaskR = crate::FieldReader;
44#[doc = "Field `PIN_SAMPLE_MASK` writer - 20:19\\]
45PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
46pub type PinSampleMaskW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
47#[doc = "Field `RESERVED3` reader - 23:21\\]
48Reserved"]
49pub type Reserved3R = crate::FieldReader;
50#[doc = "Field `RESERVED3` writer - 23:21\\]
51Reserved"]
52pub type Reserved3W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
53#[doc = "Field `BRKDT_ENA` reader - 24:24\\]
54Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
55pub type BrkdtEnaR = crate::BitReader;
56#[doc = "Field `BRKDT_ENA` writer - 24:24\\]
57Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
58pub type BrkdtEnaW<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `PEN` reader - 25:25\\]
60Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
61pub type PenR = crate::BitReader;
62#[doc = "Field `PEN` writer - 25:25\\]
63Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
64pub type PenW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `FEN` reader - 26:26\\]
66Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
67pub type FenR = crate::BitReader;
68#[doc = "Field `FEN` writer - 26:26\\]
69Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
70pub type FenW<'a, REG> = crate::BitWriter<'a, REG>;
71#[doc = "Field `RESERVED4` reader - 31:27\\]
72Reserved"]
73pub type Reserved4R = crate::FieldReader;
74#[doc = "Field `RESERVED4` writer - 31:27\\]
75Reserved"]
76pub type Reserved4W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
77impl R {
78 #[doc = "Bit 0 - 0:0\\]
79Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
80 #[inline(always)]
81 pub fn rxp_ena(&self) -> RxpEnaR {
82 RxpEnaR::new((self.bits & 1) != 0)
83 }
84 #[doc = "Bit 1 - 1:1\\]
85Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
86 #[inline(always)]
87 pub fn lbp_ena(&self) -> LbpEnaR {
88 LbpEnaR::new(((self.bits >> 1) & 1) != 0)
89 }
90 #[doc = "Bits 2:7 - 7:2\\]
91Reserved"]
92 #[inline(always)]
93 pub fn reserved1(&self) -> Reserved1R {
94 Reserved1R::new(((self.bits >> 2) & 0x3f) as u8)
95 }
96 #[doc = "Bits 8:11 - 11:8\\]
97These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
98 #[inline(always)]
99 pub fn iodftena(&self) -> IodftenaR {
100 IodftenaR::new(((self.bits >> 8) & 0x0f) as u8)
101 }
102 #[doc = "Bits 12:15 - 15:12\\]
103Reserved"]
104 #[inline(always)]
105 pub fn reserved2(&self) -> Reserved2R {
106 Reserved2R::new(((self.bits >> 12) & 0x0f) as u8)
107 }
108 #[doc = "Bits 16:18 - 18:16\\]
109These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
110 #[inline(always)]
111 pub fn tx_shift(&self) -> TxShiftR {
112 TxShiftR::new(((self.bits >> 16) & 7) as u8)
113 }
114 #[doc = "Bits 19:20 - 20:19\\]
115PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
116 #[inline(always)]
117 pub fn pin_sample_mask(&self) -> PinSampleMaskR {
118 PinSampleMaskR::new(((self.bits >> 19) & 3) as u8)
119 }
120 #[doc = "Bits 21:23 - 23:21\\]
121Reserved"]
122 #[inline(always)]
123 pub fn reserved3(&self) -> Reserved3R {
124 Reserved3R::new(((self.bits >> 21) & 7) as u8)
125 }
126 #[doc = "Bit 24 - 24:24\\]
127Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
128 #[inline(always)]
129 pub fn brkdt_ena(&self) -> BrkdtEnaR {
130 BrkdtEnaR::new(((self.bits >> 24) & 1) != 0)
131 }
132 #[doc = "Bit 25 - 25:25\\]
133Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
134 #[inline(always)]
135 pub fn pen(&self) -> PenR {
136 PenR::new(((self.bits >> 25) & 1) != 0)
137 }
138 #[doc = "Bit 26 - 26:26\\]
139Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
140 #[inline(always)]
141 pub fn fen(&self) -> FenR {
142 FenR::new(((self.bits >> 26) & 1) != 0)
143 }
144 #[doc = "Bits 27:31 - 31:27\\]
145Reserved"]
146 #[inline(always)]
147 pub fn reserved4(&self) -> Reserved4R {
148 Reserved4R::new(((self.bits >> 27) & 0x1f) as u8)
149 }
150}
151impl W {
152 #[doc = "Bit 0 - 0:0\\]
153Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin."]
154 #[inline(always)]
155 #[must_use]
156 pub fn rxp_ena(&mut self) -> RxpEnaW<SciiodctrlSpec> {
157 RxpEnaW::new(self, 0)
158 }
159 #[doc = "Bit 1 - 1:1\\]
160Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled."]
161 #[inline(always)]
162 #[must_use]
163 pub fn lbp_ena(&mut self) -> LbpEnaW<SciiodctrlSpec> {
164 LbpEnaW::new(self, 1)
165 }
166 #[doc = "Bits 2:7 - 7:2\\]
167Reserved"]
168 #[inline(always)]
169 #[must_use]
170 pub fn reserved1(&mut self) -> Reserved1W<SciiodctrlSpec> {
171 Reserved1W::new(self, 2)
172 }
173 #[doc = "Bits 8:11 - 11:8\\]
174These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
175 #[inline(always)]
176 #[must_use]
177 pub fn iodftena(&mut self) -> IodftenaW<SciiodctrlSpec> {
178 IodftenaW::new(self, 8)
179 }
180 #[doc = "Bits 12:15 - 15:12\\]
181Reserved"]
182 #[inline(always)]
183 #[must_use]
184 pub fn reserved2(&mut self) -> Reserved2W<SciiodctrlSpec> {
185 Reserved2W::new(self, 12)
186 }
187 #[doc = "Bits 16:18 - 18:16\\]
188These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay."]
189 #[inline(always)]
190 #[must_use]
191 pub fn tx_shift(&mut self) -> TxShiftW<SciiodctrlSpec> {
192 TxShiftW::new(self, 16)
193 }
194 #[doc = "Bits 19:20 - 20:19\\]
195PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK."]
196 #[inline(always)]
197 #[must_use]
198 pub fn pin_sample_mask(&mut self) -> PinSampleMaskW<SciiodctrlSpec> {
199 PinSampleMaskW::new(self, 19)
200 }
201 #[doc = "Bits 21:23 - 23:21\\]
202Reserved"]
203 #[inline(always)]
204 #[must_use]
205 pub fn reserved3(&mut self) -> Reserved3W<SciiodctrlSpec> {
206 Reserved3W::new(self, 21)
207 }
208 #[doc = "Bit 24 - 24:24\\]
209Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ΓÇÿ0ΓÇÖ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect."]
210 #[inline(always)]
211 #[must_use]
212 pub fn brkdt_ena(&mut self) -> BrkdtEnaW<SciiodctrlSpec> {
213 BrkdtEnaW::new(self, 24)
214 }
215 #[doc = "Bit 25 - 25:25\\]
216Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect"]
217 #[inline(always)]
218 #[must_use]
219 pub fn pen(&mut self) -> PenW<SciiodctrlSpec> {
220 PenW::new(self, 25)
221 }
222 #[doc = "Bit 26 - 26:26\\]
223Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ΓÇÖ0ΓÇÖ and passed to the stop bit check circuitry. 0 = No effect."]
224 #[inline(always)]
225 #[must_use]
226 pub fn fen(&mut self) -> FenW<SciiodctrlSpec> {
227 FenW::new(self, 26)
228 }
229 #[doc = "Bits 27:31 - 31:27\\]
230Reserved"]
231 #[inline(always)]
232 #[must_use]
233 pub fn reserved4(&mut self) -> Reserved4W<SciiodctrlSpec> {
234 Reserved4W::new(self, 27)
235 }
236}
237#[doc = "SCI IO DFT Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sciiodctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sciiodctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
238pub struct SciiodctrlSpec;
239impl crate::RegisterSpec for SciiodctrlSpec {
240 type Ux = u32;
241}
242#[doc = "`read()` method returns [`sciiodctrl::R`](R) reader structure"]
243impl crate::Readable for SciiodctrlSpec {}
244#[doc = "`write(|w| ..)` method takes [`sciiodctrl::W`](W) writer structure"]
245impl crate::Writable for SciiodctrlSpec {
246 type Safety = crate::Unsafe;
247 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
248 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
249}
250#[doc = "`reset()` method sets SCIIODCTRL to value 0"]
251impl crate::Resettable for SciiodctrlSpec {
252 const RESET_VALUE: u32 = 0;
253}