Type Alias xmc4800::usic0_ch0::pcr_sscmode::W

pub type W = W<PCR_SSCMODE_SPEC>;

Register PCR_SSCMode writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn mslsen(&mut self) -> MSLSEN_W<'_, PCR_SSCMODE_SPEC>

Bit 0 - MSLS Enable

pub fn selctr(&mut self) -> SELCTR_W<'_, PCR_SSCMODE_SPEC>

Bit 1 - Select Control

pub fn selinv(&mut self) -> SELINV_W<'_, PCR_SSCMODE_SPEC>

Bit 2 - Select Inversion

pub fn fem(&mut self) -> FEM_W<'_, PCR_SSCMODE_SPEC>

Bit 3 - Frame End Mode

pub fn ctqsel1(&mut self) -> CTQSEL1_W<'_, PCR_SSCMODE_SPEC>

Bits 4:5 - Input Frequency Selection

pub fn pctq1(&mut self) -> PCTQ1_W<'_, PCR_SSCMODE_SPEC>

Bits 6:7 - Divider Factor PCTQ1 for Tiw and Tnf

pub fn dctq1(&mut self) -> DCTQ1_W<'_, PCR_SSCMODE_SPEC>

Bits 8:12 - Divider Factor DCTQ1 for Tiw and Tnf

pub fn parien(&mut self) -> PARIEN_W<'_, PCR_SSCMODE_SPEC>

Bit 13 - Parity Error Interrupt Enable

pub fn mslsien(&mut self) -> MSLSIEN_W<'_, PCR_SSCMODE_SPEC>

Bit 14 - MSLS Interrupt Enable

pub fn dx2tien(&mut self) -> DX2TIEN_W<'_, PCR_SSCMODE_SPEC>

Bit 15 - DX2T Interrupt Enable

pub fn selo(&mut self) -> SELO_W<'_, PCR_SSCMODE_SPEC>

Bits 16:23 - Select Output

pub fn tiwen(&mut self) -> TIWEN_W<'_, PCR_SSCMODE_SPEC>

Bit 24 - Enable Inter-Word Delay Tiw

pub fn slphsel(&mut self) -> SLPHSEL_W<'_, PCR_SSCMODE_SPEC>

Bit 25 - Slave Mode Clock Phase Select

pub fn mclk(&mut self) -> MCLK_W<'_, PCR_SSCMODE_SPEC>

Bit 31 - Master Clock Enable