1#[doc = "Register `MPU_CTRL` reader"]
2pub type R = crate::R<MPU_CTRL_SPEC>;
3#[doc = "Register `MPU_CTRL` writer"]
4pub type W = crate::W<MPU_CTRL_SPEC>;
5#[doc = "Enable MPU\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum ENABLE_A {
8 #[doc = "0: MPU disabled"]
9 VALUE1 = 0,
10 #[doc = "1: MPU enabled."]
11 VALUE2 = 1,
12}
13impl From<ENABLE_A> for bool {
14 #[inline(always)]
15 fn from(variant: ENABLE_A) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `ENABLE` reader - Enable MPU"]
20pub type ENABLE_R = crate::BitReader<ENABLE_A>;
21impl ENABLE_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> ENABLE_A {
25 match self.bits {
26 false => ENABLE_A::VALUE1,
27 true => ENABLE_A::VALUE2,
28 }
29 }
30 #[doc = "MPU disabled"]
31 #[inline(always)]
32 pub fn is_value1(&self) -> bool {
33 *self == ENABLE_A::VALUE1
34 }
35 #[doc = "MPU enabled."]
36 #[inline(always)]
37 pub fn is_value2(&self) -> bool {
38 *self == ENABLE_A::VALUE2
39 }
40}
41#[doc = "Field `ENABLE` writer - Enable MPU"]
42pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE_A>;
43impl<'a, REG> ENABLE_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "MPU disabled"]
48 #[inline(always)]
49 pub fn value1(self) -> &'a mut crate::W<REG> {
50 self.variant(ENABLE_A::VALUE1)
51 }
52 #[doc = "MPU enabled."]
53 #[inline(always)]
54 pub fn value2(self) -> &'a mut crate::W<REG> {
55 self.variant(ENABLE_A::VALUE2)
56 }
57}
58#[doc = "Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum HFNMIENA_A {
61 #[doc = "0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit"]
62 VALUE1 = 0,
63 #[doc = "1: the MPU is enabled during hard fault, NMI, and FAULTMASK handlers."]
64 VALUE2 = 1,
65}
66impl From<HFNMIENA_A> for bool {
67 #[inline(always)]
68 fn from(variant: HFNMIENA_A) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `HFNMIENA` reader - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers"]
73pub type HFNMIENA_R = crate::BitReader<HFNMIENA_A>;
74impl HFNMIENA_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> HFNMIENA_A {
78 match self.bits {
79 false => HFNMIENA_A::VALUE1,
80 true => HFNMIENA_A::VALUE2,
81 }
82 }
83 #[doc = "MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit"]
84 #[inline(always)]
85 pub fn is_value1(&self) -> bool {
86 *self == HFNMIENA_A::VALUE1
87 }
88 #[doc = "the MPU is enabled during hard fault, NMI, and FAULTMASK handlers."]
89 #[inline(always)]
90 pub fn is_value2(&self) -> bool {
91 *self == HFNMIENA_A::VALUE2
92 }
93}
94#[doc = "Field `HFNMIENA` writer - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers"]
95pub type HFNMIENA_W<'a, REG> = crate::BitWriter<'a, REG, HFNMIENA_A>;
96impl<'a, REG> HFNMIENA_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit"]
101 #[inline(always)]
102 pub fn value1(self) -> &'a mut crate::W<REG> {
103 self.variant(HFNMIENA_A::VALUE1)
104 }
105 #[doc = "the MPU is enabled during hard fault, NMI, and FAULTMASK handlers."]
106 #[inline(always)]
107 pub fn value2(self) -> &'a mut crate::W<REG> {
108 self.variant(HFNMIENA_A::VALUE2)
109 }
110}
111#[doc = "Enables privileged software access to the default memory map\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum PRIVDEFENA_A {
114 #[doc = "0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault."]
115 VALUE1 = 0,
116 #[doc = "1: If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses."]
117 VALUE2 = 1,
118}
119impl From<PRIVDEFENA_A> for bool {
120 #[inline(always)]
121 fn from(variant: PRIVDEFENA_A) -> Self {
122 variant as u8 != 0
123 }
124}
125#[doc = "Field `PRIVDEFENA` reader - Enables privileged software access to the default memory map"]
126pub type PRIVDEFENA_R = crate::BitReader<PRIVDEFENA_A>;
127impl PRIVDEFENA_R {
128 #[doc = "Get enumerated values variant"]
129 #[inline(always)]
130 pub const fn variant(&self) -> PRIVDEFENA_A {
131 match self.bits {
132 false => PRIVDEFENA_A::VALUE1,
133 true => PRIVDEFENA_A::VALUE2,
134 }
135 }
136 #[doc = "If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault."]
137 #[inline(always)]
138 pub fn is_value1(&self) -> bool {
139 *self == PRIVDEFENA_A::VALUE1
140 }
141 #[doc = "If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses."]
142 #[inline(always)]
143 pub fn is_value2(&self) -> bool {
144 *self == PRIVDEFENA_A::VALUE2
145 }
146}
147#[doc = "Field `PRIVDEFENA` writer - Enables privileged software access to the default memory map"]
148pub type PRIVDEFENA_W<'a, REG> = crate::BitWriter<'a, REG, PRIVDEFENA_A>;
149impl<'a, REG> PRIVDEFENA_W<'a, REG>
150where
151 REG: crate::Writable + crate::RegisterSpec,
152{
153 #[doc = "If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault."]
154 #[inline(always)]
155 pub fn value1(self) -> &'a mut crate::W<REG> {
156 self.variant(PRIVDEFENA_A::VALUE1)
157 }
158 #[doc = "If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses."]
159 #[inline(always)]
160 pub fn value2(self) -> &'a mut crate::W<REG> {
161 self.variant(PRIVDEFENA_A::VALUE2)
162 }
163}
164impl R {
165 #[doc = "Bit 0 - Enable MPU"]
166 #[inline(always)]
167 pub fn enable(&self) -> ENABLE_R {
168 ENABLE_R::new((self.bits & 1) != 0)
169 }
170 #[doc = "Bit 1 - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers"]
171 #[inline(always)]
172 pub fn hfnmiena(&self) -> HFNMIENA_R {
173 HFNMIENA_R::new(((self.bits >> 1) & 1) != 0)
174 }
175 #[doc = "Bit 2 - Enables privileged software access to the default memory map"]
176 #[inline(always)]
177 pub fn privdefena(&self) -> PRIVDEFENA_R {
178 PRIVDEFENA_R::new(((self.bits >> 2) & 1) != 0)
179 }
180}
181impl W {
182 #[doc = "Bit 0 - Enable MPU"]
183 #[inline(always)]
184 pub fn enable(&mut self) -> ENABLE_W<MPU_CTRL_SPEC> {
185 ENABLE_W::new(self, 0)
186 }
187 #[doc = "Bit 1 - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers"]
188 #[inline(always)]
189 pub fn hfnmiena(&mut self) -> HFNMIENA_W<MPU_CTRL_SPEC> {
190 HFNMIENA_W::new(self, 1)
191 }
192 #[doc = "Bit 2 - Enables privileged software access to the default memory map"]
193 #[inline(always)]
194 pub fn privdefena(&mut self) -> PRIVDEFENA_W<MPU_CTRL_SPEC> {
195 PRIVDEFENA_W::new(self, 2)
196 }
197}
198#[doc = "MPU Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
199pub struct MPU_CTRL_SPEC;
200impl crate::RegisterSpec for MPU_CTRL_SPEC {
201 type Ux = u32;
202}
203#[doc = "`read()` method returns [`mpu_ctrl::R`](R) reader structure"]
204impl crate::Readable for MPU_CTRL_SPEC {}
205#[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"]
206impl crate::Writable for MPU_CTRL_SPEC {
207 type Safety = crate::Unsafe;
208 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
210}
211#[doc = "`reset()` method sets MPU_CTRL to value 0"]
212impl crate::Resettable for MPU_CTRL_SPEC {
213 const RESET_VALUE: u32 = 0;
214}