xmc4800/ecat0/
dc_sync1_cyc_time.rs

1#[doc = "Register `DC_SYNC1_CYC_TIME` reader"]
2pub type R = crate::R<DC_SYNC1_CYC_TIME_SPEC>;
3#[doc = "Register `DC_SYNC1_CYC_TIME` writer"]
4pub type W = crate::W<DC_SYNC1_CYC_TIME_SPEC>;
5#[doc = "Field `TIME_SYNC1_SYNC0` reader - Time between SYNC1 pulses and SYNC0 pulse"]
6pub type TIME_SYNC1_SYNC0_R = crate::FieldReader<u32>;
7#[doc = "Field `TIME_SYNC1_SYNC0` writer - Time between SYNC1 pulses and SYNC0 pulse"]
8pub type TIME_SYNC1_SYNC0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Time between SYNC1 pulses and SYNC0 pulse"]
11    #[inline(always)]
12    pub fn time_sync1_sync0(&self) -> TIME_SYNC1_SYNC0_R {
13        TIME_SYNC1_SYNC0_R::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - Time between SYNC1 pulses and SYNC0 pulse"]
18    #[inline(always)]
19    pub fn time_sync1_sync0(&mut self) -> TIME_SYNC1_SYNC0_W<DC_SYNC1_CYC_TIME_SPEC> {
20        TIME_SYNC1_SYNC0_W::new(self, 0)
21    }
22}
23#[doc = "SYNC1 Cycle Time\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_sync1_cyc_time::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dc_sync1_cyc_time::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct DC_SYNC1_CYC_TIME_SPEC;
25impl crate::RegisterSpec for DC_SYNC1_CYC_TIME_SPEC {
26    type Ux = u32;
27}
28#[doc = "`read()` method returns [`dc_sync1_cyc_time::R`](R) reader structure"]
29impl crate::Readable for DC_SYNC1_CYC_TIME_SPEC {}
30#[doc = "`write(|w| ..)` method takes [`dc_sync1_cyc_time::W`](W) writer structure"]
31impl crate::Writable for DC_SYNC1_CYC_TIME_SPEC {
32    type Safety = crate::Unsafe;
33    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35}
36#[doc = "`reset()` method sets DC_SYNC1_CYC_TIME to value 0"]
37impl crate::Resettable for DC_SYNC1_CYC_TIME_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
xmc4800/ecat0/dc_sync1_cyc_time.rs

xmc4800/ecat0/
dc_sync1_cyc_time.rs
