xmc4800/scu_clk/
cpuclkcr.rs

1#[doc = "Register `CPUCLKCR` reader"]
2pub type R = crate::R<CPUCLKCR_SPEC>;
3#[doc = "Register `CPUCLKCR` writer"]
4pub type W = crate::W<CPUCLKCR_SPEC>;
5#[doc = "CPU Clock Divider Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum CPUDIV_A {
8    #[doc = "0: fCPU = fSYS"]
9    VALUE1 = 0,
10    #[doc = "1: fCPU = fSYS / 2"]
11    VALUE2 = 1,
12}
13impl From<CPUDIV_A> for bool {
14    #[inline(always)]
15    fn from(variant: CPUDIV_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CPUDIV` reader - CPU Clock Divider Enable"]
20pub type CPUDIV_R = crate::BitReader<CPUDIV_A>;
21impl CPUDIV_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CPUDIV_A {
25        match self.bits {
26            false => CPUDIV_A::VALUE1,
27            true => CPUDIV_A::VALUE2,
28        }
29    }
30    #[doc = "fCPU = fSYS"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == CPUDIV_A::VALUE1
34    }
35    #[doc = "fCPU = fSYS / 2"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == CPUDIV_A::VALUE2
39    }
40}
41#[doc = "Field `CPUDIV` writer - CPU Clock Divider Enable"]
42pub type CPUDIV_W<'a, REG> = crate::BitWriter<'a, REG, CPUDIV_A>;
43impl<'a, REG> CPUDIV_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "fCPU = fSYS"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(CPUDIV_A::VALUE1)
51    }
52    #[doc = "fCPU = fSYS / 2"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(CPUDIV_A::VALUE2)
56    }
57}
58impl R {
59    #[doc = "Bit 0 - CPU Clock Divider Enable"]
60    #[inline(always)]
61    pub fn cpudiv(&self) -> CPUDIV_R {
62        CPUDIV_R::new((self.bits & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 0 - CPU Clock Divider Enable"]
67    #[inline(always)]
68    pub fn cpudiv(&mut self) -> CPUDIV_W<CPUCLKCR_SPEC> {
69        CPUDIV_W::new(self, 0)
70    }
71}
72#[doc = "CPU Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpuclkcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuclkcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
73pub struct CPUCLKCR_SPEC;
74impl crate::RegisterSpec for CPUCLKCR_SPEC {
75    type Ux = u32;
76}
77#[doc = "`read()` method returns [`cpuclkcr::R`](R) reader structure"]
78impl crate::Readable for CPUCLKCR_SPEC {}
79#[doc = "`write(|w| ..)` method takes [`cpuclkcr::W`](W) writer structure"]
80impl crate::Writable for CPUCLKCR_SPEC {
81    type Safety = crate::Unsafe;
82    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
84}
85#[doc = "`reset()` method sets CPUCLKCR to value 0"]
86impl crate::Resettable for CPUCLKCR_SPEC {
87    const RESET_VALUE: u32 = 0;
88}
xmc4800/scu_clk/cpuclkcr.rs

xmc4800/scu_clk/
cpuclkcr.rs
