xmc4700/port4/
pdr0.rs

1#[doc = "Register `PDR0` reader"]
2pub type R = crate::R<PDR0_SPEC>;
3#[doc = "Register `PDR0` writer"]
4pub type W = crate::W<PDR0_SPEC>;
5#[doc = "Pad Driver Mode for Pn.0\n\nValue on reset: 2"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum PD0_A {
9    #[doc = "0: A2 strong driver, sharp edge"]
10    SD_SHE = 0,
11    #[doc = "1: A2 strong driver, medium edge"]
12    SD_MEE = 1,
13    #[doc = "2: A2 strong driver, soft edge"]
14    SD_SOE = 2,
15    #[doc = "4: A2 medium driver"]
16    MD = 4,
17    #[doc = "7: A2 weak driver"]
18    WD = 7,
19}
20impl From<PD0_A> for u8 {
21    #[inline(always)]
22    fn from(variant: PD0_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for PD0_A {
27    type Ux = u8;
28}
29impl crate::IsEnum for PD0_A {}
30#[doc = "Field `PD0` reader - Pad Driver Mode for Pn.0"]
31pub type PD0_R = crate::FieldReader<PD0_A>;
32impl PD0_R {
33    #[doc = "Get enumerated values variant"]
34    #[inline(always)]
35    pub const fn variant(&self) -> Option<PD0_A> {
36        match self.bits {
37            0 => Some(PD0_A::SD_SHE),
38            1 => Some(PD0_A::SD_MEE),
39            2 => Some(PD0_A::SD_SOE),
40            4 => Some(PD0_A::MD),
41            7 => Some(PD0_A::WD),
42            _ => None,
43        }
44    }
45    #[doc = "A2 strong driver, sharp edge"]
46    #[inline(always)]
47    pub fn is_sd_she(&self) -> bool {
48        *self == PD0_A::SD_SHE
49    }
50    #[doc = "A2 strong driver, medium edge"]
51    #[inline(always)]
52    pub fn is_sd_mee(&self) -> bool {
53        *self == PD0_A::SD_MEE
54    }
55    #[doc = "A2 strong driver, soft edge"]
56    #[inline(always)]
57    pub fn is_sd_soe(&self) -> bool {
58        *self == PD0_A::SD_SOE
59    }
60    #[doc = "A2 medium driver"]
61    #[inline(always)]
62    pub fn is_md(&self) -> bool {
63        *self == PD0_A::MD
64    }
65    #[doc = "A2 weak driver"]
66    #[inline(always)]
67    pub fn is_wd(&self) -> bool {
68        *self == PD0_A::WD
69    }
70}
71#[doc = "Field `PD0` writer - Pad Driver Mode for Pn.0"]
72pub type PD0_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD0_A>;
73impl<'a, REG> PD0_W<'a, REG>
74where
75    REG: crate::Writable + crate::RegisterSpec,
76    REG::Ux: From<u8>,
77{
78    #[doc = "A2 strong driver, sharp edge"]
79    #[inline(always)]
80    pub fn sd_she(self) -> &'a mut crate::W<REG> {
81        self.variant(PD0_A::SD_SHE)
82    }
83    #[doc = "A2 strong driver, medium edge"]
84    #[inline(always)]
85    pub fn sd_mee(self) -> &'a mut crate::W<REG> {
86        self.variant(PD0_A::SD_MEE)
87    }
88    #[doc = "A2 strong driver, soft edge"]
89    #[inline(always)]
90    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
91        self.variant(PD0_A::SD_SOE)
92    }
93    #[doc = "A2 medium driver"]
94    #[inline(always)]
95    pub fn md(self) -> &'a mut crate::W<REG> {
96        self.variant(PD0_A::MD)
97    }
98    #[doc = "A2 weak driver"]
99    #[inline(always)]
100    pub fn wd(self) -> &'a mut crate::W<REG> {
101        self.variant(PD0_A::WD)
102    }
103}
104#[doc = "Pad Driver Mode for Pn.1\n\nValue on reset: 2"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum PD1_A {
108    #[doc = "0: A2 strong driver, sharp edge"]
109    SD_SHE = 0,
110    #[doc = "1: A2 strong driver, medium edge"]
111    SD_MEE = 1,
112    #[doc = "2: A2 strong driver, soft edge"]
113    SD_SOE = 2,
114    #[doc = "4: A2 medium driver"]
115    MD = 4,
116    #[doc = "7: A2 weak driver"]
117    WD = 7,
118}
119impl From<PD1_A> for u8 {
120    #[inline(always)]
121    fn from(variant: PD1_A) -> Self {
122        variant as _
123    }
124}
125impl crate::FieldSpec for PD1_A {
126    type Ux = u8;
127}
128impl crate::IsEnum for PD1_A {}
129#[doc = "Field `PD1` reader - Pad Driver Mode for Pn.1"]
130pub type PD1_R = crate::FieldReader<PD1_A>;
131impl PD1_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> Option<PD1_A> {
135        match self.bits {
136            0 => Some(PD1_A::SD_SHE),
137            1 => Some(PD1_A::SD_MEE),
138            2 => Some(PD1_A::SD_SOE),
139            4 => Some(PD1_A::MD),
140            7 => Some(PD1_A::WD),
141            _ => None,
142        }
143    }
144    #[doc = "A2 strong driver, sharp edge"]
145    #[inline(always)]
146    pub fn is_sd_she(&self) -> bool {
147        *self == PD1_A::SD_SHE
148    }
149    #[doc = "A2 strong driver, medium edge"]
150    #[inline(always)]
151    pub fn is_sd_mee(&self) -> bool {
152        *self == PD1_A::SD_MEE
153    }
154    #[doc = "A2 strong driver, soft edge"]
155    #[inline(always)]
156    pub fn is_sd_soe(&self) -> bool {
157        *self == PD1_A::SD_SOE
158    }
159    #[doc = "A2 medium driver"]
160    #[inline(always)]
161    pub fn is_md(&self) -> bool {
162        *self == PD1_A::MD
163    }
164    #[doc = "A2 weak driver"]
165    #[inline(always)]
166    pub fn is_wd(&self) -> bool {
167        *self == PD1_A::WD
168    }
169}
170#[doc = "Field `PD1` writer - Pad Driver Mode for Pn.1"]
171pub type PD1_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD1_A>;
172impl<'a, REG> PD1_W<'a, REG>
173where
174    REG: crate::Writable + crate::RegisterSpec,
175    REG::Ux: From<u8>,
176{
177    #[doc = "A2 strong driver, sharp edge"]
178    #[inline(always)]
179    pub fn sd_she(self) -> &'a mut crate::W<REG> {
180        self.variant(PD1_A::SD_SHE)
181    }
182    #[doc = "A2 strong driver, medium edge"]
183    #[inline(always)]
184    pub fn sd_mee(self) -> &'a mut crate::W<REG> {
185        self.variant(PD1_A::SD_MEE)
186    }
187    #[doc = "A2 strong driver, soft edge"]
188    #[inline(always)]
189    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
190        self.variant(PD1_A::SD_SOE)
191    }
192    #[doc = "A2 medium driver"]
193    #[inline(always)]
194    pub fn md(self) -> &'a mut crate::W<REG> {
195        self.variant(PD1_A::MD)
196    }
197    #[doc = "A2 weak driver"]
198    #[inline(always)]
199    pub fn wd(self) -> &'a mut crate::W<REG> {
200        self.variant(PD1_A::WD)
201    }
202}
203#[doc = "Pad Driver Mode for Pn.2\n\nValue on reset: 2"]
204#[derive(Clone, Copy, Debug, PartialEq, Eq)]
205#[repr(u8)]
206pub enum PD2_A {
207    #[doc = "2: A1+ strong driver, soft edge"]
208    SD_SOE = 2,
209    #[doc = "3: A1+ strong driver, slow edge"]
210    SD_SLE = 3,
211    #[doc = "4: A1+ medium driver"]
212    MD = 4,
213    #[doc = "7: A1+ weak driver"]
214    WD = 7,
215    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
216    SD_SOE_ALT = 0,
217    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
218    SD_SLE_ALT = 1,
219    #[doc = "6: A1+ medium driver (alternate value)"]
220    MD_ALT = 6,
221    #[doc = "5: A1+ weak driver (alternate value)"]
222    WD_ALT = 5,
223}
224impl From<PD2_A> for u8 {
225    #[inline(always)]
226    fn from(variant: PD2_A) -> Self {
227        variant as _
228    }
229}
230impl crate::FieldSpec for PD2_A {
231    type Ux = u8;
232}
233impl crate::IsEnum for PD2_A {}
234#[doc = "Field `PD2` reader - Pad Driver Mode for Pn.2"]
235pub type PD2_R = crate::FieldReader<PD2_A>;
236impl PD2_R {
237    #[doc = "Get enumerated values variant"]
238    #[inline(always)]
239    pub const fn variant(&self) -> PD2_A {
240        match self.bits {
241            2 => PD2_A::SD_SOE,
242            3 => PD2_A::SD_SLE,
243            4 => PD2_A::MD,
244            7 => PD2_A::WD,
245            0 => PD2_A::SD_SOE_ALT,
246            1 => PD2_A::SD_SLE_ALT,
247            6 => PD2_A::MD_ALT,
248            5 => PD2_A::WD_ALT,
249            _ => unreachable!(),
250        }
251    }
252    #[doc = "A1+ strong driver, soft edge"]
253    #[inline(always)]
254    pub fn is_sd_soe(&self) -> bool {
255        *self == PD2_A::SD_SOE
256    }
257    #[doc = "A1+ strong driver, slow edge"]
258    #[inline(always)]
259    pub fn is_sd_sle(&self) -> bool {
260        *self == PD2_A::SD_SLE
261    }
262    #[doc = "A1+ medium driver"]
263    #[inline(always)]
264    pub fn is_md(&self) -> bool {
265        *self == PD2_A::MD
266    }
267    #[doc = "A1+ weak driver"]
268    #[inline(always)]
269    pub fn is_wd(&self) -> bool {
270        *self == PD2_A::WD
271    }
272    #[doc = "A1+ strong driver, soft edge (alternate value)"]
273    #[inline(always)]
274    pub fn is_sd_soe_alt(&self) -> bool {
275        *self == PD2_A::SD_SOE_ALT
276    }
277    #[doc = "A1+ strong driver, slow edge (alternate value)"]
278    #[inline(always)]
279    pub fn is_sd_sle_alt(&self) -> bool {
280        *self == PD2_A::SD_SLE_ALT
281    }
282    #[doc = "A1+ medium driver (alternate value)"]
283    #[inline(always)]
284    pub fn is_md_alt(&self) -> bool {
285        *self == PD2_A::MD_ALT
286    }
287    #[doc = "A1+ weak driver (alternate value)"]
288    #[inline(always)]
289    pub fn is_wd_alt(&self) -> bool {
290        *self == PD2_A::WD_ALT
291    }
292}
293#[doc = "Field `PD2` writer - Pad Driver Mode for Pn.2"]
294pub type PD2_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD2_A, crate::Safe>;
295impl<'a, REG> PD2_W<'a, REG>
296where
297    REG: crate::Writable + crate::RegisterSpec,
298    REG::Ux: From<u8>,
299{
300    #[doc = "A1+ strong driver, soft edge"]
301    #[inline(always)]
302    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
303        self.variant(PD2_A::SD_SOE)
304    }
305    #[doc = "A1+ strong driver, slow edge"]
306    #[inline(always)]
307    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
308        self.variant(PD2_A::SD_SLE)
309    }
310    #[doc = "A1+ medium driver"]
311    #[inline(always)]
312    pub fn md(self) -> &'a mut crate::W<REG> {
313        self.variant(PD2_A::MD)
314    }
315    #[doc = "A1+ weak driver"]
316    #[inline(always)]
317    pub fn wd(self) -> &'a mut crate::W<REG> {
318        self.variant(PD2_A::WD)
319    }
320    #[doc = "A1+ strong driver, soft edge (alternate value)"]
321    #[inline(always)]
322    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
323        self.variant(PD2_A::SD_SOE_ALT)
324    }
325    #[doc = "A1+ strong driver, slow edge (alternate value)"]
326    #[inline(always)]
327    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
328        self.variant(PD2_A::SD_SLE_ALT)
329    }
330    #[doc = "A1+ medium driver (alternate value)"]
331    #[inline(always)]
332    pub fn md_alt(self) -> &'a mut crate::W<REG> {
333        self.variant(PD2_A::MD_ALT)
334    }
335    #[doc = "A1+ weak driver (alternate value)"]
336    #[inline(always)]
337    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
338        self.variant(PD2_A::WD_ALT)
339    }
340}
341#[doc = "Pad Driver Mode for Pn.3\n\nValue on reset: 2"]
342#[derive(Clone, Copy, Debug, PartialEq, Eq)]
343#[repr(u8)]
344pub enum PD3_A {
345    #[doc = "2: A1+ strong driver, soft edge"]
346    SD_SOE = 2,
347    #[doc = "3: A1+ strong driver, slow edge"]
348    SD_SLE = 3,
349    #[doc = "4: A1+ medium driver"]
350    MD = 4,
351    #[doc = "7: A1+ weak driver"]
352    WD = 7,
353    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
354    SD_SOE_ALT = 0,
355    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
356    SD_SLE_ALT = 1,
357    #[doc = "6: A1+ medium driver (alternate value)"]
358    MD_ALT = 6,
359    #[doc = "5: A1+ weak driver (alternate value)"]
360    WD_ALT = 5,
361}
362impl From<PD3_A> for u8 {
363    #[inline(always)]
364    fn from(variant: PD3_A) -> Self {
365        variant as _
366    }
367}
368impl crate::FieldSpec for PD3_A {
369    type Ux = u8;
370}
371impl crate::IsEnum for PD3_A {}
372#[doc = "Field `PD3` reader - Pad Driver Mode for Pn.3"]
373pub type PD3_R = crate::FieldReader<PD3_A>;
374impl PD3_R {
375    #[doc = "Get enumerated values variant"]
376    #[inline(always)]
377    pub const fn variant(&self) -> PD3_A {
378        match self.bits {
379            2 => PD3_A::SD_SOE,
380            3 => PD3_A::SD_SLE,
381            4 => PD3_A::MD,
382            7 => PD3_A::WD,
383            0 => PD3_A::SD_SOE_ALT,
384            1 => PD3_A::SD_SLE_ALT,
385            6 => PD3_A::MD_ALT,
386            5 => PD3_A::WD_ALT,
387            _ => unreachable!(),
388        }
389    }
390    #[doc = "A1+ strong driver, soft edge"]
391    #[inline(always)]
392    pub fn is_sd_soe(&self) -> bool {
393        *self == PD3_A::SD_SOE
394    }
395    #[doc = "A1+ strong driver, slow edge"]
396    #[inline(always)]
397    pub fn is_sd_sle(&self) -> bool {
398        *self == PD3_A::SD_SLE
399    }
400    #[doc = "A1+ medium driver"]
401    #[inline(always)]
402    pub fn is_md(&self) -> bool {
403        *self == PD3_A::MD
404    }
405    #[doc = "A1+ weak driver"]
406    #[inline(always)]
407    pub fn is_wd(&self) -> bool {
408        *self == PD3_A::WD
409    }
410    #[doc = "A1+ strong driver, soft edge (alternate value)"]
411    #[inline(always)]
412    pub fn is_sd_soe_alt(&self) -> bool {
413        *self == PD3_A::SD_SOE_ALT
414    }
415    #[doc = "A1+ strong driver, slow edge (alternate value)"]
416    #[inline(always)]
417    pub fn is_sd_sle_alt(&self) -> bool {
418        *self == PD3_A::SD_SLE_ALT
419    }
420    #[doc = "A1+ medium driver (alternate value)"]
421    #[inline(always)]
422    pub fn is_md_alt(&self) -> bool {
423        *self == PD3_A::MD_ALT
424    }
425    #[doc = "A1+ weak driver (alternate value)"]
426    #[inline(always)]
427    pub fn is_wd_alt(&self) -> bool {
428        *self == PD3_A::WD_ALT
429    }
430}
431#[doc = "Field `PD3` writer - Pad Driver Mode for Pn.3"]
432pub type PD3_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD3_A, crate::Safe>;
433impl<'a, REG> PD3_W<'a, REG>
434where
435    REG: crate::Writable + crate::RegisterSpec,
436    REG::Ux: From<u8>,
437{
438    #[doc = "A1+ strong driver, soft edge"]
439    #[inline(always)]
440    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
441        self.variant(PD3_A::SD_SOE)
442    }
443    #[doc = "A1+ strong driver, slow edge"]
444    #[inline(always)]
445    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
446        self.variant(PD3_A::SD_SLE)
447    }
448    #[doc = "A1+ medium driver"]
449    #[inline(always)]
450    pub fn md(self) -> &'a mut crate::W<REG> {
451        self.variant(PD3_A::MD)
452    }
453    #[doc = "A1+ weak driver"]
454    #[inline(always)]
455    pub fn wd(self) -> &'a mut crate::W<REG> {
456        self.variant(PD3_A::WD)
457    }
458    #[doc = "A1+ strong driver, soft edge (alternate value)"]
459    #[inline(always)]
460    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
461        self.variant(PD3_A::SD_SOE_ALT)
462    }
463    #[doc = "A1+ strong driver, slow edge (alternate value)"]
464    #[inline(always)]
465    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
466        self.variant(PD3_A::SD_SLE_ALT)
467    }
468    #[doc = "A1+ medium driver (alternate value)"]
469    #[inline(always)]
470    pub fn md_alt(self) -> &'a mut crate::W<REG> {
471        self.variant(PD3_A::MD_ALT)
472    }
473    #[doc = "A1+ weak driver (alternate value)"]
474    #[inline(always)]
475    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
476        self.variant(PD3_A::WD_ALT)
477    }
478}
479#[doc = "Pad Driver Mode for Pn.4\n\nValue on reset: 2"]
480#[derive(Clone, Copy, Debug, PartialEq, Eq)]
481#[repr(u8)]
482pub enum PD4_A {
483    #[doc = "2: A1+ strong driver, soft edge"]
484    SD_SOE = 2,
485    #[doc = "3: A1+ strong driver, slow edge"]
486    SD_SLE = 3,
487    #[doc = "4: A1+ medium driver"]
488    MD = 4,
489    #[doc = "7: A1+ weak driver"]
490    WD = 7,
491    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
492    SD_SOE_ALT = 0,
493    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
494    SD_SLE_ALT = 1,
495    #[doc = "6: A1+ medium driver (alternate value)"]
496    MD_ALT = 6,
497    #[doc = "5: A1+ weak driver (alternate value)"]
498    WD_ALT = 5,
499}
500impl From<PD4_A> for u8 {
501    #[inline(always)]
502    fn from(variant: PD4_A) -> Self {
503        variant as _
504    }
505}
506impl crate::FieldSpec for PD4_A {
507    type Ux = u8;
508}
509impl crate::IsEnum for PD4_A {}
510#[doc = "Field `PD4` reader - Pad Driver Mode for Pn.4"]
511pub type PD4_R = crate::FieldReader<PD4_A>;
512impl PD4_R {
513    #[doc = "Get enumerated values variant"]
514    #[inline(always)]
515    pub const fn variant(&self) -> PD4_A {
516        match self.bits {
517            2 => PD4_A::SD_SOE,
518            3 => PD4_A::SD_SLE,
519            4 => PD4_A::MD,
520            7 => PD4_A::WD,
521            0 => PD4_A::SD_SOE_ALT,
522            1 => PD4_A::SD_SLE_ALT,
523            6 => PD4_A::MD_ALT,
524            5 => PD4_A::WD_ALT,
525            _ => unreachable!(),
526        }
527    }
528    #[doc = "A1+ strong driver, soft edge"]
529    #[inline(always)]
530    pub fn is_sd_soe(&self) -> bool {
531        *self == PD4_A::SD_SOE
532    }
533    #[doc = "A1+ strong driver, slow edge"]
534    #[inline(always)]
535    pub fn is_sd_sle(&self) -> bool {
536        *self == PD4_A::SD_SLE
537    }
538    #[doc = "A1+ medium driver"]
539    #[inline(always)]
540    pub fn is_md(&self) -> bool {
541        *self == PD4_A::MD
542    }
543    #[doc = "A1+ weak driver"]
544    #[inline(always)]
545    pub fn is_wd(&self) -> bool {
546        *self == PD4_A::WD
547    }
548    #[doc = "A1+ strong driver, soft edge (alternate value)"]
549    #[inline(always)]
550    pub fn is_sd_soe_alt(&self) -> bool {
551        *self == PD4_A::SD_SOE_ALT
552    }
553    #[doc = "A1+ strong driver, slow edge (alternate value)"]
554    #[inline(always)]
555    pub fn is_sd_sle_alt(&self) -> bool {
556        *self == PD4_A::SD_SLE_ALT
557    }
558    #[doc = "A1+ medium driver (alternate value)"]
559    #[inline(always)]
560    pub fn is_md_alt(&self) -> bool {
561        *self == PD4_A::MD_ALT
562    }
563    #[doc = "A1+ weak driver (alternate value)"]
564    #[inline(always)]
565    pub fn is_wd_alt(&self) -> bool {
566        *self == PD4_A::WD_ALT
567    }
568}
569#[doc = "Field `PD4` writer - Pad Driver Mode for Pn.4"]
570pub type PD4_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD4_A, crate::Safe>;
571impl<'a, REG> PD4_W<'a, REG>
572where
573    REG: crate::Writable + crate::RegisterSpec,
574    REG::Ux: From<u8>,
575{
576    #[doc = "A1+ strong driver, soft edge"]
577    #[inline(always)]
578    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
579        self.variant(PD4_A::SD_SOE)
580    }
581    #[doc = "A1+ strong driver, slow edge"]
582    #[inline(always)]
583    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
584        self.variant(PD4_A::SD_SLE)
585    }
586    #[doc = "A1+ medium driver"]
587    #[inline(always)]
588    pub fn md(self) -> &'a mut crate::W<REG> {
589        self.variant(PD4_A::MD)
590    }
591    #[doc = "A1+ weak driver"]
592    #[inline(always)]
593    pub fn wd(self) -> &'a mut crate::W<REG> {
594        self.variant(PD4_A::WD)
595    }
596    #[doc = "A1+ strong driver, soft edge (alternate value)"]
597    #[inline(always)]
598    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
599        self.variant(PD4_A::SD_SOE_ALT)
600    }
601    #[doc = "A1+ strong driver, slow edge (alternate value)"]
602    #[inline(always)]
603    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
604        self.variant(PD4_A::SD_SLE_ALT)
605    }
606    #[doc = "A1+ medium driver (alternate value)"]
607    #[inline(always)]
608    pub fn md_alt(self) -> &'a mut crate::W<REG> {
609        self.variant(PD4_A::MD_ALT)
610    }
611    #[doc = "A1+ weak driver (alternate value)"]
612    #[inline(always)]
613    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
614        self.variant(PD4_A::WD_ALT)
615    }
616}
617#[doc = "Pad Driver Mode for Pn.5\n\nValue on reset: 2"]
618#[derive(Clone, Copy, Debug, PartialEq, Eq)]
619#[repr(u8)]
620pub enum PD5_A {
621    #[doc = "2: A1+ strong driver, soft edge"]
622    SD_SOE = 2,
623    #[doc = "3: A1+ strong driver, slow edge"]
624    SD_SLE = 3,
625    #[doc = "4: A1+ medium driver"]
626    MD = 4,
627    #[doc = "7: A1+ weak driver"]
628    WD = 7,
629    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
630    SD_SOE_ALT = 0,
631    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
632    SD_SLE_ALT = 1,
633    #[doc = "6: A1+ medium driver (alternate value)"]
634    MD_ALT = 6,
635    #[doc = "5: A1+ weak driver (alternate value)"]
636    WD_ALT = 5,
637}
638impl From<PD5_A> for u8 {
639    #[inline(always)]
640    fn from(variant: PD5_A) -> Self {
641        variant as _
642    }
643}
644impl crate::FieldSpec for PD5_A {
645    type Ux = u8;
646}
647impl crate::IsEnum for PD5_A {}
648#[doc = "Field `PD5` reader - Pad Driver Mode for Pn.5"]
649pub type PD5_R = crate::FieldReader<PD5_A>;
650impl PD5_R {
651    #[doc = "Get enumerated values variant"]
652    #[inline(always)]
653    pub const fn variant(&self) -> PD5_A {
654        match self.bits {
655            2 => PD5_A::SD_SOE,
656            3 => PD5_A::SD_SLE,
657            4 => PD5_A::MD,
658            7 => PD5_A::WD,
659            0 => PD5_A::SD_SOE_ALT,
660            1 => PD5_A::SD_SLE_ALT,
661            6 => PD5_A::MD_ALT,
662            5 => PD5_A::WD_ALT,
663            _ => unreachable!(),
664        }
665    }
666    #[doc = "A1+ strong driver, soft edge"]
667    #[inline(always)]
668    pub fn is_sd_soe(&self) -> bool {
669        *self == PD5_A::SD_SOE
670    }
671    #[doc = "A1+ strong driver, slow edge"]
672    #[inline(always)]
673    pub fn is_sd_sle(&self) -> bool {
674        *self == PD5_A::SD_SLE
675    }
676    #[doc = "A1+ medium driver"]
677    #[inline(always)]
678    pub fn is_md(&self) -> bool {
679        *self == PD5_A::MD
680    }
681    #[doc = "A1+ weak driver"]
682    #[inline(always)]
683    pub fn is_wd(&self) -> bool {
684        *self == PD5_A::WD
685    }
686    #[doc = "A1+ strong driver, soft edge (alternate value)"]
687    #[inline(always)]
688    pub fn is_sd_soe_alt(&self) -> bool {
689        *self == PD5_A::SD_SOE_ALT
690    }
691    #[doc = "A1+ strong driver, slow edge (alternate value)"]
692    #[inline(always)]
693    pub fn is_sd_sle_alt(&self) -> bool {
694        *self == PD5_A::SD_SLE_ALT
695    }
696    #[doc = "A1+ medium driver (alternate value)"]
697    #[inline(always)]
698    pub fn is_md_alt(&self) -> bool {
699        *self == PD5_A::MD_ALT
700    }
701    #[doc = "A1+ weak driver (alternate value)"]
702    #[inline(always)]
703    pub fn is_wd_alt(&self) -> bool {
704        *self == PD5_A::WD_ALT
705    }
706}
707#[doc = "Field `PD5` writer - Pad Driver Mode for Pn.5"]
708pub type PD5_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD5_A, crate::Safe>;
709impl<'a, REG> PD5_W<'a, REG>
710where
711    REG: crate::Writable + crate::RegisterSpec,
712    REG::Ux: From<u8>,
713{
714    #[doc = "A1+ strong driver, soft edge"]
715    #[inline(always)]
716    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
717        self.variant(PD5_A::SD_SOE)
718    }
719    #[doc = "A1+ strong driver, slow edge"]
720    #[inline(always)]
721    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
722        self.variant(PD5_A::SD_SLE)
723    }
724    #[doc = "A1+ medium driver"]
725    #[inline(always)]
726    pub fn md(self) -> &'a mut crate::W<REG> {
727        self.variant(PD5_A::MD)
728    }
729    #[doc = "A1+ weak driver"]
730    #[inline(always)]
731    pub fn wd(self) -> &'a mut crate::W<REG> {
732        self.variant(PD5_A::WD)
733    }
734    #[doc = "A1+ strong driver, soft edge (alternate value)"]
735    #[inline(always)]
736    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
737        self.variant(PD5_A::SD_SOE_ALT)
738    }
739    #[doc = "A1+ strong driver, slow edge (alternate value)"]
740    #[inline(always)]
741    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
742        self.variant(PD5_A::SD_SLE_ALT)
743    }
744    #[doc = "A1+ medium driver (alternate value)"]
745    #[inline(always)]
746    pub fn md_alt(self) -> &'a mut crate::W<REG> {
747        self.variant(PD5_A::MD_ALT)
748    }
749    #[doc = "A1+ weak driver (alternate value)"]
750    #[inline(always)]
751    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
752        self.variant(PD5_A::WD_ALT)
753    }
754}
755#[doc = "Pad Driver Mode for Pn.6\n\nValue on reset: 2"]
756#[derive(Clone, Copy, Debug, PartialEq, Eq)]
757#[repr(u8)]
758pub enum PD6_A {
759    #[doc = "2: A1+ strong driver, soft edge"]
760    SD_SOE = 2,
761    #[doc = "3: A1+ strong driver, slow edge"]
762    SD_SLE = 3,
763    #[doc = "4: A1+ medium driver"]
764    MD = 4,
765    #[doc = "7: A1+ weak driver"]
766    WD = 7,
767    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
768    SD_SOE_ALT = 0,
769    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
770    SD_SLE_ALT = 1,
771    #[doc = "6: A1+ medium driver (alternate value)"]
772    MD_ALT = 6,
773    #[doc = "5: A1+ weak driver (alternate value)"]
774    WD_ALT = 5,
775}
776impl From<PD6_A> for u8 {
777    #[inline(always)]
778    fn from(variant: PD6_A) -> Self {
779        variant as _
780    }
781}
782impl crate::FieldSpec for PD6_A {
783    type Ux = u8;
784}
785impl crate::IsEnum for PD6_A {}
786#[doc = "Field `PD6` reader - Pad Driver Mode for Pn.6"]
787pub type PD6_R = crate::FieldReader<PD6_A>;
788impl PD6_R {
789    #[doc = "Get enumerated values variant"]
790    #[inline(always)]
791    pub const fn variant(&self) -> PD6_A {
792        match self.bits {
793            2 => PD6_A::SD_SOE,
794            3 => PD6_A::SD_SLE,
795            4 => PD6_A::MD,
796            7 => PD6_A::WD,
797            0 => PD6_A::SD_SOE_ALT,
798            1 => PD6_A::SD_SLE_ALT,
799            6 => PD6_A::MD_ALT,
800            5 => PD6_A::WD_ALT,
801            _ => unreachable!(),
802        }
803    }
804    #[doc = "A1+ strong driver, soft edge"]
805    #[inline(always)]
806    pub fn is_sd_soe(&self) -> bool {
807        *self == PD6_A::SD_SOE
808    }
809    #[doc = "A1+ strong driver, slow edge"]
810    #[inline(always)]
811    pub fn is_sd_sle(&self) -> bool {
812        *self == PD6_A::SD_SLE
813    }
814    #[doc = "A1+ medium driver"]
815    #[inline(always)]
816    pub fn is_md(&self) -> bool {
817        *self == PD6_A::MD
818    }
819    #[doc = "A1+ weak driver"]
820    #[inline(always)]
821    pub fn is_wd(&self) -> bool {
822        *self == PD6_A::WD
823    }
824    #[doc = "A1+ strong driver, soft edge (alternate value)"]
825    #[inline(always)]
826    pub fn is_sd_soe_alt(&self) -> bool {
827        *self == PD6_A::SD_SOE_ALT
828    }
829    #[doc = "A1+ strong driver, slow edge (alternate value)"]
830    #[inline(always)]
831    pub fn is_sd_sle_alt(&self) -> bool {
832        *self == PD6_A::SD_SLE_ALT
833    }
834    #[doc = "A1+ medium driver (alternate value)"]
835    #[inline(always)]
836    pub fn is_md_alt(&self) -> bool {
837        *self == PD6_A::MD_ALT
838    }
839    #[doc = "A1+ weak driver (alternate value)"]
840    #[inline(always)]
841    pub fn is_wd_alt(&self) -> bool {
842        *self == PD6_A::WD_ALT
843    }
844}
845#[doc = "Field `PD6` writer - Pad Driver Mode for Pn.6"]
846pub type PD6_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD6_A, crate::Safe>;
847impl<'a, REG> PD6_W<'a, REG>
848where
849    REG: crate::Writable + crate::RegisterSpec,
850    REG::Ux: From<u8>,
851{
852    #[doc = "A1+ strong driver, soft edge"]
853    #[inline(always)]
854    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
855        self.variant(PD6_A::SD_SOE)
856    }
857    #[doc = "A1+ strong driver, slow edge"]
858    #[inline(always)]
859    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
860        self.variant(PD6_A::SD_SLE)
861    }
862    #[doc = "A1+ medium driver"]
863    #[inline(always)]
864    pub fn md(self) -> &'a mut crate::W<REG> {
865        self.variant(PD6_A::MD)
866    }
867    #[doc = "A1+ weak driver"]
868    #[inline(always)]
869    pub fn wd(self) -> &'a mut crate::W<REG> {
870        self.variant(PD6_A::WD)
871    }
872    #[doc = "A1+ strong driver, soft edge (alternate value)"]
873    #[inline(always)]
874    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
875        self.variant(PD6_A::SD_SOE_ALT)
876    }
877    #[doc = "A1+ strong driver, slow edge (alternate value)"]
878    #[inline(always)]
879    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
880        self.variant(PD6_A::SD_SLE_ALT)
881    }
882    #[doc = "A1+ medium driver (alternate value)"]
883    #[inline(always)]
884    pub fn md_alt(self) -> &'a mut crate::W<REG> {
885        self.variant(PD6_A::MD_ALT)
886    }
887    #[doc = "A1+ weak driver (alternate value)"]
888    #[inline(always)]
889    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
890        self.variant(PD6_A::WD_ALT)
891    }
892}
893#[doc = "Pad Driver Mode for Pn.7\n\nValue on reset: 2"]
894#[derive(Clone, Copy, Debug, PartialEq, Eq)]
895#[repr(u8)]
896pub enum PD7_A {
897    #[doc = "2: A1+ strong driver, soft edge"]
898    SD_SOE = 2,
899    #[doc = "3: A1+ strong driver, slow edge"]
900    SD_SLE = 3,
901    #[doc = "4: A1+ medium driver"]
902    MD = 4,
903    #[doc = "7: A1+ weak driver"]
904    WD = 7,
905    #[doc = "0: A1+ strong driver, soft edge (alternate value)"]
906    SD_SOE_ALT = 0,
907    #[doc = "1: A1+ strong driver, slow edge (alternate value)"]
908    SD_SLE_ALT = 1,
909    #[doc = "6: A1+ medium driver (alternate value)"]
910    MD_ALT = 6,
911    #[doc = "5: A1+ weak driver (alternate value)"]
912    WD_ALT = 5,
913}
914impl From<PD7_A> for u8 {
915    #[inline(always)]
916    fn from(variant: PD7_A) -> Self {
917        variant as _
918    }
919}
920impl crate::FieldSpec for PD7_A {
921    type Ux = u8;
922}
923impl crate::IsEnum for PD7_A {}
924#[doc = "Field `PD7` reader - Pad Driver Mode for Pn.7"]
925pub type PD7_R = crate::FieldReader<PD7_A>;
926impl PD7_R {
927    #[doc = "Get enumerated values variant"]
928    #[inline(always)]
929    pub const fn variant(&self) -> PD7_A {
930        match self.bits {
931            2 => PD7_A::SD_SOE,
932            3 => PD7_A::SD_SLE,
933            4 => PD7_A::MD,
934            7 => PD7_A::WD,
935            0 => PD7_A::SD_SOE_ALT,
936            1 => PD7_A::SD_SLE_ALT,
937            6 => PD7_A::MD_ALT,
938            5 => PD7_A::WD_ALT,
939            _ => unreachable!(),
940        }
941    }
942    #[doc = "A1+ strong driver, soft edge"]
943    #[inline(always)]
944    pub fn is_sd_soe(&self) -> bool {
945        *self == PD7_A::SD_SOE
946    }
947    #[doc = "A1+ strong driver, slow edge"]
948    #[inline(always)]
949    pub fn is_sd_sle(&self) -> bool {
950        *self == PD7_A::SD_SLE
951    }
952    #[doc = "A1+ medium driver"]
953    #[inline(always)]
954    pub fn is_md(&self) -> bool {
955        *self == PD7_A::MD
956    }
957    #[doc = "A1+ weak driver"]
958    #[inline(always)]
959    pub fn is_wd(&self) -> bool {
960        *self == PD7_A::WD
961    }
962    #[doc = "A1+ strong driver, soft edge (alternate value)"]
963    #[inline(always)]
964    pub fn is_sd_soe_alt(&self) -> bool {
965        *self == PD7_A::SD_SOE_ALT
966    }
967    #[doc = "A1+ strong driver, slow edge (alternate value)"]
968    #[inline(always)]
969    pub fn is_sd_sle_alt(&self) -> bool {
970        *self == PD7_A::SD_SLE_ALT
971    }
972    #[doc = "A1+ medium driver (alternate value)"]
973    #[inline(always)]
974    pub fn is_md_alt(&self) -> bool {
975        *self == PD7_A::MD_ALT
976    }
977    #[doc = "A1+ weak driver (alternate value)"]
978    #[inline(always)]
979    pub fn is_wd_alt(&self) -> bool {
980        *self == PD7_A::WD_ALT
981    }
982}
983#[doc = "Field `PD7` writer - Pad Driver Mode for Pn.7"]
984pub type PD7_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PD7_A, crate::Safe>;
985impl<'a, REG> PD7_W<'a, REG>
986where
987    REG: crate::Writable + crate::RegisterSpec,
988    REG::Ux: From<u8>,
989{
990    #[doc = "A1+ strong driver, soft edge"]
991    #[inline(always)]
992    pub fn sd_soe(self) -> &'a mut crate::W<REG> {
993        self.variant(PD7_A::SD_SOE)
994    }
995    #[doc = "A1+ strong driver, slow edge"]
996    #[inline(always)]
997    pub fn sd_sle(self) -> &'a mut crate::W<REG> {
998        self.variant(PD7_A::SD_SLE)
999    }
1000    #[doc = "A1+ medium driver"]
1001    #[inline(always)]
1002    pub fn md(self) -> &'a mut crate::W<REG> {
1003        self.variant(PD7_A::MD)
1004    }
1005    #[doc = "A1+ weak driver"]
1006    #[inline(always)]
1007    pub fn wd(self) -> &'a mut crate::W<REG> {
1008        self.variant(PD7_A::WD)
1009    }
1010    #[doc = "A1+ strong driver, soft edge (alternate value)"]
1011    #[inline(always)]
1012    pub fn sd_soe_alt(self) -> &'a mut crate::W<REG> {
1013        self.variant(PD7_A::SD_SOE_ALT)
1014    }
1015    #[doc = "A1+ strong driver, slow edge (alternate value)"]
1016    #[inline(always)]
1017    pub fn sd_sle_alt(self) -> &'a mut crate::W<REG> {
1018        self.variant(PD7_A::SD_SLE_ALT)
1019    }
1020    #[doc = "A1+ medium driver (alternate value)"]
1021    #[inline(always)]
1022    pub fn md_alt(self) -> &'a mut crate::W<REG> {
1023        self.variant(PD7_A::MD_ALT)
1024    }
1025    #[doc = "A1+ weak driver (alternate value)"]
1026    #[inline(always)]
1027    pub fn wd_alt(self) -> &'a mut crate::W<REG> {
1028        self.variant(PD7_A::WD_ALT)
1029    }
1030}
1031impl R {
1032    #[doc = "Bits 0:2 - Pad Driver Mode for Pn.0"]
1033    #[inline(always)]
1034    pub fn pd0(&self) -> PD0_R {
1035        PD0_R::new((self.bits & 7) as u8)
1036    }
1037    #[doc = "Bits 4:6 - Pad Driver Mode for Pn.1"]
1038    #[inline(always)]
1039    pub fn pd1(&self) -> PD1_R {
1040        PD1_R::new(((self.bits >> 4) & 7) as u8)
1041    }
1042    #[doc = "Bits 8:10 - Pad Driver Mode for Pn.2"]
1043    #[inline(always)]
1044    pub fn pd2(&self) -> PD2_R {
1045        PD2_R::new(((self.bits >> 8) & 7) as u8)
1046    }
1047    #[doc = "Bits 12:14 - Pad Driver Mode for Pn.3"]
1048    #[inline(always)]
1049    pub fn pd3(&self) -> PD3_R {
1050        PD3_R::new(((self.bits >> 12) & 7) as u8)
1051    }
1052    #[doc = "Bits 16:18 - Pad Driver Mode for Pn.4"]
1053    #[inline(always)]
1054    pub fn pd4(&self) -> PD4_R {
1055        PD4_R::new(((self.bits >> 16) & 7) as u8)
1056    }
1057    #[doc = "Bits 20:22 - Pad Driver Mode for Pn.5"]
1058    #[inline(always)]
1059    pub fn pd5(&self) -> PD5_R {
1060        PD5_R::new(((self.bits >> 20) & 7) as u8)
1061    }
1062    #[doc = "Bits 24:26 - Pad Driver Mode for Pn.6"]
1063    #[inline(always)]
1064    pub fn pd6(&self) -> PD6_R {
1065        PD6_R::new(((self.bits >> 24) & 7) as u8)
1066    }
1067    #[doc = "Bits 28:30 - Pad Driver Mode for Pn.7"]
1068    #[inline(always)]
1069    pub fn pd7(&self) -> PD7_R {
1070        PD7_R::new(((self.bits >> 28) & 7) as u8)
1071    }
1072}
1073impl W {
1074    #[doc = "Bits 0:2 - Pad Driver Mode for Pn.0"]
1075    #[inline(always)]
1076    pub fn pd0(&mut self) -> PD0_W<PDR0_SPEC> {
1077        PD0_W::new(self, 0)
1078    }
1079    #[doc = "Bits 4:6 - Pad Driver Mode for Pn.1"]
1080    #[inline(always)]
1081    pub fn pd1(&mut self) -> PD1_W<PDR0_SPEC> {
1082        PD1_W::new(self, 4)
1083    }
1084    #[doc = "Bits 8:10 - Pad Driver Mode for Pn.2"]
1085    #[inline(always)]
1086    pub fn pd2(&mut self) -> PD2_W<PDR0_SPEC> {
1087        PD2_W::new(self, 8)
1088    }
1089    #[doc = "Bits 12:14 - Pad Driver Mode for Pn.3"]
1090    #[inline(always)]
1091    pub fn pd3(&mut self) -> PD3_W<PDR0_SPEC> {
1092        PD3_W::new(self, 12)
1093    }
1094    #[doc = "Bits 16:18 - Pad Driver Mode for Pn.4"]
1095    #[inline(always)]
1096    pub fn pd4(&mut self) -> PD4_W<PDR0_SPEC> {
1097        PD4_W::new(self, 16)
1098    }
1099    #[doc = "Bits 20:22 - Pad Driver Mode for Pn.5"]
1100    #[inline(always)]
1101    pub fn pd5(&mut self) -> PD5_W<PDR0_SPEC> {
1102        PD5_W::new(self, 20)
1103    }
1104    #[doc = "Bits 24:26 - Pad Driver Mode for Pn.6"]
1105    #[inline(always)]
1106    pub fn pd6(&mut self) -> PD6_W<PDR0_SPEC> {
1107        PD6_W::new(self, 24)
1108    }
1109    #[doc = "Bits 28:30 - Pad Driver Mode for Pn.7"]
1110    #[inline(always)]
1111    pub fn pd7(&mut self) -> PD7_W<PDR0_SPEC> {
1112        PD7_W::new(self, 28)
1113    }
1114}
1115#[doc = "Port 4 Pad Driver Mode 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1116pub struct PDR0_SPEC;
1117impl crate::RegisterSpec for PDR0_SPEC {
1118    type Ux = u32;
1119}
1120#[doc = "`read()` method returns [`pdr0::R`](R) reader structure"]
1121impl crate::Readable for PDR0_SPEC {}
1122#[doc = "`write(|w| ..)` method takes [`pdr0::W`](W) writer structure"]
1123impl crate::Writable for PDR0_SPEC {
1124    type Safety = crate::Unsafe;
1125    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1126    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1127}
1128#[doc = "`reset()` method sets PDR0 to value 0x2222_2222"]
1129impl crate::Resettable for PDR0_SPEC {
1130    const RESET_VALUE: u32 = 0x2222_2222;
1131}
xmc4700/port4/pdr0.rs

xmc4700/port4/
pdr0.rs
