xmc4500/sdmmc/
clock_ctrl.rs

1#[doc = "Register `CLOCK_CTRL` reader"]
2pub type R = crate::R<CLOCK_CTRL_SPEC>;
3#[doc = "Register `CLOCK_CTRL` writer"]
4pub type W = crate::W<CLOCK_CTRL_SPEC>;
5#[doc = "Internal Clock Enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum INTERNAL_CLOCK_EN_A {
8    #[doc = "0: Stop"]
9    VALUE1 = 0,
10    #[doc = "1: Oscillate"]
11    VALUE2 = 1,
12}
13impl From<INTERNAL_CLOCK_EN_A> for bool {
14    #[inline(always)]
15    fn from(variant: INTERNAL_CLOCK_EN_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `INTERNAL_CLOCK_EN` reader - Internal Clock Enable"]
20pub type INTERNAL_CLOCK_EN_R = crate::BitReader<INTERNAL_CLOCK_EN_A>;
21impl INTERNAL_CLOCK_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> INTERNAL_CLOCK_EN_A {
25        match self.bits {
26            false => INTERNAL_CLOCK_EN_A::VALUE1,
27            true => INTERNAL_CLOCK_EN_A::VALUE2,
28        }
29    }
30    #[doc = "Stop"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == INTERNAL_CLOCK_EN_A::VALUE1
34    }
35    #[doc = "Oscillate"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == INTERNAL_CLOCK_EN_A::VALUE2
39    }
40}
41#[doc = "Field `INTERNAL_CLOCK_EN` writer - Internal Clock Enable"]
42pub type INTERNAL_CLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG, INTERNAL_CLOCK_EN_A>;
43impl<'a, REG> INTERNAL_CLOCK_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Stop"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(INTERNAL_CLOCK_EN_A::VALUE1)
51    }
52    #[doc = "Oscillate"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(INTERNAL_CLOCK_EN_A::VALUE2)
56    }
57}
58#[doc = "Internal Clock Stable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum INTERNAL_CLOCK_STABLE_A {
61    #[doc = "0: Not Ready"]
62    VALUE1 = 0,
63    #[doc = "1: Ready"]
64    VALUE2 = 1,
65}
66impl From<INTERNAL_CLOCK_STABLE_A> for bool {
67    #[inline(always)]
68    fn from(variant: INTERNAL_CLOCK_STABLE_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `INTERNAL_CLOCK_STABLE` reader - Internal Clock Stable"]
73pub type INTERNAL_CLOCK_STABLE_R = crate::BitReader<INTERNAL_CLOCK_STABLE_A>;
74impl INTERNAL_CLOCK_STABLE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> INTERNAL_CLOCK_STABLE_A {
78        match self.bits {
79            false => INTERNAL_CLOCK_STABLE_A::VALUE1,
80            true => INTERNAL_CLOCK_STABLE_A::VALUE2,
81        }
82    }
83    #[doc = "Not Ready"]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == INTERNAL_CLOCK_STABLE_A::VALUE1
87    }
88    #[doc = "Ready"]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == INTERNAL_CLOCK_STABLE_A::VALUE2
92    }
93}
94#[doc = "SD Clock Enable\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum SDCLOCK_EN_A {
97    #[doc = "0: Disable"]
98    VALUE1 = 0,
99    #[doc = "1: Enable"]
100    VALUE2 = 1,
101}
102impl From<SDCLOCK_EN_A> for bool {
103    #[inline(always)]
104    fn from(variant: SDCLOCK_EN_A) -> Self {
105        variant as u8 != 0
106    }
107}
108#[doc = "Field `SDCLOCK_EN` reader - SD Clock Enable"]
109pub type SDCLOCK_EN_R = crate::BitReader<SDCLOCK_EN_A>;
110impl SDCLOCK_EN_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub const fn variant(&self) -> SDCLOCK_EN_A {
114        match self.bits {
115            false => SDCLOCK_EN_A::VALUE1,
116            true => SDCLOCK_EN_A::VALUE2,
117        }
118    }
119    #[doc = "Disable"]
120    #[inline(always)]
121    pub fn is_value1(&self) -> bool {
122        *self == SDCLOCK_EN_A::VALUE1
123    }
124    #[doc = "Enable"]
125    #[inline(always)]
126    pub fn is_value2(&self) -> bool {
127        *self == SDCLOCK_EN_A::VALUE2
128    }
129}
130#[doc = "Field `SDCLOCK_EN` writer - SD Clock Enable"]
131pub type SDCLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG, SDCLOCK_EN_A>;
132impl<'a, REG> SDCLOCK_EN_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135{
136    #[doc = "Disable"]
137    #[inline(always)]
138    pub fn value1(self) -> &'a mut crate::W<REG> {
139        self.variant(SDCLOCK_EN_A::VALUE1)
140    }
141    #[doc = "Enable"]
142    #[inline(always)]
143    pub fn value2(self) -> &'a mut crate::W<REG> {
144        self.variant(SDCLOCK_EN_A::VALUE2)
145    }
146}
147#[doc = "SDCLK Frequency Select\n\nValue on reset: 0"]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum SDCLK_FREQ_SEL_A {
151    #[doc = "0: base clock(10MHz-63MHz)"]
152    VALUE1 = 0,
153    #[doc = "1: base clock divided by 2"]
154    VALUE2 = 1,
155    #[doc = "16: base clock divided by 32"]
156    VALUE3 = 16,
157    #[doc = "2: base clock divided by 4"]
158    VALUE4 = 2,
159    #[doc = "4: base clock divided by 8"]
160    VALUE5 = 4,
161    #[doc = "8: base clock divided by 16"]
162    VALUE6 = 8,
163    #[doc = "32: base clock divided by 64"]
164    VALUE7 = 32,
165    #[doc = "64: base clock divided by 128"]
166    VALUE8 = 64,
167    #[doc = "128: base clock divided by 256"]
168    VALUE9 = 128,
169}
170impl From<SDCLK_FREQ_SEL_A> for u8 {
171    #[inline(always)]
172    fn from(variant: SDCLK_FREQ_SEL_A) -> Self {
173        variant as _
174    }
175}
176impl crate::FieldSpec for SDCLK_FREQ_SEL_A {
177    type Ux = u8;
178}
179impl crate::IsEnum for SDCLK_FREQ_SEL_A {}
180#[doc = "Field `SDCLK_FREQ_SEL` reader - SDCLK Frequency Select"]
181pub type SDCLK_FREQ_SEL_R = crate::FieldReader<SDCLK_FREQ_SEL_A>;
182impl SDCLK_FREQ_SEL_R {
183    #[doc = "Get enumerated values variant"]
184    #[inline(always)]
185    pub const fn variant(&self) -> Option<SDCLK_FREQ_SEL_A> {
186        match self.bits {
187            0 => Some(SDCLK_FREQ_SEL_A::VALUE1),
188            1 => Some(SDCLK_FREQ_SEL_A::VALUE2),
189            16 => Some(SDCLK_FREQ_SEL_A::VALUE3),
190            2 => Some(SDCLK_FREQ_SEL_A::VALUE4),
191            4 => Some(SDCLK_FREQ_SEL_A::VALUE5),
192            8 => Some(SDCLK_FREQ_SEL_A::VALUE6),
193            32 => Some(SDCLK_FREQ_SEL_A::VALUE7),
194            64 => Some(SDCLK_FREQ_SEL_A::VALUE8),
195            128 => Some(SDCLK_FREQ_SEL_A::VALUE9),
196            _ => None,
197        }
198    }
199    #[doc = "base clock(10MHz-63MHz)"]
200    #[inline(always)]
201    pub fn is_value1(&self) -> bool {
202        *self == SDCLK_FREQ_SEL_A::VALUE1
203    }
204    #[doc = "base clock divided by 2"]
205    #[inline(always)]
206    pub fn is_value2(&self) -> bool {
207        *self == SDCLK_FREQ_SEL_A::VALUE2
208    }
209    #[doc = "base clock divided by 32"]
210    #[inline(always)]
211    pub fn is_value3(&self) -> bool {
212        *self == SDCLK_FREQ_SEL_A::VALUE3
213    }
214    #[doc = "base clock divided by 4"]
215    #[inline(always)]
216    pub fn is_value4(&self) -> bool {
217        *self == SDCLK_FREQ_SEL_A::VALUE4
218    }
219    #[doc = "base clock divided by 8"]
220    #[inline(always)]
221    pub fn is_value5(&self) -> bool {
222        *self == SDCLK_FREQ_SEL_A::VALUE5
223    }
224    #[doc = "base clock divided by 16"]
225    #[inline(always)]
226    pub fn is_value6(&self) -> bool {
227        *self == SDCLK_FREQ_SEL_A::VALUE6
228    }
229    #[doc = "base clock divided by 64"]
230    #[inline(always)]
231    pub fn is_value7(&self) -> bool {
232        *self == SDCLK_FREQ_SEL_A::VALUE7
233    }
234    #[doc = "base clock divided by 128"]
235    #[inline(always)]
236    pub fn is_value8(&self) -> bool {
237        *self == SDCLK_FREQ_SEL_A::VALUE8
238    }
239    #[doc = "base clock divided by 256"]
240    #[inline(always)]
241    pub fn is_value9(&self) -> bool {
242        *self == SDCLK_FREQ_SEL_A::VALUE9
243    }
244}
245#[doc = "Field `SDCLK_FREQ_SEL` writer - SDCLK Frequency Select"]
246pub type SDCLK_FREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8, SDCLK_FREQ_SEL_A>;
247impl<'a, REG> SDCLK_FREQ_SEL_W<'a, REG>
248where
249    REG: crate::Writable + crate::RegisterSpec,
250    REG::Ux: From<u8>,
251{
252    #[doc = "base clock(10MHz-63MHz)"]
253    #[inline(always)]
254    pub fn value1(self) -> &'a mut crate::W<REG> {
255        self.variant(SDCLK_FREQ_SEL_A::VALUE1)
256    }
257    #[doc = "base clock divided by 2"]
258    #[inline(always)]
259    pub fn value2(self) -> &'a mut crate::W<REG> {
260        self.variant(SDCLK_FREQ_SEL_A::VALUE2)
261    }
262    #[doc = "base clock divided by 32"]
263    #[inline(always)]
264    pub fn value3(self) -> &'a mut crate::W<REG> {
265        self.variant(SDCLK_FREQ_SEL_A::VALUE3)
266    }
267    #[doc = "base clock divided by 4"]
268    #[inline(always)]
269    pub fn value4(self) -> &'a mut crate::W<REG> {
270        self.variant(SDCLK_FREQ_SEL_A::VALUE4)
271    }
272    #[doc = "base clock divided by 8"]
273    #[inline(always)]
274    pub fn value5(self) -> &'a mut crate::W<REG> {
275        self.variant(SDCLK_FREQ_SEL_A::VALUE5)
276    }
277    #[doc = "base clock divided by 16"]
278    #[inline(always)]
279    pub fn value6(self) -> &'a mut crate::W<REG> {
280        self.variant(SDCLK_FREQ_SEL_A::VALUE6)
281    }
282    #[doc = "base clock divided by 64"]
283    #[inline(always)]
284    pub fn value7(self) -> &'a mut crate::W<REG> {
285        self.variant(SDCLK_FREQ_SEL_A::VALUE7)
286    }
287    #[doc = "base clock divided by 128"]
288    #[inline(always)]
289    pub fn value8(self) -> &'a mut crate::W<REG> {
290        self.variant(SDCLK_FREQ_SEL_A::VALUE8)
291    }
292    #[doc = "base clock divided by 256"]
293    #[inline(always)]
294    pub fn value9(self) -> &'a mut crate::W<REG> {
295        self.variant(SDCLK_FREQ_SEL_A::VALUE9)
296    }
297}
298impl R {
299    #[doc = "Bit 0 - Internal Clock Enable"]
300    #[inline(always)]
301    pub fn internal_clock_en(&self) -> INTERNAL_CLOCK_EN_R {
302        INTERNAL_CLOCK_EN_R::new((self.bits & 1) != 0)
303    }
304    #[doc = "Bit 1 - Internal Clock Stable"]
305    #[inline(always)]
306    pub fn internal_clock_stable(&self) -> INTERNAL_CLOCK_STABLE_R {
307        INTERNAL_CLOCK_STABLE_R::new(((self.bits >> 1) & 1) != 0)
308    }
309    #[doc = "Bit 2 - SD Clock Enable"]
310    #[inline(always)]
311    pub fn sdclock_en(&self) -> SDCLOCK_EN_R {
312        SDCLOCK_EN_R::new(((self.bits >> 2) & 1) != 0)
313    }
314    #[doc = "Bits 8:15 - SDCLK Frequency Select"]
315    #[inline(always)]
316    pub fn sdclk_freq_sel(&self) -> SDCLK_FREQ_SEL_R {
317        SDCLK_FREQ_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
318    }
319}
320impl W {
321    #[doc = "Bit 0 - Internal Clock Enable"]
322    #[inline(always)]
323    pub fn internal_clock_en(&mut self) -> INTERNAL_CLOCK_EN_W<CLOCK_CTRL_SPEC> {
324        INTERNAL_CLOCK_EN_W::new(self, 0)
325    }
326    #[doc = "Bit 2 - SD Clock Enable"]
327    #[inline(always)]
328    pub fn sdclock_en(&mut self) -> SDCLOCK_EN_W<CLOCK_CTRL_SPEC> {
329        SDCLOCK_EN_W::new(self, 2)
330    }
331    #[doc = "Bits 8:15 - SDCLK Frequency Select"]
332    #[inline(always)]
333    pub fn sdclk_freq_sel(&mut self) -> SDCLK_FREQ_SEL_W<CLOCK_CTRL_SPEC> {
334        SDCLK_FREQ_SEL_W::new(self, 8)
335    }
336}
337#[doc = "Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
338pub struct CLOCK_CTRL_SPEC;
339impl crate::RegisterSpec for CLOCK_CTRL_SPEC {
340    type Ux = u16;
341}
342#[doc = "`read()` method returns [`clock_ctrl::R`](R) reader structure"]
343impl crate::Readable for CLOCK_CTRL_SPEC {}
344#[doc = "`write(|w| ..)` method takes [`clock_ctrl::W`](W) writer structure"]
345impl crate::Writable for CLOCK_CTRL_SPEC {
346    type Safety = crate::Unsafe;
347    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
348    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
349}
350#[doc = "`reset()` method sets CLOCK_CTRL to value 0"]
351impl crate::Resettable for CLOCK_CTRL_SPEC {
352    const RESET_VALUE: u16 = 0;
353}
xmc4500/sdmmc/clock_ctrl.rs

xmc4500/sdmmc/
clock_ctrl.rs
