xmc4500/can/
clc.rs

1#[doc = "Register `CLC` reader"]
2pub type R = crate::R<CLC_SPEC>;
3#[doc = "Register `CLC` writer"]
4pub type W = crate::W<CLC_SPEC>;
5#[doc = "Field `DISR` reader - Module Disable Request Bit"]
6pub type DISR_R = crate::BitReader;
7#[doc = "Field `DISR` writer - Module Disable Request Bit"]
8pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DISS` reader - Module Disable Status Bit"]
10pub type DISS_R = crate::BitReader;
11#[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
12pub type EDIS_R = crate::BitReader;
13#[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
14pub type EDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `SBWE` writer - Module Suspend Bit Write Enable for OCDS"]
16pub type SBWE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Module Disable Request Bit"]
19    #[inline(always)]
20    pub fn disr(&self) -> DISR_R {
21        DISR_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Module Disable Status Bit"]
24    #[inline(always)]
25    pub fn diss(&self) -> DISS_R {
26        DISS_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 3 - Sleep Mode Enable Control"]
29    #[inline(always)]
30    pub fn edis(&self) -> EDIS_R {
31        EDIS_R::new(((self.bits >> 3) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bit 0 - Module Disable Request Bit"]
36    #[inline(always)]
37    pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
38        DISR_W::new(self, 0)
39    }
40    #[doc = "Bit 3 - Sleep Mode Enable Control"]
41    #[inline(always)]
42    pub fn edis(&mut self) -> EDIS_W<CLC_SPEC> {
43        EDIS_W::new(self, 3)
44    }
45    #[doc = "Bit 4 - Module Suspend Bit Write Enable for OCDS"]
46    #[inline(always)]
47    pub fn sbwe(&mut self) -> SBWE_W<CLC_SPEC> {
48        SBWE_W::new(self, 4)
49    }
50}
51#[doc = "CAN Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52pub struct CLC_SPEC;
53impl crate::RegisterSpec for CLC_SPEC {
54    type Ux = u32;
55}
56#[doc = "`read()` method returns [`clc::R`](R) reader structure"]
57impl crate::Readable for CLC_SPEC {}
58#[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
59impl crate::Writable for CLC_SPEC {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets CLC to value 0x03"]
65impl crate::Resettable for CLC_SPEC {
66    const RESET_VALUE: u32 = 0x03;
67}
xmc4500/can/clc.rs

xmc4500/can/
clc.rs
