xmc4500/dsd_ch0/
modcfg.rs

1#[doc = "Register `MODCFG` reader"]
2pub type R = crate::R<MODCFG_SPEC>;
3#[doc = "Register `MODCFG` writer"]
4pub type W = crate::W<MODCFG_SPEC>;
5#[doc = "Divider Factor for Modulator Clock\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum DIVM_A {
9    #[doc = "0: fMOD = fCLK / 2"]
10    VALUE1 = 0,
11    #[doc = "1: fMOD = fCLK / 4"]
12    VALUE2 = 1,
13    #[doc = "2: fMOD = fCLK / 6"]
14    VALUE3 = 2,
15    #[doc = "15: fMOD = fCLK / 32"]
16    VALUE4 = 15,
17}
18impl From<DIVM_A> for u8 {
19    #[inline(always)]
20    fn from(variant: DIVM_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for DIVM_A {
25    type Ux = u8;
26}
27impl crate::IsEnum for DIVM_A {}
28#[doc = "Field `DIVM` reader - Divider Factor for Modulator Clock"]
29pub type DIVM_R = crate::FieldReader<DIVM_A>;
30impl DIVM_R {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Option<DIVM_A> {
34        match self.bits {
35            0 => Some(DIVM_A::VALUE1),
36            1 => Some(DIVM_A::VALUE2),
37            2 => Some(DIVM_A::VALUE3),
38            15 => Some(DIVM_A::VALUE4),
39            _ => None,
40        }
41    }
42    #[doc = "fMOD = fCLK / 2"]
43    #[inline(always)]
44    pub fn is_value1(&self) -> bool {
45        *self == DIVM_A::VALUE1
46    }
47    #[doc = "fMOD = fCLK / 4"]
48    #[inline(always)]
49    pub fn is_value2(&self) -> bool {
50        *self == DIVM_A::VALUE2
51    }
52    #[doc = "fMOD = fCLK / 6"]
53    #[inline(always)]
54    pub fn is_value3(&self) -> bool {
55        *self == DIVM_A::VALUE3
56    }
57    #[doc = "fMOD = fCLK / 32"]
58    #[inline(always)]
59    pub fn is_value4(&self) -> bool {
60        *self == DIVM_A::VALUE4
61    }
62}
63#[doc = "Field `DIVM` writer - Divider Factor for Modulator Clock"]
64pub type DIVM_W<'a, REG> = crate::FieldWriter<'a, REG, 4, DIVM_A>;
65impl<'a, REG> DIVM_W<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "fMOD = fCLK / 2"]
71    #[inline(always)]
72    pub fn value1(self) -> &'a mut crate::W<REG> {
73        self.variant(DIVM_A::VALUE1)
74    }
75    #[doc = "fMOD = fCLK / 4"]
76    #[inline(always)]
77    pub fn value2(self) -> &'a mut crate::W<REG> {
78        self.variant(DIVM_A::VALUE2)
79    }
80    #[doc = "fMOD = fCLK / 6"]
81    #[inline(always)]
82    pub fn value3(self) -> &'a mut crate::W<REG> {
83        self.variant(DIVM_A::VALUE3)
84    }
85    #[doc = "fMOD = fCLK / 32"]
86    #[inline(always)]
87    pub fn value4(self) -> &'a mut crate::W<REG> {
88        self.variant(DIVM_A::VALUE4)
89    }
90}
91#[doc = "Write Control for Divider Factor\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum DWC_A {
94    #[doc = "0: No write access to divider factor"]
95    VALUE1 = 0,
96    #[doc = "1: Bitfield DIVM can be written"]
97    VALUE2 = 1,
98}
99impl From<DWC_A> for bool {
100    #[inline(always)]
101    fn from(variant: DWC_A) -> Self {
102        variant as u8 != 0
103    }
104}
105#[doc = "Field `DWC` writer - Write Control for Divider Factor"]
106pub type DWC_W<'a, REG> = crate::BitWriter<'a, REG, DWC_A>;
107impl<'a, REG> DWC_W<'a, REG>
108where
109    REG: crate::Writable + crate::RegisterSpec,
110{
111    #[doc = "No write access to divider factor"]
112    #[inline(always)]
113    pub fn value1(self) -> &'a mut crate::W<REG> {
114        self.variant(DWC_A::VALUE1)
115    }
116    #[doc = "Bitfield DIVM can be written"]
117    #[inline(always)]
118    pub fn value2(self) -> &'a mut crate::W<REG> {
119        self.variant(DWC_A::VALUE2)
120    }
121}
122impl R {
123    #[doc = "Bits 16:19 - Divider Factor for Modulator Clock"]
124    #[inline(always)]
125    pub fn divm(&self) -> DIVM_R {
126        DIVM_R::new(((self.bits >> 16) & 0x0f) as u8)
127    }
128}
129impl W {
130    #[doc = "Bits 16:19 - Divider Factor for Modulator Clock"]
131    #[inline(always)]
132    pub fn divm(&mut self) -> DIVM_W<MODCFG_SPEC> {
133        DIVM_W::new(self, 16)
134    }
135    #[doc = "Bit 23 - Write Control for Divider Factor"]
136    #[inline(always)]
137    pub fn dwc(&mut self) -> DWC_W<MODCFG_SPEC> {
138        DWC_W::new(self, 23)
139    }
140}
141#[doc = "Modulator Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`modcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
142pub struct MODCFG_SPEC;
143impl crate::RegisterSpec for MODCFG_SPEC {
144    type Ux = u32;
145}
146#[doc = "`read()` method returns [`modcfg::R`](R) reader structure"]
147impl crate::Readable for MODCFG_SPEC {}
148#[doc = "`write(|w| ..)` method takes [`modcfg::W`](W) writer structure"]
149impl crate::Writable for MODCFG_SPEC {
150    type Safety = crate::Unsafe;
151    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
152    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
153}
154#[doc = "`reset()` method sets MODCFG to value 0"]
155impl crate::Resettable for MODCFG_SPEC {
156    const RESET_VALUE: u32 = 0;
157}
xmc4500/dsd_ch0/modcfg.rs

xmc4500/dsd_ch0/
modcfg.rs
