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#[doc = "Reader of register BRSCTRL"] pub type R = crate::R<u32, super::BRSCTRL>; #[doc = "Writer for register BRSCTRL"] pub type W = crate::W<u32, super::BRSCTRL>; #[doc = "Register BRSCTRL `reset()`'s with value 0"] impl crate::ResetValue for super::BRSCTRL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Source-specific Result Register\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum SRCRESREG_A { #[doc = "0: Use GxCHCTRy.RESREG to select a group result register"] VALUE1 = 0, #[doc = "1: Store result in group result register GxRES1"] VALUE2 = 1, #[doc = "15: Store result in group result register GxRES15"] VALUE3 = 15, } impl From<SRCRESREG_A> for u8 { #[inline(always)] fn from(variant: SRCRESREG_A) -> Self { variant as _ } } #[doc = "Reader of field `SRCRESREG`"] pub type SRCRESREG_R = crate::R<u8, SRCRESREG_A>; impl SRCRESREG_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, SRCRESREG_A> { use crate::Variant::*; match self.bits { 0 => Val(SRCRESREG_A::VALUE1), 1 => Val(SRCRESREG_A::VALUE2), 15 => Val(SRCRESREG_A::VALUE3), i => Res(i), } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == SRCRESREG_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == SRCRESREG_A::VALUE2 } #[doc = "Checks if the value of the field is `VALUE3`"] #[inline(always)] pub fn is_value3(&self) -> bool { *self == SRCRESREG_A::VALUE3 } } #[doc = "Write proxy for field `SRCRESREG`"] pub struct SRCRESREG_W<'a> { w: &'a mut W, } impl<'a> SRCRESREG_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: SRCRESREG_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Use GxCHCTRy.RESREG to select a group result register"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE1) } #[doc = "Store result in group result register GxRES1"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE2) } #[doc = "Store result in group result register GxRES15"] #[inline(always)] pub fn value3(self) -> &'a mut W { self.variant(SRCRESREG_A::VALUE3) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); self.w } } #[doc = "Reader of field `XTSEL`"] pub type XTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `XTSEL`"] pub struct XTSEL_W<'a> { w: &'a mut W, } impl<'a> XTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8); self.w } } #[doc = "Reader of field `XTLVL`"] pub type XTLVL_R = crate::R<bool, bool>; #[doc = "Trigger Operating Mode\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum XTMODE_A { #[doc = "0: No external trigger"] VALUE1 = 0, #[doc = "1: Trigger event upon a falling edge"] VALUE2 = 1, #[doc = "2: Trigger event upon a rising edge"] VALUE3 = 2, #[doc = "3: Trigger event upon any edge"] VALUE4 = 3, } impl From<XTMODE_A> for u8 { #[inline(always)] fn from(variant: XTMODE_A) -> Self { variant as _ } } #[doc = "Reader of field `XTMODE`"] pub type XTMODE_R = crate::R<u8, XTMODE_A>; impl XTMODE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> XTMODE_A { match self.bits { 0 => XTMODE_A::VALUE1, 1 => XTMODE_A::VALUE2, 2 => XTMODE_A::VALUE3, 3 => XTMODE_A::VALUE4, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `VALUE1`"] #[inline(always)] pub fn is_value1(&self) -> bool { *self == XTMODE_A::VALUE1 } #[doc = "Checks if the value of the field is `VALUE2`"] #[inline(always)] pub fn is_value2(&self) -> bool { *self == XTMODE_A::VALUE2 } #[doc = "Checks if the value of the field is `VALUE3`"] #[inline(always)] pub fn is_value3(&self) -> bool { *self == XTMODE_A::VALUE3 } #[doc = "Checks if the value of the field is `VALUE4`"] #[inline(always)] pub fn is_value4(&self) -> bool { *self == XTMODE_A::VALUE4 } } #[doc = "Write proxy for field `XTMODE`"] pub struct XTMODE_W<'a> { w: &'a mut W, } impl<'a> XTMODE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: XTMODE_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "No external trigger"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(XTMODE_A::VALUE1) } #[doc = "Trigger event upon a falling edge"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(XTMODE_A::VALUE2) } #[doc = "Trigger event upon a rising edge"] #[inline(always)] pub fn value3(self) -> &'a mut W { self.variant(XTMODE_A::VALUE3) } #[doc = "Trigger event upon any edge"] #[inline(always)] pub fn value4(self) -> &'a mut W { self.variant(XTMODE_A::VALUE4) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13); self.w } } #[doc = "Write Control for Trigger Configuration\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum XTWC_AW { #[doc = "0: No write access to trigger configuration"] VALUE1 = 0, #[doc = "1: Bitfields XTMODE and XTSEL can be written"] VALUE2 = 1, } impl From<XTWC_AW> for bool { #[inline(always)] fn from(variant: XTWC_AW) -> Self { variant as u8 != 0 } } #[doc = "Write proxy for field `XTWC`"] pub struct XTWC_W<'a> { w: &'a mut W, } impl<'a> XTWC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: XTWC_AW) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No write access to trigger configuration"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(XTWC_AW::VALUE1) } #[doc = "Bitfields XTMODE and XTSEL can be written"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(XTWC_AW::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `GTSEL`"] pub type GTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `GTSEL`"] pub struct GTSEL_W<'a> { w: &'a mut W, } impl<'a> GTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); self.w } } #[doc = "Reader of field `GTLVL`"] pub type GTLVL_R = crate::R<bool, bool>; #[doc = "Write Control for Gate Configuration\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum GTWC_AW { #[doc = "0: No write access to gate configuration"] VALUE1 = 0, #[doc = "1: Bitfield GTSEL can be written"] VALUE2 = 1, } impl From<GTWC_AW> for bool { #[inline(always)] fn from(variant: GTWC_AW) -> Self { variant as u8 != 0 } } #[doc = "Write proxy for field `GTWC`"] pub struct GTWC_W<'a> { w: &'a mut W, } impl<'a> GTWC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: GTWC_AW) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "No write access to gate configuration"] #[inline(always)] pub fn value1(self) -> &'a mut W { self.variant(GTWC_AW::VALUE1) } #[doc = "Bitfield GTSEL can be written"] #[inline(always)] pub fn value2(self) -> &'a mut W { self.variant(GTWC_AW::VALUE2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); self.w } } impl R { #[doc = "Bits 0:3 - Source-specific Result Register"] #[inline(always)] pub fn srcresreg(&self) -> SRCRESREG_R { SRCRESREG_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 8:11 - External Trigger Input Selection"] #[inline(always)] pub fn xtsel(&self) -> XTSEL_R { XTSEL_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bit 12 - External Trigger Level"] #[inline(always)] pub fn xtlvl(&self) -> XTLVL_R { XTLVL_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bits 13:14 - Trigger Operating Mode"] #[inline(always)] pub fn xtmode(&self) -> XTMODE_R { XTMODE_R::new(((self.bits >> 13) & 0x03) as u8) } #[doc = "Bits 16:19 - Gate Input Selection"] #[inline(always)] pub fn gtsel(&self) -> GTSEL_R { GTSEL_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bit 20 - Gate Input Level"] #[inline(always)] pub fn gtlvl(&self) -> GTLVL_R { GTLVL_R::new(((self.bits >> 20) & 0x01) != 0) } } impl W { #[doc = "Bits 0:3 - Source-specific Result Register"] #[inline(always)] pub fn srcresreg(&mut self) -> SRCRESREG_W { SRCRESREG_W { w: self } } #[doc = "Bits 8:11 - External Trigger Input Selection"] #[inline(always)] pub fn xtsel(&mut self) -> XTSEL_W { XTSEL_W { w: self } } #[doc = "Bits 13:14 - Trigger Operating Mode"] #[inline(always)] pub fn xtmode(&mut self) -> XTMODE_W { XTMODE_W { w: self } } #[doc = "Bit 15 - Write Control for Trigger Configuration"] #[inline(always)] pub fn xtwc(&mut self) -> XTWC_W { XTWC_W { w: self } } #[doc = "Bits 16:19 - Gate Input Selection"] #[inline(always)] pub fn gtsel(&mut self) -> GTSEL_W { GTSEL_W { w: self } } #[doc = "Bit 23 - Write Control for Gate Configuration"] #[inline(always)] pub fn gtwc(&mut self) -> GTWC_W { GTWC_W { w: self } } }