Type Alias xmc4300::usic0_ch0::pcr_sscmode::W

pub type W = W<PcrSscmodeSpec>;

Register PCR_SSCMode writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn mslsen(&mut self) -> MslsenW<'_, PcrSscmodeSpec>

Bit 0 - MSLS Enable

pub fn selctr(&mut self) -> SelctrW<'_, PcrSscmodeSpec>

Bit 1 - Select Control

pub fn selinv(&mut self) -> SelinvW<'_, PcrSscmodeSpec>

Bit 2 - Select Inversion

pub fn fem(&mut self) -> FemW<'_, PcrSscmodeSpec>

Bit 3 - Frame End Mode

pub fn ctqsel1(&mut self) -> Ctqsel1W<'_, PcrSscmodeSpec>

Bits 4:5 - Input Frequency Selection

pub fn pctq1(&mut self) -> Pctq1W<'_, PcrSscmodeSpec>

Bits 6:7 - Divider Factor PCTQ1 for Tiw and Tnf

pub fn dctq1(&mut self) -> Dctq1W<'_, PcrSscmodeSpec>

Bits 8:12 - Divider Factor DCTQ1 for Tiw and Tnf

pub fn parien(&mut self) -> ParienW<'_, PcrSscmodeSpec>

Bit 13 - Parity Error Interrupt Enable

pub fn mslsien(&mut self) -> MslsienW<'_, PcrSscmodeSpec>

Bit 14 - MSLS Interrupt Enable

pub fn dx2tien(&mut self) -> Dx2tienW<'_, PcrSscmodeSpec>

Bit 15 - DX2T Interrupt Enable

pub fn selo(&mut self) -> SeloW<'_, PcrSscmodeSpec>

Bits 16:23 - Select Output

pub fn tiwen(&mut self) -> TiwenW<'_, PcrSscmodeSpec>

Bit 24 - Enable Inter-Word Delay Tiw

pub fn slphsel(&mut self) -> SlphselW<'_, PcrSscmodeSpec>

Bit 25 - Slave Mode Clock Phase Select

pub fn mclk(&mut self) -> MclkW<'_, PcrSscmodeSpec>

Bit 31 - Master Clock Enable