Type Alias xmc4300::usic0_ch0::pcr_ascmode::W
source · pub type W = W<PcrAscmodeSpec>;
Expand description
Register PCR_ASCMode
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn smd(&mut self) -> SmdW<'_, PcrAscmodeSpec>
pub fn smd(&mut self) -> SmdW<'_, PcrAscmodeSpec>
Bit 0 - Sample Mode
sourcepub fn stpb(&mut self) -> StpbW<'_, PcrAscmodeSpec>
pub fn stpb(&mut self) -> StpbW<'_, PcrAscmodeSpec>
Bit 1 - Stop Bits
sourcepub fn idm(&mut self) -> IdmW<'_, PcrAscmodeSpec>
pub fn idm(&mut self) -> IdmW<'_, PcrAscmodeSpec>
Bit 2 - Idle Detection Mode
sourcepub fn sbien(&mut self) -> SbienW<'_, PcrAscmodeSpec>
pub fn sbien(&mut self) -> SbienW<'_, PcrAscmodeSpec>
Bit 3 - Synchronization Break Interrupt Enable
sourcepub fn cden(&mut self) -> CdenW<'_, PcrAscmodeSpec>
pub fn cden(&mut self) -> CdenW<'_, PcrAscmodeSpec>
Bit 4 - Collision Detection Enable
sourcepub fn rnien(&mut self) -> RnienW<'_, PcrAscmodeSpec>
pub fn rnien(&mut self) -> RnienW<'_, PcrAscmodeSpec>
Bit 5 - Receiver Noise Detection Interrupt Enable
sourcepub fn feien(&mut self) -> FeienW<'_, PcrAscmodeSpec>
pub fn feien(&mut self) -> FeienW<'_, PcrAscmodeSpec>
Bit 6 - Format Error Interrupt Enable
sourcepub fn ffien(&mut self) -> FfienW<'_, PcrAscmodeSpec>
pub fn ffien(&mut self) -> FfienW<'_, PcrAscmodeSpec>
Bit 7 - Frame Finished Interrupt Enable
sourcepub fn sp(&mut self) -> SpW<'_, PcrAscmodeSpec>
pub fn sp(&mut self) -> SpW<'_, PcrAscmodeSpec>
Bits 8:12 - Sample Point
sourcepub fn pl(&mut self) -> PlW<'_, PcrAscmodeSpec>
pub fn pl(&mut self) -> PlW<'_, PcrAscmodeSpec>
Bits 13:15 - Pulse Length
sourcepub fn rsten(&mut self) -> RstenW<'_, PcrAscmodeSpec>
pub fn rsten(&mut self) -> RstenW<'_, PcrAscmodeSpec>
Bit 16 - Receiver Status Enable
sourcepub fn tsten(&mut self) -> TstenW<'_, PcrAscmodeSpec>
pub fn tsten(&mut self) -> TstenW<'_, PcrAscmodeSpec>
Bit 17 - Transmitter Status Enable
sourcepub fn mclk(&mut self) -> MclkW<'_, PcrAscmodeSpec>
pub fn mclk(&mut self) -> MclkW<'_, PcrAscmodeSpec>
Bit 31 - Master Clock Enable