Type Alias xmc4200::usic0_ch0::brg::W

pub type W = W<BRG_SPEC>;

Register BRG writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn clksel(&mut self) -> CLKSEL_W<'_, BRG_SPEC>

Bits 0:1 - Clock Selection

pub fn tmen(&mut self) -> TMEN_W<'_, BRG_SPEC>

Bit 3 - Timing Measurement Enable

pub fn pppen(&mut self) -> PPPEN_W<'_, BRG_SPEC>

Bit 4 - Enable 2:1 Divider for fPPP

pub fn ctqsel(&mut self) -> CTQSEL_W<'_, BRG_SPEC>

Bits 6:7 - Input Selection for CTQ

pub fn pctq(&mut self) -> PCTQ_W<'_, BRG_SPEC>

Bits 8:9 - Pre-Divider for Time Quanta Counter

pub fn dctq(&mut self) -> DCTQ_W<'_, BRG_SPEC>

Bits 10:14 - Denominator for Time Quanta Counter

pub fn pdiv(&mut self) -> PDIV_W<'_, BRG_SPEC>

Bits 16:25 - Divider Mode: Divider Factor to Generate fPDIV

pub fn sclkosel(&mut self) -> SCLKOSEL_W<'_, BRG_SPEC>

Bit 28 - Shift Clock Output Select

pub fn mclkcfg(&mut self) -> MCLKCFG_W<'_, BRG_SPEC>

Bit 29 - Master Clock Configuration

pub fn sclkcfg(&mut self) -> SCLKCFG_W<'_, BRG_SPEC>

Bits 30:31 - Shift Clock Output Configuration