xmc4200/gpdma0_ch0/
cfgh.rs1#[doc = "Register `CFGH` reader"]
2pub type R = crate::R<CFGH_SPEC>;
3#[doc = "Register `CFGH` writer"]
4pub type W = crate::W<CFGH_SPEC>;
5#[doc = "Flow Control Mode\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum FCMODE_A {
8 #[doc = "0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled."]
9 VALUE1 = 0,
10 #[doc = "1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled."]
11 VALUE2 = 1,
12}
13impl From<FCMODE_A> for bool {
14 #[inline(always)]
15 fn from(variant: FCMODE_A) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `FCMODE` reader - Flow Control Mode"]
20pub type FCMODE_R = crate::BitReader<FCMODE_A>;
21impl FCMODE_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> FCMODE_A {
25 match self.bits {
26 false => FCMODE_A::VALUE1,
27 true => FCMODE_A::VALUE2,
28 }
29 }
30 #[doc = "Source transaction requests are serviced when they occur. Data pre-fetching is enabled."]
31 #[inline(always)]
32 pub fn is_value1(&self) -> bool {
33 *self == FCMODE_A::VALUE1
34 }
35 #[doc = "Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled."]
36 #[inline(always)]
37 pub fn is_value2(&self) -> bool {
38 *self == FCMODE_A::VALUE2
39 }
40}
41#[doc = "Field `FCMODE` writer - Flow Control Mode"]
42pub type FCMODE_W<'a, REG> = crate::BitWriter<'a, REG, FCMODE_A>;
43impl<'a, REG> FCMODE_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Source transaction requests are serviced when they occur. Data pre-fetching is enabled."]
48 #[inline(always)]
49 pub fn value1(self) -> &'a mut crate::W<REG> {
50 self.variant(FCMODE_A::VALUE1)
51 }
52 #[doc = "Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled."]
53 #[inline(always)]
54 pub fn value2(self) -> &'a mut crate::W<REG> {
55 self.variant(FCMODE_A::VALUE2)
56 }
57}
58#[doc = "FIFO Mode Select\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum FIFO_MODE_A {
61 #[doc = "0: Space/data available for single AHB transfer of the specified transfer width."]
62 VALUE1 = 0,
63 #[doc = "1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer."]
64 VALUE2 = 1,
65}
66impl From<FIFO_MODE_A> for bool {
67 #[inline(always)]
68 fn from(variant: FIFO_MODE_A) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `FIFO_MODE` reader - FIFO Mode Select"]
73pub type FIFO_MODE_R = crate::BitReader<FIFO_MODE_A>;
74impl FIFO_MODE_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> FIFO_MODE_A {
78 match self.bits {
79 false => FIFO_MODE_A::VALUE1,
80 true => FIFO_MODE_A::VALUE2,
81 }
82 }
83 #[doc = "Space/data available for single AHB transfer of the specified transfer width."]
84 #[inline(always)]
85 pub fn is_value1(&self) -> bool {
86 *self == FIFO_MODE_A::VALUE1
87 }
88 #[doc = "Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer."]
89 #[inline(always)]
90 pub fn is_value2(&self) -> bool {
91 *self == FIFO_MODE_A::VALUE2
92 }
93}
94#[doc = "Field `FIFO_MODE` writer - FIFO Mode Select"]
95pub type FIFO_MODE_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_MODE_A>;
96impl<'a, REG> FIFO_MODE_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Space/data available for single AHB transfer of the specified transfer width."]
101 #[inline(always)]
102 pub fn value1(self) -> &'a mut crate::W<REG> {
103 self.variant(FIFO_MODE_A::VALUE1)
104 }
105 #[doc = "Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer."]
106 #[inline(always)]
107 pub fn value2(self) -> &'a mut crate::W<REG> {
108 self.variant(FIFO_MODE_A::VALUE2)
109 }
110}
111#[doc = "Field `PROTCTL` reader - Protection Control"]
112pub type PROTCTL_R = crate::FieldReader;
113#[doc = "Field `PROTCTL` writer - Protection Control"]
114pub type PROTCTL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
115#[doc = "Field `DS_UPD_EN` reader - Destination Status Update Enable"]
116pub type DS_UPD_EN_R = crate::BitReader;
117#[doc = "Field `DS_UPD_EN` writer - Destination Status Update Enable"]
118pub type DS_UPD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `SS_UPD_EN` reader - Source Status Update Enable"]
120pub type SS_UPD_EN_R = crate::BitReader;
121#[doc = "Field `SS_UPD_EN` writer - Source Status Update Enable"]
122pub type SS_UPD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
123#[doc = "Field `SRC_PER` reader - Source Peripheral"]
124pub type SRC_PER_R = crate::FieldReader;
125#[doc = "Field `SRC_PER` writer - Source Peripheral"]
126pub type SRC_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
127#[doc = "Field `DEST_PER` reader - Destination Peripheral"]
128pub type DEST_PER_R = crate::FieldReader;
129#[doc = "Field `DEST_PER` writer - Destination Peripheral"]
130pub type DEST_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
131impl R {
132 #[doc = "Bit 0 - Flow Control Mode"]
133 #[inline(always)]
134 pub fn fcmode(&self) -> FCMODE_R {
135 FCMODE_R::new((self.bits & 1) != 0)
136 }
137 #[doc = "Bit 1 - FIFO Mode Select"]
138 #[inline(always)]
139 pub fn fifo_mode(&self) -> FIFO_MODE_R {
140 FIFO_MODE_R::new(((self.bits >> 1) & 1) != 0)
141 }
142 #[doc = "Bits 2:4 - Protection Control"]
143 #[inline(always)]
144 pub fn protctl(&self) -> PROTCTL_R {
145 PROTCTL_R::new(((self.bits >> 2) & 7) as u8)
146 }
147 #[doc = "Bit 5 - Destination Status Update Enable"]
148 #[inline(always)]
149 pub fn ds_upd_en(&self) -> DS_UPD_EN_R {
150 DS_UPD_EN_R::new(((self.bits >> 5) & 1) != 0)
151 }
152 #[doc = "Bit 6 - Source Status Update Enable"]
153 #[inline(always)]
154 pub fn ss_upd_en(&self) -> SS_UPD_EN_R {
155 SS_UPD_EN_R::new(((self.bits >> 6) & 1) != 0)
156 }
157 #[doc = "Bits 7:10 - Source Peripheral"]
158 #[inline(always)]
159 pub fn src_per(&self) -> SRC_PER_R {
160 SRC_PER_R::new(((self.bits >> 7) & 0x0f) as u8)
161 }
162 #[doc = "Bits 11:14 - Destination Peripheral"]
163 #[inline(always)]
164 pub fn dest_per(&self) -> DEST_PER_R {
165 DEST_PER_R::new(((self.bits >> 11) & 0x0f) as u8)
166 }
167}
168impl W {
169 #[doc = "Bit 0 - Flow Control Mode"]
170 #[inline(always)]
171 pub fn fcmode(&mut self) -> FCMODE_W<CFGH_SPEC> {
172 FCMODE_W::new(self, 0)
173 }
174 #[doc = "Bit 1 - FIFO Mode Select"]
175 #[inline(always)]
176 pub fn fifo_mode(&mut self) -> FIFO_MODE_W<CFGH_SPEC> {
177 FIFO_MODE_W::new(self, 1)
178 }
179 #[doc = "Bits 2:4 - Protection Control"]
180 #[inline(always)]
181 pub fn protctl(&mut self) -> PROTCTL_W<CFGH_SPEC> {
182 PROTCTL_W::new(self, 2)
183 }
184 #[doc = "Bit 5 - Destination Status Update Enable"]
185 #[inline(always)]
186 pub fn ds_upd_en(&mut self) -> DS_UPD_EN_W<CFGH_SPEC> {
187 DS_UPD_EN_W::new(self, 5)
188 }
189 #[doc = "Bit 6 - Source Status Update Enable"]
190 #[inline(always)]
191 pub fn ss_upd_en(&mut self) -> SS_UPD_EN_W<CFGH_SPEC> {
192 SS_UPD_EN_W::new(self, 6)
193 }
194 #[doc = "Bits 7:10 - Source Peripheral"]
195 #[inline(always)]
196 pub fn src_per(&mut self) -> SRC_PER_W<CFGH_SPEC> {
197 SRC_PER_W::new(self, 7)
198 }
199 #[doc = "Bits 11:14 - Destination Peripheral"]
200 #[inline(always)]
201 pub fn dest_per(&mut self) -> DEST_PER_W<CFGH_SPEC> {
202 DEST_PER_W::new(self, 11)
203 }
204}
205#[doc = "Configuration Register High\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
206pub struct CFGH_SPEC;
207impl crate::RegisterSpec for CFGH_SPEC {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [`cfgh::R`](R) reader structure"]
211impl crate::Readable for CFGH_SPEC {}
212#[doc = "`write(|w| ..)` method takes [`cfgh::W`](W) writer structure"]
213impl crate::Writable for CFGH_SPEC {
214 type Safety = crate::Unsafe;
215 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
216 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
217}
218#[doc = "`reset()` method sets CFGH to value 0x04"]
219impl crate::Resettable for CFGH_SPEC {
220 const RESET_VALUE: u32 = 0x04;
221}