Expand description
Baud Rate Generator Register
Structs§
- Baud Rate Generator Register
Enums§
- Clock Selection
- Input Selection for CTQ
- Master Clock Configuration
- Enable 2:1 Divider for fPPP
- Shift Clock Output Configuration
- Shift Clock Output Select
- Timing Measurement Enable
Type Aliases§
- Field
CLKSEL
reader - Clock Selection - Field
CLKSEL
writer - Clock Selection - Field
CTQSEL
reader - Input Selection for CTQ - Field
CTQSEL
writer - Input Selection for CTQ - Field
DCTQ
reader - Denominator for Time Quanta Counter - Field
DCTQ
writer - Denominator for Time Quanta Counter - Field
MCLKCFG
reader - Master Clock Configuration - Field
MCLKCFG
writer - Master Clock Configuration - Field
PCTQ
reader - Pre-Divider for Time Quanta Counter - Field
PCTQ
writer - Pre-Divider for Time Quanta Counter - Field
PDIV
reader - Divider Mode: Divider Factor to Generate fPDIV - Field
PDIV
writer - Divider Mode: Divider Factor to Generate fPDIV - Field
PPPEN
reader - Enable 2:1 Divider for fPPP - Field
PPPEN
writer - Enable 2:1 Divider for fPPP - Register
BRG
reader - Field
SCLKCFG
reader - Shift Clock Output Configuration - Field
SCLKCFG
writer - Shift Clock Output Configuration - Field
SCLKOSEL
reader - Shift Clock Output Select - Field
SCLKOSEL
writer - Shift Clock Output Select - Field
TMEN
reader - Timing Measurement Enable - Field
TMEN
writer - Timing Measurement Enable - Register
BRG
writer