[][src]Type Definition xmc4100::posif0::pconf::R

type R = R<u32, PCONF>;

Reader of register PCONF

Implementations

impl R[src]

pub fn fsel(&self) -> FSEL_R[src]

Bits 0:1 - Function Selector

pub fn qdcm(&self) -> QDCM_R[src]

Bit 2 - Position Decoder Mode selection

pub fn hidg(&self) -> HIDG_R[src]

Bit 4 - Idle generation enable

pub fn mcue(&self) -> MCUE_R[src]

Bit 5 - Multi-Channel Pattern SW update enable

pub fn insel0(&self) -> INSEL0_R[src]

Bits 8:9 - PhaseA/Hal input 1 selector

pub fn insel1(&self) -> INSEL1_R[src]

Bits 10:11 - PhaseB/Hall input 2 selector

pub fn insel2(&self) -> INSEL2_R[src]

Bits 12:13 - Index/Hall input 3 selector

pub fn dsel(&self) -> DSEL_R[src]

Bit 16 - Delay Pin selector

pub fn spes(&self) -> SPES_R[src]

Bit 17 - Edge selector for the sampling trigger

pub fn msets(&self) -> MSETS_R[src]

Bits 18:20 - Pattern update signal select

pub fn mses(&self) -> MSES_R[src]

Bit 21 - Multi-Channel pattern update trigger edge

pub fn msyns(&self) -> MSYNS_R[src]

Bits 22:23 - PWM synchronization signal selector

pub fn ewis(&self) -> EWIS_R[src]

Bits 24:25 - Wrong Hall Event selection

pub fn ewie(&self) -> EWIE_R[src]

Bit 26 - External Wrong Hall Event enable

pub fn ewil(&self) -> EWIL_R[src]

Bit 27 - External Wrong Hall Event active level

pub fn lpc(&self) -> LPC_R[src]

Bits 28:30 - Low Pass Filters Configuration