[−][src]Enum xmc1100::usic0_ch0::pcr_sscmode::SLPHSEL_A
Slave Mode Clock Phase Select
Value on reset: 0
Variants
0: Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
1: The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.
Trait Implementations
impl Clone for SLPHSEL_A
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fn clone(&self) -> SLPHSEL_A
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fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl Copy for SLPHSEL_A
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impl Debug for SLPHSEL_A
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impl From<SLPHSEL_A> for bool
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impl PartialEq<SLPHSEL_A> for SLPHSEL_A
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impl StructuralPartialEq for SLPHSEL_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,