Crate xed_sys2 Copy item path Source __BindgenBitfieldUnit __fsid_t xed_attributes_t xed_chip_features_t @ingroup ISASET xed_cpuid_rec_t xed_decoded_inst_s @ingroup DEC
The main container for instructions. After decode, it holds an array of
operands with derived information from decode and also valid
#xed_inst_t pointer which describes the operand templates and the
operand order. See @ref DEC for API documentation. xed_decoder_vars_s xed_enc_displacement_t xed_encoder_iforms_s xed_encoder_instruction_t xed_encoder_operand_t xed_encoder_operand_t__bindgen_ty_1__bindgen_ty_1 xed_encoder_prefixes_t__bindgen_ty_1 xed_encoder_vars_s xed_flag_enum_s @ingroup FLAGS
Associated with each flag field there can be one action. xed_flag_set_s__bindgen_ty_1 xed_format_options_t Options for the disasembly formatting functions. Set once during
initialization by a calling #xed_format_set_options
@ingroup PRINT xed_iform_info_s @ingroup IFORM
Statically available information about iforms.
Values are returned by #xed_iform_map(). xed_ild_vars_t__bindgen_ty_1 xed_inst_s @ingroup DEC
constant information about a decoded instruction form, including
the pointer to the constant operand properties #xed_operand_t for this
instruction form. xed_memop_t xed_operand_s @ingroup DEC
Constant information about an individual generic operand, like an
operand template, describing the operand properties. See @ref DEC for
API information. xed_operand_storage_s xed_print_info_t @ingroup PRINT
This contains the information used by the various disassembly printers.
Call xed_init_print_info to initialize the fields. Then change the
required and optional fields when required. xed_simple_flag_s @ingroup FLAGS
A collection of #xed_flag_action_t’s and unions of read and written flags xed_state_s Encapsulates machine modes for decoder/encoder requests.
It specifies the machine operating mode as a
#xed_machine_mode_enum_t
for decoding and encoding. The machine mode corresponds to the default
data operand width for that mode. For all modes other than the 64b long
mode (XED_MACHINE_MODE_LONG_64), a default addressing width, and a
stack addressing width must be supplied of type
#xed_address_width_enum_t . @ingroup INIT xed_union16_t__bindgen_ty_1 xed_union32_t__bindgen_ty_1 xed_union32_t__bindgen_ty_2 xed_union64_t__bindgen_ty_1 xed_union64_t__bindgen_ty_2 xed_union64_t__bindgen_ty_3 xed_address_width_enum_t xed_attribute_enum_t xed_category_enum_t xed_chip_enum_t xed_cpuid_group_enum_t xed_cpuid_rec_enum_t xed_encoder_operand_type_t xed_error_enum_t xed_exception_enum_t xed_extension_enum_t xed_flag_action_enum_t xed_flag_enum_t xed_iclass_enum_t xed_iform_enum_t xed_iformfl_enum_t xed_isa_set_enum_t xed_machine_mode_enum_t xed_nonterminal_enum_t xed_operand_action_enum_t xed_operand_convert_enum_t xed_operand_element_type_enum_t xed_operand_element_xtype_enum_t xed_operand_enum_t xed_operand_type_enum_t xed_operand_visibility_enum_t xed_operand_width_enum_t xed_reg_class_enum_t xed_reg_enum_t xed_syntax_enum_t INT8_MAX INT8_MIN INT16_MAX INT16_MIN INT32_MAX INT32_MIN INTPTR_MAX INTPTR_MIN INT_FAST8_MAX INT_FAST8_MIN INT_FAST16_MAX INT_FAST16_MIN INT_FAST32_MAX INT_FAST32_MIN INT_LEAST8_MAX INT_LEAST8_MIN INT_LEAST16_MAX INT_LEAST16_MIN INT_LEAST32_MAX INT_LEAST32_MIN PTRDIFF_MAX PTRDIFF_MIN SIG_ATOMIC_MAX SIG_ATOMIC_MIN SIZE_MAX UINT8_MAX UINT16_MAX UINT32_MAX UINTPTR_MAX UINT_FAST8_MAX UINT_FAST16_MAX UINT_FAST32_MAX UINT_LEAST8_MAX UINT_LEAST16_MAX UINT_LEAST32_MAX WINT_MAX WINT_MIN XED_64B XED_ADDRESS_WIDTH_16b_DEFINED XED_ADDRESS_WIDTH_32b_DEFINED XED_ADDRESS_WIDTH_64b_DEFINED XED_ADDRESS_WIDTH_INVALID_DEFINED XED_ADDRESS_WIDTH_LAST_DEFINED XED_ATTRIBUTE_AMDONLY_DEFINED XED_ATTRIBUTE_APX_NDD_DEFINED XED_ATTRIBUTE_APX_NF_DEFINED XED_ATTRIBUTE_ATOMIC_DEFINED XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION_DEFINED XED_ATTRIBUTE_BROADCAST_ENABLED_DEFINED XED_ATTRIBUTE_BYTEOP_DEFINED XED_ATTRIBUTE_DISP8_EIGHTHMEM_DEFINED XED_ATTRIBUTE_DISP8_FULLMEM_DEFINED XED_ATTRIBUTE_DISP8_FULL_DEFINED XED_ATTRIBUTE_DISP8_GPR_READER_BYTE_DEFINED XED_ATTRIBUTE_DISP8_GPR_READER_DEFINED XED_ATTRIBUTE_DISP8_GPR_READER_WORD_DEFINED XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D_DEFINED XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q_DEFINED XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE_DEFINED XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_DEFINED XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD_DEFINED XED_ATTRIBUTE_DISP8_GSCAT_DEFINED XED_ATTRIBUTE_DISP8_HALFMEM_DEFINED XED_ATTRIBUTE_DISP8_HALF_DEFINED XED_ATTRIBUTE_DISP8_MEM128_DEFINED XED_ATTRIBUTE_DISP8_MOVDDUP_DEFINED XED_ATTRIBUTE_DISP8_NO_SCALE_DEFINED XED_ATTRIBUTE_DISP8_QUARTERMEM_DEFINED XED_ATTRIBUTE_DISP8_QUARTER_DEFINED XED_ATTRIBUTE_DISP8_SCALAR_DEFINED XED_ATTRIBUTE_DISP8_TUPLE1_4X_DEFINED XED_ATTRIBUTE_DISP8_TUPLE1_BYTE_DEFINED XED_ATTRIBUTE_DISP8_TUPLE1_DEFINED XED_ATTRIBUTE_DISP8_TUPLE1_WORD_DEFINED XED_ATTRIBUTE_DISP8_TUPLE2_DEFINED XED_ATTRIBUTE_DISP8_TUPLE4_DEFINED XED_ATTRIBUTE_DISP8_TUPLE8_DEFINED XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP_DEFINED XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT_DEFINED XED_ATTRIBUTE_DWORD_INDICES_DEFINED XED_ATTRIBUTE_ELEMENT_SIZE_D_DEFINED XED_ATTRIBUTE_ELEMENT_SIZE_Q_DEFINED XED_ATTRIBUTE_EXCEPTION_BR_DEFINED XED_ATTRIBUTE_FAR_XFER_DEFINED XED_ATTRIBUTE_FIXED_BASE0_DEFINED XED_ATTRIBUTE_FIXED_BASE1_DEFINED XED_ATTRIBUTE_FIXED_ROUNDING_RNE_DEFINED XED_ATTRIBUTE_FLUSH_INPUT_DENORM_DEFINED XED_ATTRIBUTE_FLUSH_OUTPUT_DENORM_DEFINED XED_ATTRIBUTE_GATHER_DEFINED XED_ATTRIBUTE_HALF_WIDE_OUTPUT_DEFINED XED_ATTRIBUTE_HLE_ACQ_ABLE_DEFINED XED_ATTRIBUTE_HLE_REL_ABLE_DEFINED XED_ATTRIBUTE_IGNORES_OSFXSR_DEFINED XED_ATTRIBUTE_IMPLICIT_ONE_DEFINED XED_ATTRIBUTE_INDEX_REG_IS_POINTER_DEFINED XED_ATTRIBUTE_INDIRECT_BRANCH_DEFINED XED_ATTRIBUTE_INVALID_DEFINED XED_ATTRIBUTE_KMASK_DEFINED XED_ATTRIBUTE_LAST_DEFINED XED_ATTRIBUTE_LOCKABLE_DEFINED XED_ATTRIBUTE_LOCKED_DEFINED XED_ATTRIBUTE_MASKOP_DEFINED XED_ATTRIBUTE_MASKOP_EVEX_DEFINED XED_ATTRIBUTE_MASK_AS_CONTROL_DEFINED XED_ATTRIBUTE_MASK_VARIABLE_MEMOP_DEFINED XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION_DEFINED XED_ATTRIBUTE_MMX_EXCEPT_DEFINED XED_ATTRIBUTE_MPX_PREFIX_ABLE_DEFINED XED_ATTRIBUTE_MULTIDEST2_DEFINED XED_ATTRIBUTE_MULTISOURCE4_DEFINED XED_ATTRIBUTE_MXCSR_DEFINED XED_ATTRIBUTE_MXCSR_RD_DEFINED XED_ATTRIBUTE_NONTEMPORAL_DEFINED XED_ATTRIBUTE_NOP_DEFINED XED_ATTRIBUTE_NOTSX_COND_DEFINED XED_ATTRIBUTE_NOTSX_DEFINED XED_ATTRIBUTE_NO_RIP_REL_DEFINED XED_ATTRIBUTE_NO_SRC_DEST_MATCH_DEFINED XED_ATTRIBUTE_PREFETCH_DEFINED XED_ATTRIBUTE_PROTECTED_MODE_DEFINED XED_ATTRIBUTE_QWORD_INDICES_DEFINED XED_ATTRIBUTE_REP_DEFINED XED_ATTRIBUTE_REQUIRES_ALIGNMENT_4B_DEFINED XED_ATTRIBUTE_REQUIRES_ALIGNMENT_8B_DEFINED XED_ATTRIBUTE_REQUIRES_ALIGNMENT_DEFINED XED_ATTRIBUTE_RING0_DEFINED XED_ATTRIBUTE_SCALABLE_DEFINED XED_ATTRIBUTE_SCATTER_DEFINED XED_ATTRIBUTE_SIMD_SCALAR_DEFINED XED_ATTRIBUTE_SKIPLOW32_DEFINED XED_ATTRIBUTE_SKIPLOW64_DEFINED XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED_DEFINED XED_ATTRIBUTE_STACKPOP0_DEFINED XED_ATTRIBUTE_STACKPOP1_DEFINED XED_ATTRIBUTE_STACKPUSH0_DEFINED XED_ATTRIBUTE_STACKPUSH1_DEFINED XED_ATTRIBUTE_UNDOCUMENTED_DEFINED XED_ATTRIBUTE_USES_DAZ_DEFINED XED_ATTRIBUTE_USES_FTZ_DEFINED XED_ATTRIBUTE_X87_CONTROL_DEFINED XED_ATTRIBUTE_X87_MMX_STATE_CW_DEFINED XED_ATTRIBUTE_X87_MMX_STATE_R_DEFINED XED_ATTRIBUTE_X87_MMX_STATE_W_DEFINED XED_ATTRIBUTE_X87_NOWAIT_DEFINED XED_ATTRIBUTE_XMM_STATE_CW_DEFINED XED_ATTRIBUTE_XMM_STATE_R_DEFINED XED_ATTRIBUTE_XMM_STATE_W_DEFINED XED_CATEGORY_3DNOW_DEFINED XED_CATEGORY_ADOX_ADCX_DEFINED XED_CATEGORY_AES_DEFINED XED_CATEGORY_AMX_TILE_DEFINED XED_CATEGORY_APX_DEFINED XED_CATEGORY_AVX2GATHER_DEFINED XED_CATEGORY_AVX2_DEFINED XED_CATEGORY_AVX512_4FMAPS_DEFINED XED_CATEGORY_AVX512_4VNNIW_DEFINED XED_CATEGORY_AVX512_BITALG_DEFINED XED_CATEGORY_AVX512_DEFINED XED_CATEGORY_AVX512_VBMI_DEFINED XED_CATEGORY_AVX512_VP2INTERSECT_DEFINED XED_CATEGORY_AVX_DEFINED XED_CATEGORY_AVX_IFMA_DEFINED XED_CATEGORY_BINARY_DEFINED XED_CATEGORY_BITBYTE_DEFINED XED_CATEGORY_BLEND_DEFINED XED_CATEGORY_BMI1_DEFINED XED_CATEGORY_BMI2_DEFINED XED_CATEGORY_BROADCAST_DEFINED XED_CATEGORY_CALL_DEFINED XED_CATEGORY_CET_DEFINED XED_CATEGORY_CLDEMOTE_DEFINED XED_CATEGORY_CLFLUSHOPT_DEFINED XED_CATEGORY_CLWB_DEFINED XED_CATEGORY_CLZERO_DEFINED XED_CATEGORY_CMOV_DEFINED XED_CATEGORY_COMPRESS_DEFINED XED_CATEGORY_COND_BR_DEFINED XED_CATEGORY_CONFLICT_DEFINED XED_CATEGORY_CONVERT_DEFINED XED_CATEGORY_DATAXFER_DEFINED XED_CATEGORY_DECIMAL_DEFINED XED_CATEGORY_ENQCMD_DEFINED XED_CATEGORY_EXPAND_DEFINED XED_CATEGORY_FCMOV_DEFINED XED_CATEGORY_FLAGOP_DEFINED XED_CATEGORY_FMA4_DEFINED XED_CATEGORY_FP16_DEFINED XED_CATEGORY_FRED_DEFINED XED_CATEGORY_GATHER_DEFINED XED_CATEGORY_GFNI_DEFINED XED_CATEGORY_HRESET_DEFINED XED_CATEGORY_IFMA_DEFINED XED_CATEGORY_INTERRUPT_DEFINED XED_CATEGORY_INVALID_DEFINED XED_CATEGORY_IOSTRINGOP_DEFINED XED_CATEGORY_IO_DEFINED XED_CATEGORY_KEYLOCKER_DEFINED XED_CATEGORY_KEYLOCKER_WIDE_DEFINED XED_CATEGORY_KMASK_DEFINED XED_CATEGORY_LAST_DEFINED XED_CATEGORY_LEGACY_DEFINED XED_CATEGORY_LKGS_DEFINED XED_CATEGORY_LOGICAL_DEFINED XED_CATEGORY_LOGICAL_FP_DEFINED XED_CATEGORY_LZCNT_DEFINED XED_CATEGORY_MISC_DEFINED XED_CATEGORY_MMX_DEFINED XED_CATEGORY_MOVDIR_DEFINED XED_CATEGORY_MPX_DEFINED XED_CATEGORY_MSRLIST_DEFINED XED_CATEGORY_NOP_DEFINED XED_CATEGORY_PBNDKB_DEFINED XED_CATEGORY_PCLMULQDQ_DEFINED XED_CATEGORY_PCONFIG_DEFINED XED_CATEGORY_PKU_DEFINED XED_CATEGORY_POP_DEFINED XED_CATEGORY_PREFETCHWT1_DEFINED XED_CATEGORY_PREFETCH_DEFINED XED_CATEGORY_PTWRITE_DEFINED XED_CATEGORY_PUSH_DEFINED XED_CATEGORY_RDPID_DEFINED XED_CATEGORY_RDPRU_DEFINED XED_CATEGORY_RDRAND_DEFINED XED_CATEGORY_RDSEED_DEFINED XED_CATEGORY_RDWRFSGS_DEFINED XED_CATEGORY_RET_DEFINED XED_CATEGORY_ROTATE_DEFINED XED_CATEGORY_SCATTER_DEFINED XED_CATEGORY_SEGOP_DEFINED XED_CATEGORY_SEMAPHORE_DEFINED XED_CATEGORY_SERIALIZE_DEFINED XED_CATEGORY_SETCC_DEFINED XED_CATEGORY_SGX_DEFINED XED_CATEGORY_SHA512_DEFINED XED_CATEGORY_SHA_DEFINED XED_CATEGORY_SHIFT_DEFINED XED_CATEGORY_SMAP_DEFINED XED_CATEGORY_SSE_DEFINED XED_CATEGORY_STRINGOP_DEFINED XED_CATEGORY_STTNI_DEFINED XED_CATEGORY_SYSCALL_DEFINED XED_CATEGORY_SYSRET_DEFINED XED_CATEGORY_SYSTEM_DEFINED XED_CATEGORY_TBM_DEFINED XED_CATEGORY_TSX_LDTRK_DEFINED XED_CATEGORY_UINTR_DEFINED XED_CATEGORY_UNCOND_BR_DEFINED XED_CATEGORY_USER_MSR_DEFINED XED_CATEGORY_VAES_DEFINED XED_CATEGORY_VBMI2_DEFINED XED_CATEGORY_VEX_DEFINED XED_CATEGORY_VFMA_DEFINED XED_CATEGORY_VIA_PADLOCK_DEFINED XED_CATEGORY_VPCLMULQDQ_DEFINED XED_CATEGORY_VTX_DEFINED XED_CATEGORY_WAITPKG_DEFINED XED_CATEGORY_WIDENOP_DEFINED XED_CATEGORY_WRMSRNS_DEFINED XED_CATEGORY_X87_ALU_DEFINED XED_CATEGORY_XOP_DEFINED XED_CATEGORY_XSAVEOPT_DEFINED XED_CATEGORY_XSAVE_DEFINED XED_CHIP_ALDER_LAKE_DEFINED XED_CHIP_ALLREAL_DEFINED XED_CHIP_ALL_DEFINED XED_CHIP_AMD_BULLDOZER_DEFINED XED_CHIP_AMD_FUTURE_DEFINED XED_CHIP_AMD_K10_DEFINED XED_CHIP_AMD_PILEDRIVER_DEFINED XED_CHIP_AMD_ZEN2_DEFINED XED_CHIP_AMD_ZENPLUS_DEFINED XED_CHIP_AMD_ZEN_DEFINED XED_CHIP_ARROW_LAKE_DEFINED XED_CHIP_BONNELL_DEFINED XED_CHIP_BROADWELL_DEFINED XED_CHIP_CANNONLAKE_DEFINED XED_CHIP_CASCADE_LAKE_DEFINED XED_CHIP_CLEARWATER_FOREST_DEFINED XED_CHIP_COMET_LAKE_DEFINED XED_CHIP_COOPER_LAKE_DEFINED XED_CHIP_EMERALD_RAPIDS_DEFINED XED_CHIP_FUTURE_DEFINED XED_CHIP_GOLDMONT_DEFINED XED_CHIP_GOLDMONT_PLUS_DEFINED XED_CHIP_GRANITE_RAPIDS_DEFINED XED_CHIP_HASWELL_DEFINED XED_CHIP_I86FP_DEFINED XED_CHIP_I86_DEFINED XED_CHIP_I186FP_DEFINED XED_CHIP_I186_DEFINED XED_CHIP_I286REAL_DEFINED XED_CHIP_I286_DEFINED XED_CHIP_I386FP_DEFINED XED_CHIP_I386REAL_DEFINED XED_CHIP_I386_DEFINED XED_CHIP_I486REAL_DEFINED XED_CHIP_I486_DEFINED XED_CHIP_I2186FP_DEFINED XED_CHIP_ICE_LAKE_DEFINED XED_CHIP_ICE_LAKE_SERVER_DEFINED XED_CHIP_INVALID_DEFINED XED_CHIP_IVYBRIDGE_DEFINED XED_CHIP_KNL_DEFINED XED_CHIP_KNM_DEFINED XED_CHIP_LAKEFIELD_DEFINED XED_CHIP_LAST_DEFINED XED_CHIP_LUNAR_LAKE_DEFINED XED_CHIP_MEROM_DEFINED XED_CHIP_NEHALEM_DEFINED XED_CHIP_P4PRESCOTT_DEFINED XED_CHIP_P4PRESCOTT_NOLAHF_DEFINED XED_CHIP_P4PRESCOTT_VTX_DEFINED XED_CHIP_PANTHER_LAKE_DEFINED XED_CHIP_PENRYN_DEFINED XED_CHIP_PENRYN_E_DEFINED XED_CHIP_PENTIUM2_DEFINED XED_CHIP_PENTIUM3_DEFINED XED_CHIP_PENTIUM4_DEFINED XED_CHIP_PENTIUMMMXREAL_DEFINED XED_CHIP_PENTIUMMMX_DEFINED XED_CHIP_PENTIUMPRO_DEFINED XED_CHIP_PENTIUMREAL_DEFINED XED_CHIP_PENTIUM_DEFINED XED_CHIP_QUARK_DEFINED XED_CHIP_SALTWELL_DEFINED XED_CHIP_SANDYBRIDGE_DEFINED XED_CHIP_SAPPHIRE_RAPIDS_DEFINED XED_CHIP_SIERRA_FOREST_DEFINED XED_CHIP_SILVERMONT_DEFINED XED_CHIP_SKYLAKE_DEFINED XED_CHIP_SKYLAKE_SERVER_DEFINED XED_CHIP_SNOW_RIDGE_DEFINED XED_CHIP_TIGER_LAKE_DEFINED XED_CHIP_TREMONT_DEFINED XED_CHIP_VIA_DEFINED XED_CHIP_WESTMERE_DEFINED XED_CPUID_GROUP_ADOX_ADCX_DEFINED XED_CPUID_GROUP_AES_DEFINED XED_CPUID_GROUP_AMX_BF16_DEFINED XED_CPUID_GROUP_AMX_COMPLEX_DEFINED XED_CPUID_GROUP_AMX_FP16_DEFINED XED_CPUID_GROUP_AMX_INT8_DEFINED XED_CPUID_GROUP_AMX_TILE_DEFINED XED_CPUID_GROUP_APX_F_AMX_DEFINED XED_CPUID_GROUP_APX_F_DEFINED XED_CPUID_GROUP_APX_F_KOPB_DEFINED XED_CPUID_GROUP_APX_F_KOPD_DEFINED XED_CPUID_GROUP_APX_F_KOPQ_DEFINED XED_CPUID_GROUP_APX_F_KOPW_DEFINED XED_CPUID_GROUP_AVX2GATHER_DEFINED XED_CPUID_GROUP_AVX2_DEFINED XED_CPUID_GROUP_AVX512BW_128N_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_128N_DEFINED XED_CPUID_GROUP_AVX512BW_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_128_DEFINED XED_CPUID_GROUP_AVX512BW_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_256_DEFINED XED_CPUID_GROUP_AVX512BW_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_512_DEFINED XED_CPUID_GROUP_AVX512BW_KOPD_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_KOPD_DEFINED XED_CPUID_GROUP_AVX512BW_KOPQ_AVX10_DEFINED XED_CPUID_GROUP_AVX512BW_KOPQ_DEFINED XED_CPUID_GROUP_AVX512CD_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512CD_128_DEFINED XED_CPUID_GROUP_AVX512CD_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512CD_256_DEFINED XED_CPUID_GROUP_AVX512CD_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512CD_512_DEFINED XED_CPUID_GROUP_AVX512DQ_128N_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_128N_DEFINED XED_CPUID_GROUP_AVX512DQ_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_128_DEFINED XED_CPUID_GROUP_AVX512DQ_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_256_DEFINED XED_CPUID_GROUP_AVX512DQ_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_512_DEFINED XED_CPUID_GROUP_AVX512DQ_KOPB_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_KOPB_DEFINED XED_CPUID_GROUP_AVX512DQ_KOPW_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_KOPW_DEFINED XED_CPUID_GROUP_AVX512DQ_SCALAR_AVX10_DEFINED XED_CPUID_GROUP_AVX512DQ_SCALAR_DEFINED XED_CPUID_GROUP_AVX512ER_512_DEFINED XED_CPUID_GROUP_AVX512ER_SCALAR_DEFINED XED_CPUID_GROUP_AVX512F_128N_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_128N_DEFINED XED_CPUID_GROUP_AVX512F_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_128_DEFINED XED_CPUID_GROUP_AVX512F_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_256_DEFINED XED_CPUID_GROUP_AVX512F_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_512_DEFINED XED_CPUID_GROUP_AVX512F_KOPW_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_KOPW_DEFINED XED_CPUID_GROUP_AVX512F_SCALAR_AVX10_DEFINED XED_CPUID_GROUP_AVX512F_SCALAR_DEFINED XED_CPUID_GROUP_AVX512PF_512_DEFINED XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR_DEFINED XED_CPUID_GROUP_AVX512_4VNNIW_512_DEFINED XED_CPUID_GROUP_AVX512_BF16_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BF16_128_DEFINED XED_CPUID_GROUP_AVX512_BF16_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BF16_256_DEFINED XED_CPUID_GROUP_AVX512_BF16_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BF16_512_DEFINED XED_CPUID_GROUP_AVX512_BITALG_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BITALG_128_DEFINED XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED XED_CPUID_GROUP_AVX512_FP16_128N_DEFINED XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_FP16_128_DEFINED XED_CPUID_GROUP_AVX512_FP16_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_FP16_256_DEFINED XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_FP16_512_DEFINED XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED XED_CPUID_GROUP_AVX512_GFNI_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_GFNI_128_DEFINED XED_CPUID_GROUP_AVX512_GFNI_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_GFNI_256_DEFINED XED_CPUID_GROUP_AVX512_GFNI_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_GFNI_512_DEFINED XED_CPUID_GROUP_AVX512_IFMA_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_IFMA_128_DEFINED XED_CPUID_GROUP_AVX512_IFMA_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_IFMA_256_DEFINED XED_CPUID_GROUP_AVX512_IFMA_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED XED_CPUID_GROUP_AVX512_VAES_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VAES_128_DEFINED XED_CPUID_GROUP_AVX512_VAES_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VAES_256_DEFINED XED_CPUID_GROUP_AVX512_VAES_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VAES_512_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_128_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_256_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI2_512_DEFINED XED_CPUID_GROUP_AVX512_VBMI_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI_128_DEFINED XED_CPUID_GROUP_AVX512_VBMI_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI_256_DEFINED XED_CPUID_GROUP_AVX512_VBMI_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VBMI_512_DEFINED XED_CPUID_GROUP_AVX512_VNNI_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VNNI_128_DEFINED XED_CPUID_GROUP_AVX512_VNNI_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VNNI_256_DEFINED XED_CPUID_GROUP_AVX512_VNNI_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VNNI_512_DEFINED XED_CPUID_GROUP_AVX512_VP2INTERSECT_128_DEFINED XED_CPUID_GROUP_AVX512_VP2INTERSECT_256_DEFINED XED_CPUID_GROUP_AVX512_VP2INTERSECT_512_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_128_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_256_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPCLMULQDQ_512_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_128_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_128_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_256_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_256_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_512_AVX10_DEFINED XED_CPUID_GROUP_AVX512_VPOPCNTDQ_512_DEFINED XED_CPUID_GROUP_AVXAES_DEFINED XED_CPUID_GROUP_AVX_DEFINED XED_CPUID_GROUP_AVX_GFNI_DEFINED XED_CPUID_GROUP_AVX_IFMA_DEFINED XED_CPUID_GROUP_AVX_NE_CONVERT_DEFINED XED_CPUID_GROUP_AVX_VNNI_DEFINED XED_CPUID_GROUP_AVX_VNNI_INT8_DEFINED XED_CPUID_GROUP_AVX_VNNI_INT16_DEFINED XED_CPUID_GROUP_BMI1_DEFINED XED_CPUID_GROUP_BMI2_DEFINED XED_CPUID_GROUP_CET_DEFINED XED_CPUID_GROUP_CLDEMOTE_DEFINED XED_CPUID_GROUP_CLFLUSHOPT_DEFINED XED_CPUID_GROUP_CLFSH_DEFINED XED_CPUID_GROUP_CLWB_DEFINED XED_CPUID_GROUP_CMOV_DEFINED XED_CPUID_GROUP_CMPCCXADD_DEFINED XED_CPUID_GROUP_CMPXCHG16B_DEFINED XED_CPUID_GROUP_ENQCMD_DEFINED XED_CPUID_GROUP_F16C_DEFINED XED_CPUID_GROUP_FCMOV_DEFINED XED_CPUID_GROUP_FCOMI_DEFINED XED_CPUID_GROUP_FMA_DEFINED XED_CPUID_GROUP_FRED_DEFINED XED_CPUID_GROUP_FXSAVE64_DEFINED XED_CPUID_GROUP_FXSAVE_DEFINED XED_CPUID_GROUP_GFNI_DEFINED XED_CPUID_GROUP_HRESET_DEFINED XED_CPUID_GROUP_ICACHE_PREFETCH_DEFINED XED_CPUID_GROUP_INVALID_DEFINED XED_CPUID_GROUP_INVPCID_DEFINED XED_CPUID_GROUP_KEYLOCKER_DEFINED XED_CPUID_GROUP_KEYLOCKER_WIDE_DEFINED XED_CPUID_GROUP_LAHF_DEFINED XED_CPUID_GROUP_LAST_DEFINED XED_CPUID_GROUP_LKGS_DEFINED XED_CPUID_GROUP_LONGMODE_DEFINED XED_CPUID_GROUP_LZCNT_DEFINED XED_CPUID_GROUP_MCOMMIT_DEFINED XED_CPUID_GROUP_MONITORX_DEFINED XED_CPUID_GROUP_MONITOR_DEFINED XED_CPUID_GROUP_MOVBE_DEFINED XED_CPUID_GROUP_MOVDIR_DEFINED XED_CPUID_GROUP_MPX_DEFINED XED_CPUID_GROUP_MSRLIST_DEFINED XED_CPUID_GROUP_PBNDKB_DEFINED XED_CPUID_GROUP_PCLMULQDQ_DEFINED XED_CPUID_GROUP_PCONFIG_DEFINED XED_CPUID_GROUP_PENTIUMMMX_DEFINED XED_CPUID_GROUP_PKU_DEFINED XED_CPUID_GROUP_POPCNT_DEFINED XED_CPUID_GROUP_PREFETCHWT1_DEFINED XED_CPUID_GROUP_PREFETCHW_DEFINED XED_CPUID_GROUP_PTWRITE_DEFINED XED_CPUID_GROUP_RAO_INT_DEFINED XED_CPUID_GROUP_RDPID_DEFINED XED_CPUID_GROUP_RDPRU_DEFINED XED_CPUID_GROUP_RDRAND_DEFINED XED_CPUID_GROUP_RDSEED_DEFINED XED_CPUID_GROUP_RDTSCP_DEFINED XED_CPUID_GROUP_RDWRFSGS_DEFINED XED_CPUID_GROUP_RTM_DEFINED XED_CPUID_GROUP_SERIALIZE_DEFINED XED_CPUID_GROUP_SGX_DEFINED XED_CPUID_GROUP_SHA512_DEFINED XED_CPUID_GROUP_SHA_DEFINED XED_CPUID_GROUP_SM3_DEFINED XED_CPUID_GROUP_SM4_DEFINED XED_CPUID_GROUP_SMAP_DEFINED XED_CPUID_GROUP_SMX_DEFINED XED_CPUID_GROUP_SNP_DEFINED XED_CPUID_GROUP_SSE2MMX_DEFINED XED_CPUID_GROUP_SSE2_DEFINED XED_CPUID_GROUP_SSE3X87_DEFINED XED_CPUID_GROUP_SSE3_DEFINED XED_CPUID_GROUP_SSE4A_DEFINED XED_CPUID_GROUP_SSE4_DEFINED XED_CPUID_GROUP_SSE42_DEFINED XED_CPUID_GROUP_SSEMXCSR_DEFINED XED_CPUID_GROUP_SSE_DEFINED XED_CPUID_GROUP_SSSE3MMX_DEFINED XED_CPUID_GROUP_SSSE3_DEFINED XED_CPUID_GROUP_TSX_LDTRK_DEFINED XED_CPUID_GROUP_UINTR_DEFINED XED_CPUID_GROUP_USER_MSR_DEFINED XED_CPUID_GROUP_VAES_DEFINED XED_CPUID_GROUP_VIA_PADLOCK_AES_DEFINED XED_CPUID_GROUP_VIA_PADLOCK_MONTMUL_DEFINED XED_CPUID_GROUP_VIA_PADLOCK_RNG_DEFINED XED_CPUID_GROUP_VIA_PADLOCK_SHA_DEFINED XED_CPUID_GROUP_VPCLMULQDQ_DEFINED XED_CPUID_GROUP_VTX_DEFINED XED_CPUID_GROUP_WAITPKG_DEFINED XED_CPUID_GROUP_WBNOINVD_DEFINED XED_CPUID_GROUP_WRMSRNS_DEFINED XED_CPUID_GROUP_XSAVEC_DEFINED XED_CPUID_GROUP_XSAVEOPT_DEFINED XED_CPUID_GROUP_XSAVES_DEFINED XED_CPUID_GROUP_XSAVE_DEFINED XED_CPUID_REC_ADOXADCX_DEFINED XED_CPUID_REC_AES_DEFINED XED_CPUID_REC_AMX_BF16_DEFINED XED_CPUID_REC_AMX_COMPLEX_DEFINED XED_CPUID_REC_AMX_FP16_DEFINED XED_CPUID_REC_AMX_INT8_DEFINED XED_CPUID_REC_AMX_TILES_DEFINED XED_CPUID_REC_APX_F_DEFINED XED_CPUID_REC_AVX2_DEFINED XED_CPUID_REC_AVX10_128VL_DEFINED XED_CPUID_REC_AVX10_256VL_DEFINED XED_CPUID_REC_AVX10_512VL_DEFINED XED_CPUID_REC_AVX10_ENABLED_DEFINED XED_CPUID_REC_AVX10_VER1_DEFINED XED_CPUID_REC_AVX512BW_DEFINED XED_CPUID_REC_AVX512CD_DEFINED XED_CPUID_REC_AVX512DQ_DEFINED XED_CPUID_REC_AVX512ER_DEFINED XED_CPUID_REC_AVX512F_DEFINED XED_CPUID_REC_AVX512IFMA_DEFINED XED_CPUID_REC_AVX512PF_DEFINED XED_CPUID_REC_AVX512VBMI_DEFINED XED_CPUID_REC_AVX512VL_DEFINED XED_CPUID_REC_AVX512_4FMAPS_DEFINED XED_CPUID_REC_AVX512_4VNNIW_DEFINED XED_CPUID_REC_AVX512_BITALG_DEFINED XED_CPUID_REC_AVX512_FP16_DEFINED XED_CPUID_REC_AVX512_VBMI2_DEFINED XED_CPUID_REC_AVX512_VNNI_DEFINED XED_CPUID_REC_AVX512_VP2INTERSECT_DEFINED XED_CPUID_REC_AVX512_VPOPCNTDQ_DEFINED XED_CPUID_REC_AVX_DEFINED XED_CPUID_REC_AVX_IFMA_DEFINED XED_CPUID_REC_AVX_NE_CONVERT_DEFINED XED_CPUID_REC_AVX_VNNI_DEFINED XED_CPUID_REC_AVX_VNNI_INT8_DEFINED XED_CPUID_REC_AVX_VNNI_INT16_DEFINED XED_CPUID_REC_BF16_DEFINED XED_CPUID_REC_BMI1_DEFINED XED_CPUID_REC_BMI2_DEFINED XED_CPUID_REC_CET_DEFINED XED_CPUID_REC_CLDEMOTE_DEFINED XED_CPUID_REC_CLFLUSHOPT_DEFINED XED_CPUID_REC_CLFLUSH_DEFINED XED_CPUID_REC_CLWB_DEFINED XED_CPUID_REC_CMOV_DEFINED XED_CPUID_REC_CMPCCXADD_DEFINED XED_CPUID_REC_CMPXCHG16B_DEFINED XED_CPUID_REC_ENQCMD_DEFINED XED_CPUID_REC_F16C_DEFINED XED_CPUID_REC_FMA_DEFINED XED_CPUID_REC_FPU_DEFINED XED_CPUID_REC_FRED_DEFINED XED_CPUID_REC_FXSAVE_DEFINED XED_CPUID_REC_GFNI_DEFINED XED_CPUID_REC_HRESET_DEFINED XED_CPUID_REC_ICACHE_PREFETCH_DEFINED XED_CPUID_REC_INTEL64_DEFINED XED_CPUID_REC_INTELPT_DEFINED XED_CPUID_REC_INVALID_DEFINED XED_CPUID_REC_INVPCID_DEFINED XED_CPUID_REC_KLENABLED_DEFINED XED_CPUID_REC_KLSUPPORTED_DEFINED XED_CPUID_REC_KLWIDE_DEFINED XED_CPUID_REC_LAHF_DEFINED XED_CPUID_REC_LAST_DEFINED XED_CPUID_REC_LKGS_DEFINED XED_CPUID_REC_LZCNT_DEFINED XED_CPUID_REC_MCOMMIT_DEFINED XED_CPUID_REC_MMX_DEFINED XED_CPUID_REC_MONITORX_DEFINED XED_CPUID_REC_MONITOR_DEFINED XED_CPUID_REC_MOVDIR64B_DEFINED XED_CPUID_REC_MOVDIRI_DEFINED XED_CPUID_REC_MOVEBE_DEFINED XED_CPUID_REC_MPX_DEFINED XED_CPUID_REC_MSRLIST_DEFINED XED_CPUID_REC_OSPKU_DEFINED XED_CPUID_REC_OSXSAVE_DEFINED XED_CPUID_REC_PBNDKB_DEFINED XED_CPUID_REC_PCLMULQDQ_DEFINED XED_CPUID_REC_PCONFIG_DEFINED XED_CPUID_REC_PKU_DEFINED XED_CPUID_REC_POPCNT_DEFINED XED_CPUID_REC_PREFETCHWT1_DEFINED XED_CPUID_REC_PREFETCHW_DEFINED XED_CPUID_REC_PTWRITE_DEFINED XED_CPUID_REC_RAO_INT_DEFINED XED_CPUID_REC_RDPRU_DEFINED XED_CPUID_REC_RDP_DEFINED XED_CPUID_REC_RDRAND_DEFINED XED_CPUID_REC_RDSEED_DEFINED XED_CPUID_REC_RDTSCP_DEFINED XED_CPUID_REC_RDWRFSGS_DEFINED XED_CPUID_REC_RTM_DEFINED XED_CPUID_REC_SERIALIZE_DEFINED XED_CPUID_REC_SGX_DEFINED XED_CPUID_REC_SHA512_DEFINED XED_CPUID_REC_SHA_DEFINED XED_CPUID_REC_SM3_DEFINED XED_CPUID_REC_SM4_DEFINED XED_CPUID_REC_SMAP_DEFINED XED_CPUID_REC_SMX_DEFINED XED_CPUID_REC_SNP_DEFINED XED_CPUID_REC_SSE2_DEFINED XED_CPUID_REC_SSE3_DEFINED XED_CPUID_REC_SSE4A_DEFINED XED_CPUID_REC_SSE4_DEFINED XED_CPUID_REC_SSE42_DEFINED XED_CPUID_REC_SSE_DEFINED XED_CPUID_REC_SSSE3_DEFINED XED_CPUID_REC_TSX_LDTRK_DEFINED XED_CPUID_REC_UINTR_DEFINED XED_CPUID_REC_USER_MSR_DEFINED XED_CPUID_REC_VAES_DEFINED XED_CPUID_REC_VIA_PADLOCK_AES_DEFINED XED_CPUID_REC_VIA_PADLOCK_AES_EN_DEFINED XED_CPUID_REC_VIA_PADLOCK_PMM_DEFINED XED_CPUID_REC_VIA_PADLOCK_PMM_EN_DEFINED XED_CPUID_REC_VIA_PADLOCK_RNG_DEFINED XED_CPUID_REC_VIA_PADLOCK_RNG_EN_DEFINED XED_CPUID_REC_VIA_PADLOCK_SHA_DEFINED XED_CPUID_REC_VIA_PADLOCK_SHA_EN_DEFINED XED_CPUID_REC_VMX_DEFINED XED_CPUID_REC_VPCLMULQDQ_DEFINED XED_CPUID_REC_WAITPKG_DEFINED XED_CPUID_REC_WBNOINVD_DEFINED XED_CPUID_REC_WRMSRNS_DEFINED XED_CPUID_REC_XSAVEC_DEFINED XED_CPUID_REC_XSAVEOPT_DEFINED XED_CPUID_REC_XSAVES_DEFINED XED_CPUID_REC_XSAVE_DEFINED XED_EMIT_MESSAGES XED_ENCODER_OPERANDS_MAX XED_ENCODE_FB_VALUES_TABLE_SIZE XED_ENCODE_MAX_EMIT_PATTERNS XED_ENCODE_MAX_FB_PATTERNS XED_ENCODE_MAX_IFORMS XED_ENCODE_ORDER_MAX_ENTRIES XED_ENCODE_ORDER_MAX_OPERANDS XED_ENC_GROUPS XED_ERROR_BAD_EVEX_LL_DEFINED XED_ERROR_BAD_EVEX_V_PRIME_DEFINED XED_ERROR_BAD_EVEX_Z_NO_MASKING_DEFINED XED_ERROR_BAD_LEGACY_PREFIX_DEFINED XED_ERROR_BAD_LOCK_PREFIX_DEFINED XED_ERROR_BAD_MAP_DEFINED XED_ERROR_BAD_MEMOP_INDEX_DEFINED XED_ERROR_BAD_REGISTER_DEFINED XED_ERROR_BAD_REG_MATCH_DEFINED XED_ERROR_BAD_REP_PREFIX_DEFINED XED_ERROR_BAD_REX_PREFIX_DEFINED XED_ERROR_BUFFER_TOO_SHORT_DEFINED XED_ERROR_CALLBACK_PROBLEM_DEFINED XED_ERROR_GATHER_REGS_DEFINED XED_ERROR_GENERAL_ERROR_DEFINED XED_ERROR_INSTR_TOO_LONG_DEFINED XED_ERROR_INVALID_FOR_CHIP_DEFINED XED_ERROR_INVALID_MODE_DEFINED XED_ERROR_LAST_DEFINED XED_ERROR_NONE_DEFINED XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED_DEFINED XED_ERROR_NO_OUTPUT_POINTER_DEFINED XED_EXCEPTION_AMX_E1_DEFINED XED_EXCEPTION_AMX_E1_EVEX_DEFINED XED_EXCEPTION_AMX_E2_DEFINED XED_EXCEPTION_AMX_E2_EVEX_DEFINED XED_EXCEPTION_AMX_E3_DEFINED XED_EXCEPTION_AMX_E3_EVEX_DEFINED XED_EXCEPTION_AMX_E4_DEFINED XED_EXCEPTION_AMX_E5_DEFINED XED_EXCEPTION_AMX_E6_DEFINED XED_EXCEPTION_APX_EVEX_BMI_DEFINED XED_EXCEPTION_APX_EVEX_CCMP_DEFINED XED_EXCEPTION_APX_EVEX_CET_WRSS_DEFINED XED_EXCEPTION_APX_EVEX_CET_WRUSS_DEFINED XED_EXCEPTION_APX_EVEX_CFCMOV_DEFINED XED_EXCEPTION_APX_EVEX_CMPCCXADD_DEFINED XED_EXCEPTION_APX_EVEX_ENQCMD_DEFINED XED_EXCEPTION_APX_EVEX_INT_DEFINED XED_EXCEPTION_APX_EVEX_INVEPT_DEFINED XED_EXCEPTION_APX_EVEX_INVPCID_DEFINED XED_EXCEPTION_APX_EVEX_INVVPID_DEFINED XED_EXCEPTION_APX_EVEX_KEYLOCKER_DEFINED XED_EXCEPTION_APX_EVEX_KMOV_DEFINED XED_EXCEPTION_APX_EVEX_PP2_DEFINED XED_EXCEPTION_APX_EVEX_SHA_DEFINED XED_EXCEPTION_APX_LEGACY_JMPABS_DEFINED XED_EXCEPTION_AVX512_E1NF_DEFINED XED_EXCEPTION_AVX512_E1_DEFINED XED_EXCEPTION_AVX512_E2_DEFINED XED_EXCEPTION_AVX512_E3NF_DEFINED XED_EXCEPTION_AVX512_E3_DEFINED XED_EXCEPTION_AVX512_E4NF_DEFINED XED_EXCEPTION_AVX512_E4_DEFINED XED_EXCEPTION_AVX512_E5NF_DEFINED XED_EXCEPTION_AVX512_E5_DEFINED XED_EXCEPTION_AVX512_E6NF_DEFINED XED_EXCEPTION_AVX512_E6_DEFINED XED_EXCEPTION_AVX512_E7NM128_DEFINED XED_EXCEPTION_AVX512_E7NM_DEFINED XED_EXCEPTION_AVX512_E9NF_DEFINED XED_EXCEPTION_AVX512_E10NF_DEFINED XED_EXCEPTION_AVX512_E10_DEFINED XED_EXCEPTION_AVX512_E11_DEFINED XED_EXCEPTION_AVX512_E12NP_DEFINED XED_EXCEPTION_AVX512_E12_DEFINED XED_EXCEPTION_AVX512_K20_DEFINED XED_EXCEPTION_AVX512_K21_DEFINED XED_EXCEPTION_AVX_TYPE_1_DEFINED XED_EXCEPTION_AVX_TYPE_2D_DEFINED XED_EXCEPTION_AVX_TYPE_2_DEFINED XED_EXCEPTION_AVX_TYPE_3_DEFINED XED_EXCEPTION_AVX_TYPE_4M_DEFINED XED_EXCEPTION_AVX_TYPE_4_DEFINED XED_EXCEPTION_AVX_TYPE_5L_DEFINED XED_EXCEPTION_AVX_TYPE_5_DEFINED XED_EXCEPTION_AVX_TYPE_6_DEFINED XED_EXCEPTION_AVX_TYPE_7_DEFINED XED_EXCEPTION_AVX_TYPE_8_DEFINED XED_EXCEPTION_AVX_TYPE_11_DEFINED XED_EXCEPTION_AVX_TYPE_12_DEFINED XED_EXCEPTION_AVX_TYPE_14_DEFINED XED_EXCEPTION_INVALID_DEFINED XED_EXCEPTION_LAST_DEFINED XED_EXCEPTION_MMX_FP_16ALIGN_DEFINED XED_EXCEPTION_MMX_FP_DEFINED XED_EXCEPTION_MMX_MEM_DEFINED XED_EXCEPTION_MMX_NOFP2_DEFINED XED_EXCEPTION_MMX_NOFP_DEFINED XED_EXCEPTION_MMX_NOMEM_DEFINED XED_EXCEPTION_SSE_TYPE_1_DEFINED XED_EXCEPTION_SSE_TYPE_2D_DEFINED XED_EXCEPTION_SSE_TYPE_2_DEFINED XED_EXCEPTION_SSE_TYPE_3_DEFINED XED_EXCEPTION_SSE_TYPE_4M_DEFINED XED_EXCEPTION_SSE_TYPE_4_DEFINED XED_EXCEPTION_SSE_TYPE_5_DEFINED XED_EXCEPTION_SSE_TYPE_7_DEFINED XED_EXTENSION_3DNOW_DEFINED XED_EXTENSION_3DNOW_PREFETCH_DEFINED XED_EXTENSION_ADOX_ADCX_DEFINED XED_EXTENSION_AES_DEFINED XED_EXTENSION_AMD_INVLPGB_DEFINED XED_EXTENSION_AMX_FP16_DEFINED XED_EXTENSION_AMX_TILE_DEFINED XED_EXTENSION_APXEVEX_DEFINED XED_EXTENSION_APX_F_DEFINED XED_EXTENSION_AVX2GATHER_DEFINED XED_EXTENSION_AVX2_DEFINED XED_EXTENSION_AVX512EVEX_DEFINED XED_EXTENSION_AVX512VEX_DEFINED XED_EXTENSION_AVXAES_DEFINED XED_EXTENSION_AVX_DEFINED XED_EXTENSION_AVX_IFMA_DEFINED XED_EXTENSION_AVX_NE_CONVERT_DEFINED XED_EXTENSION_AVX_VNNI_DEFINED XED_EXTENSION_AVX_VNNI_INT8_DEFINED XED_EXTENSION_AVX_VNNI_INT16_DEFINED XED_EXTENSION_BASE_DEFINED XED_EXTENSION_BMI1_DEFINED XED_EXTENSION_BMI2_DEFINED XED_EXTENSION_CET_DEFINED XED_EXTENSION_CLDEMOTE_DEFINED XED_EXTENSION_CLFLUSHOPT_DEFINED XED_EXTENSION_CLFSH_DEFINED XED_EXTENSION_CLWB_DEFINED XED_EXTENSION_CLZERO_DEFINED XED_EXTENSION_CMPCCXADD_DEFINED XED_EXTENSION_ENQCMD_DEFINED XED_EXTENSION_F16C_DEFINED XED_EXTENSION_FMA4_DEFINED XED_EXTENSION_FMA_DEFINED XED_EXTENSION_FRED_DEFINED XED_EXTENSION_GFNI_DEFINED XED_EXTENSION_HRESET_DEFINED XED_EXTENSION_ICACHE_PREFETCH_DEFINED XED_EXTENSION_INVALID_DEFINED XED_EXTENSION_INVPCID_DEFINED XED_EXTENSION_KEYLOCKER_DEFINED XED_EXTENSION_KEYLOCKER_WIDE_DEFINED XED_EXTENSION_LAST_DEFINED XED_EXTENSION_LKGS_DEFINED XED_EXTENSION_LONGMODE_DEFINED XED_EXTENSION_LZCNT_DEFINED XED_EXTENSION_MCOMMIT_DEFINED XED_EXTENSION_MMX_DEFINED XED_EXTENSION_MONITORX_DEFINED XED_EXTENSION_MONITOR_DEFINED XED_EXTENSION_MOVBE_DEFINED XED_EXTENSION_MOVDIR_DEFINED XED_EXTENSION_MPX_DEFINED XED_EXTENSION_MSRLIST_DEFINED XED_EXTENSION_PAUSE_DEFINED XED_EXTENSION_PBNDKB_DEFINED XED_EXTENSION_PCLMULQDQ_DEFINED XED_EXTENSION_PCONFIG_DEFINED XED_EXTENSION_PKU_DEFINED XED_EXTENSION_PREFETCHWT1_DEFINED XED_EXTENSION_PTWRITE_DEFINED XED_EXTENSION_RAO_INT_DEFINED XED_EXTENSION_RDPID_DEFINED XED_EXTENSION_RDPRU_DEFINED XED_EXTENSION_RDRAND_DEFINED XED_EXTENSION_RDSEED_DEFINED XED_EXTENSION_RDTSCP_DEFINED XED_EXTENSION_RDWRFSGS_DEFINED XED_EXTENSION_RTM_DEFINED XED_EXTENSION_SERIALIZE_DEFINED XED_EXTENSION_SGX_DEFINED XED_EXTENSION_SGX_ENCLV_DEFINED XED_EXTENSION_SHA512_DEFINED XED_EXTENSION_SHA_DEFINED XED_EXTENSION_SM3_DEFINED XED_EXTENSION_SM4_DEFINED XED_EXTENSION_SMAP_DEFINED XED_EXTENSION_SMX_DEFINED XED_EXTENSION_SNP_DEFINED XED_EXTENSION_SSE2_DEFINED XED_EXTENSION_SSE3_DEFINED XED_EXTENSION_SSE4A_DEFINED XED_EXTENSION_SSE4_DEFINED XED_EXTENSION_SSE_DEFINED XED_EXTENSION_SSSE3_DEFINED XED_EXTENSION_SVM_DEFINED XED_EXTENSION_TBM_DEFINED XED_EXTENSION_TDX_DEFINED XED_EXTENSION_TSX_LDTRK_DEFINED XED_EXTENSION_UINTR_DEFINED XED_EXTENSION_USER_MSR_DEFINED XED_EXTENSION_VAES_DEFINED XED_EXTENSION_VIA_PADLOCK_AES_DEFINED XED_EXTENSION_VIA_PADLOCK_MONTMUL_DEFINED XED_EXTENSION_VIA_PADLOCK_RNG_DEFINED XED_EXTENSION_VIA_PADLOCK_SHA_DEFINED XED_EXTENSION_VMFUNC_DEFINED XED_EXTENSION_VPCLMULQDQ_DEFINED XED_EXTENSION_VTX_DEFINED XED_EXTENSION_WAITPKG_DEFINED XED_EXTENSION_WBNOINVD_DEFINED XED_EXTENSION_WRMSRNS_DEFINED XED_EXTENSION_X87_DEFINED XED_EXTENSION_XOP_DEFINED XED_EXTENSION_XSAVEC_DEFINED XED_EXTENSION_XSAVEOPT_DEFINED XED_EXTENSION_XSAVES_DEFINED XED_EXTENSION_XSAVE_DEFINED XED_FEATURE_VECTOR_MAX XED_FLAG_ACTION_0_DEFINED XED_FLAG_ACTION_1_DEFINED XED_FLAG_ACTION_INVALID_DEFINED XED_FLAG_ACTION_LAST_DEFINED XED_FLAG_ACTION_ah_DEFINED XED_FLAG_ACTION_mod_DEFINED XED_FLAG_ACTION_pop_DEFINED XED_FLAG_ACTION_tst_DEFINED XED_FLAG_ACTION_u_DEFINED XED_FLAG_INVALID_DEFINED XED_FLAG_LAST_DEFINED XED_FLAG_ac_DEFINED XED_FLAG_af_DEFINED XED_FLAG_cf_DEFINED XED_FLAG_df_DEFINED XED_FLAG_fc0_DEFINED XED_FLAG_fc1_DEFINED XED_FLAG_fc2_DEFINED XED_FLAG_fc3_DEFINED XED_FLAG_id_DEFINED XED_FLAG_if_DEFINED XED_FLAG_iopl_DEFINED XED_FLAG_nt_DEFINED XED_FLAG_of_DEFINED XED_FLAG_pf_DEFINED XED_FLAG_rf_DEFINED XED_FLAG_sf_DEFINED XED_FLAG_tf_DEFINED XED_FLAG_vif_DEFINED XED_FLAG_vip_DEFINED XED_FLAG_vm_DEFINED XED_FLAG_zf_DEFINED XED_FMT_08X XED_FMT_9U XED_FMT_D XED_FMT_LD XED_FMT_LU XED_FMT_LU12 XED_FMT_LX XED_FMT_LX16 XED_FMT_LX16_UPPER XED_FMT_LX_UPPER XED_FMT_SIZET XED_FMT_U XED_FMT_X XED_ICLASS_AAA_DEFINED XED_ICLASS_AADD_DEFINED XED_ICLASS_AAD_DEFINED XED_ICLASS_AAM_DEFINED XED_ICLASS_AAND_DEFINED XED_ICLASS_AAS_DEFINED XED_ICLASS_ADCX_DEFINED XED_ICLASS_ADC_DEFINED XED_ICLASS_ADC_LOCK_DEFINED XED_ICLASS_ADDPD_DEFINED XED_ICLASS_ADDPS_DEFINED XED_ICLASS_ADDSD_DEFINED XED_ICLASS_ADDSS_DEFINED XED_ICLASS_ADDSUBPD_DEFINED XED_ICLASS_ADDSUBPS_DEFINED XED_ICLASS_ADD_DEFINED XED_ICLASS_ADD_LOCK_DEFINED XED_ICLASS_ADOX_DEFINED XED_ICLASS_AESDEC128KL_DEFINED XED_ICLASS_AESDEC256KL_DEFINED XED_ICLASS_AESDECLAST_DEFINED XED_ICLASS_AESDECWIDE128KL_DEFINED XED_ICLASS_AESDECWIDE256KL_DEFINED XED_ICLASS_AESDEC_DEFINED XED_ICLASS_AESENC128KL_DEFINED XED_ICLASS_AESENC256KL_DEFINED XED_ICLASS_AESENCLAST_DEFINED XED_ICLASS_AESENCWIDE128KL_DEFINED XED_ICLASS_AESENCWIDE256KL_DEFINED XED_ICLASS_AESENC_DEFINED XED_ICLASS_AESIMC_DEFINED XED_ICLASS_AESKEYGENASSIST_DEFINED XED_ICLASS_ANDNPD_DEFINED XED_ICLASS_ANDNPS_DEFINED XED_ICLASS_ANDN_DEFINED XED_ICLASS_ANDPD_DEFINED XED_ICLASS_ANDPS_DEFINED XED_ICLASS_AND_DEFINED XED_ICLASS_AND_LOCK_DEFINED XED_ICLASS_AOR_DEFINED XED_ICLASS_ARPL_DEFINED XED_ICLASS_AXOR_DEFINED XED_ICLASS_BEXTR_DEFINED XED_ICLASS_BEXTR_XOP_DEFINED XED_ICLASS_BLCFILL_DEFINED XED_ICLASS_BLCIC_DEFINED XED_ICLASS_BLCI_DEFINED XED_ICLASS_BLCMSK_DEFINED XED_ICLASS_BLCS_DEFINED XED_ICLASS_BLENDPD_DEFINED XED_ICLASS_BLENDPS_DEFINED XED_ICLASS_BLENDVPD_DEFINED XED_ICLASS_BLENDVPS_DEFINED XED_ICLASS_BLSFILL_DEFINED XED_ICLASS_BLSIC_DEFINED XED_ICLASS_BLSI_DEFINED XED_ICLASS_BLSMSK_DEFINED XED_ICLASS_BLSR_DEFINED XED_ICLASS_BNDCL_DEFINED XED_ICLASS_BNDCN_DEFINED XED_ICLASS_BNDCU_DEFINED XED_ICLASS_BNDLDX_DEFINED XED_ICLASS_BNDMK_DEFINED XED_ICLASS_BNDMOV_DEFINED XED_ICLASS_BNDSTX_DEFINED XED_ICLASS_BOUND_DEFINED XED_ICLASS_BSF_DEFINED XED_ICLASS_BSR_DEFINED XED_ICLASS_BSWAP_DEFINED XED_ICLASS_BTC_DEFINED XED_ICLASS_BTC_LOCK_DEFINED XED_ICLASS_BTR_DEFINED XED_ICLASS_BTR_LOCK_DEFINED XED_ICLASS_BTS_DEFINED XED_ICLASS_BTS_LOCK_DEFINED XED_ICLASS_BT_DEFINED XED_ICLASS_BZHI_DEFINED XED_ICLASS_CALL_FAR_DEFINED XED_ICLASS_CALL_NEAR_DEFINED XED_ICLASS_CBW_DEFINED XED_ICLASS_CCMPBE_DEFINED XED_ICLASS_CCMPB_DEFINED XED_ICLASS_CCMPF_DEFINED XED_ICLASS_CCMPLE_DEFINED XED_ICLASS_CCMPL_DEFINED XED_ICLASS_CCMPNBE_DEFINED XED_ICLASS_CCMPNB_DEFINED XED_ICLASS_CCMPNLE_DEFINED XED_ICLASS_CCMPNL_DEFINED XED_ICLASS_CCMPNO_DEFINED XED_ICLASS_CCMPNS_DEFINED XED_ICLASS_CCMPNZ_DEFINED XED_ICLASS_CCMPO_DEFINED XED_ICLASS_CCMPS_DEFINED XED_ICLASS_CCMPT_DEFINED XED_ICLASS_CCMPZ_DEFINED XED_ICLASS_CDQE_DEFINED XED_ICLASS_CDQ_DEFINED XED_ICLASS_CFCMOVBE_DEFINED XED_ICLASS_CFCMOVB_DEFINED XED_ICLASS_CFCMOVLE_DEFINED XED_ICLASS_CFCMOVL_DEFINED XED_ICLASS_CFCMOVNBE_DEFINED XED_ICLASS_CFCMOVNB_DEFINED XED_ICLASS_CFCMOVNLE_DEFINED XED_ICLASS_CFCMOVNL_DEFINED XED_ICLASS_CFCMOVNO_DEFINED XED_ICLASS_CFCMOVNP_DEFINED XED_ICLASS_CFCMOVNS_DEFINED XED_ICLASS_CFCMOVNZ_DEFINED XED_ICLASS_CFCMOVO_DEFINED XED_ICLASS_CFCMOVP_DEFINED XED_ICLASS_CFCMOVS_DEFINED XED_ICLASS_CFCMOVZ_DEFINED XED_ICLASS_CLAC_DEFINED XED_ICLASS_CLC_DEFINED XED_ICLASS_CLDEMOTE_DEFINED XED_ICLASS_CLD_DEFINED XED_ICLASS_CLFLUSHOPT_DEFINED XED_ICLASS_CLFLUSH_DEFINED XED_ICLASS_CLGI_DEFINED XED_ICLASS_CLI_DEFINED XED_ICLASS_CLRSSBSY_DEFINED XED_ICLASS_CLTS_DEFINED XED_ICLASS_CLUI_DEFINED XED_ICLASS_CLWB_DEFINED XED_ICLASS_CLZERO_DEFINED XED_ICLASS_CMC_DEFINED XED_ICLASS_CMOVBE_DEFINED XED_ICLASS_CMOVB_DEFINED XED_ICLASS_CMOVLE_DEFINED XED_ICLASS_CMOVL_DEFINED XED_ICLASS_CMOVNBE_DEFINED XED_ICLASS_CMOVNB_DEFINED XED_ICLASS_CMOVNLE_DEFINED XED_ICLASS_CMOVNL_DEFINED XED_ICLASS_CMOVNO_DEFINED XED_ICLASS_CMOVNP_DEFINED XED_ICLASS_CMOVNS_DEFINED XED_ICLASS_CMOVNZ_DEFINED XED_ICLASS_CMOVO_DEFINED XED_ICLASS_CMOVP_DEFINED XED_ICLASS_CMOVS_DEFINED XED_ICLASS_CMOVZ_DEFINED XED_ICLASS_CMPBEXADD_DEFINED XED_ICLASS_CMPBXADD_DEFINED XED_ICLASS_CMPLEXADD_DEFINED XED_ICLASS_CMPLXADD_DEFINED XED_ICLASS_CMPNBEXADD_DEFINED XED_ICLASS_CMPNBXADD_DEFINED XED_ICLASS_CMPNLEXADD_DEFINED XED_ICLASS_CMPNLXADD_DEFINED XED_ICLASS_CMPNOXADD_DEFINED XED_ICLASS_CMPNPXADD_DEFINED XED_ICLASS_CMPNSXADD_DEFINED XED_ICLASS_CMPNZXADD_DEFINED XED_ICLASS_CMPOXADD_DEFINED XED_ICLASS_CMPPD_DEFINED XED_ICLASS_CMPPS_DEFINED XED_ICLASS_CMPPXADD_DEFINED XED_ICLASS_CMPSB_DEFINED XED_ICLASS_CMPSD_DEFINED XED_ICLASS_CMPSD_XMM_DEFINED XED_ICLASS_CMPSQ_DEFINED XED_ICLASS_CMPSS_DEFINED XED_ICLASS_CMPSW_DEFINED XED_ICLASS_CMPSXADD_DEFINED XED_ICLASS_CMPXCHG8B_DEFINED XED_ICLASS_CMPXCHG8B_LOCK_DEFINED XED_ICLASS_CMPXCHG16B_DEFINED XED_ICLASS_CMPXCHG16B_LOCK_DEFINED XED_ICLASS_CMPXCHG_DEFINED XED_ICLASS_CMPXCHG_LOCK_DEFINED XED_ICLASS_CMPZXADD_DEFINED XED_ICLASS_CMP_DEFINED XED_ICLASS_COMISD_DEFINED XED_ICLASS_COMISS_DEFINED XED_ICLASS_CPUID_DEFINED XED_ICLASS_CQO_DEFINED XED_ICLASS_CRC32_DEFINED XED_ICLASS_CTESTBE_DEFINED XED_ICLASS_CTESTB_DEFINED XED_ICLASS_CTESTF_DEFINED XED_ICLASS_CTESTLE_DEFINED XED_ICLASS_CTESTL_DEFINED XED_ICLASS_CTESTNBE_DEFINED XED_ICLASS_CTESTNB_DEFINED XED_ICLASS_CTESTNLE_DEFINED XED_ICLASS_CTESTNL_DEFINED XED_ICLASS_CTESTNO_DEFINED XED_ICLASS_CTESTNS_DEFINED XED_ICLASS_CTESTNZ_DEFINED XED_ICLASS_CTESTO_DEFINED XED_ICLASS_CTESTS_DEFINED XED_ICLASS_CTESTT_DEFINED XED_ICLASS_CTESTZ_DEFINED XED_ICLASS_CVTDQ2PD_DEFINED XED_ICLASS_CVTDQ2PS_DEFINED XED_ICLASS_CVTPD2DQ_DEFINED XED_ICLASS_CVTPD2PI_DEFINED XED_ICLASS_CVTPD2PS_DEFINED XED_ICLASS_CVTPI2PD_DEFINED XED_ICLASS_CVTPI2PS_DEFINED XED_ICLASS_CVTPS2DQ_DEFINED XED_ICLASS_CVTPS2PD_DEFINED XED_ICLASS_CVTPS2PI_DEFINED XED_ICLASS_CVTSD2SI_DEFINED XED_ICLASS_CVTSD2SS_DEFINED XED_ICLASS_CVTSI2SD_DEFINED XED_ICLASS_CVTSI2SS_DEFINED XED_ICLASS_CVTSS2SD_DEFINED XED_ICLASS_CVTSS2SI_DEFINED XED_ICLASS_CVTTPD2DQ_DEFINED XED_ICLASS_CVTTPD2PI_DEFINED XED_ICLASS_CVTTPS2DQ_DEFINED XED_ICLASS_CVTTPS2PI_DEFINED XED_ICLASS_CVTTSD2SI_DEFINED XED_ICLASS_CVTTSS2SI_DEFINED XED_ICLASS_CWDE_DEFINED XED_ICLASS_CWD_DEFINED XED_ICLASS_DAA_DEFINED XED_ICLASS_DAS_DEFINED XED_ICLASS_DEC_DEFINED XED_ICLASS_DEC_LOCK_DEFINED XED_ICLASS_DIVPD_DEFINED XED_ICLASS_DIVPS_DEFINED XED_ICLASS_DIVSD_DEFINED XED_ICLASS_DIVSS_DEFINED XED_ICLASS_DIV_DEFINED XED_ICLASS_DPPD_DEFINED XED_ICLASS_DPPS_DEFINED XED_ICLASS_EMMS_DEFINED XED_ICLASS_ENCLS_DEFINED XED_ICLASS_ENCLU_DEFINED XED_ICLASS_ENCLV_DEFINED XED_ICLASS_ENCODEKEY128_DEFINED XED_ICLASS_ENCODEKEY256_DEFINED XED_ICLASS_ENDBR32_DEFINED XED_ICLASS_ENDBR64_DEFINED XED_ICLASS_ENQCMDS_DEFINED XED_ICLASS_ENQCMD_DEFINED XED_ICLASS_ENTER_DEFINED XED_ICLASS_ERETS_DEFINED XED_ICLASS_ERETU_DEFINED XED_ICLASS_EXTRACTPS_DEFINED XED_ICLASS_EXTRQ_DEFINED XED_ICLASS_F2XM1_DEFINED XED_ICLASS_FABS_DEFINED XED_ICLASS_FADDP_DEFINED XED_ICLASS_FADD_DEFINED XED_ICLASS_FBLD_DEFINED XED_ICLASS_FBSTP_DEFINED XED_ICLASS_FCHS_DEFINED XED_ICLASS_FCMOVBE_DEFINED XED_ICLASS_FCMOVB_DEFINED XED_ICLASS_FCMOVE_DEFINED XED_ICLASS_FCMOVNBE_DEFINED XED_ICLASS_FCMOVNB_DEFINED XED_ICLASS_FCMOVNE_DEFINED XED_ICLASS_FCMOVNU_DEFINED XED_ICLASS_FCMOVU_DEFINED XED_ICLASS_FCOMIP_DEFINED XED_ICLASS_FCOMI_DEFINED XED_ICLASS_FCOMPP_DEFINED XED_ICLASS_FCOMP_DEFINED XED_ICLASS_FCOM_DEFINED XED_ICLASS_FCOS_DEFINED XED_ICLASS_FDECSTP_DEFINED XED_ICLASS_FDISI8087_NOP_DEFINED XED_ICLASS_FDIVP_DEFINED XED_ICLASS_FDIVRP_DEFINED XED_ICLASS_FDIVR_DEFINED XED_ICLASS_FDIV_DEFINED XED_ICLASS_FEMMS_DEFINED XED_ICLASS_FENI8087_NOP_DEFINED XED_ICLASS_FFREEP_DEFINED XED_ICLASS_FFREE_DEFINED XED_ICLASS_FIADD_DEFINED XED_ICLASS_FICOMP_DEFINED XED_ICLASS_FICOM_DEFINED XED_ICLASS_FIDIVR_DEFINED XED_ICLASS_FIDIV_DEFINED XED_ICLASS_FILD_DEFINED XED_ICLASS_FIMUL_DEFINED XED_ICLASS_FINCSTP_DEFINED XED_ICLASS_FISTP_DEFINED XED_ICLASS_FISTTP_DEFINED XED_ICLASS_FIST_DEFINED XED_ICLASS_FISUBR_DEFINED XED_ICLASS_FISUB_DEFINED XED_ICLASS_FLD1_DEFINED XED_ICLASS_FLDCW_DEFINED XED_ICLASS_FLDENV_DEFINED XED_ICLASS_FLDL2E_DEFINED XED_ICLASS_FLDL2T_DEFINED XED_ICLASS_FLDLG2_DEFINED XED_ICLASS_FLDLN2_DEFINED XED_ICLASS_FLDPI_DEFINED XED_ICLASS_FLDZ_DEFINED XED_ICLASS_FLD_DEFINED XED_ICLASS_FMULP_DEFINED XED_ICLASS_FMUL_DEFINED XED_ICLASS_FNCLEX_DEFINED XED_ICLASS_FNINIT_DEFINED XED_ICLASS_FNOP_DEFINED XED_ICLASS_FNSAVE_DEFINED XED_ICLASS_FNSTCW_DEFINED XED_ICLASS_FNSTENV_DEFINED XED_ICLASS_FNSTSW_DEFINED XED_ICLASS_FPATAN_DEFINED XED_ICLASS_FPREM1_DEFINED XED_ICLASS_FPREM_DEFINED XED_ICLASS_FPTAN_DEFINED XED_ICLASS_FRNDINT_DEFINED XED_ICLASS_FRSTOR_DEFINED XED_ICLASS_FSCALE_DEFINED XED_ICLASS_FSETPM287_NOP_DEFINED XED_ICLASS_FSINCOS_DEFINED XED_ICLASS_FSIN_DEFINED XED_ICLASS_FSQRT_DEFINED XED_ICLASS_FSTPNCE_DEFINED XED_ICLASS_FSTP_DEFINED XED_ICLASS_FST_DEFINED XED_ICLASS_FSUBP_DEFINED XED_ICLASS_FSUBRP_DEFINED XED_ICLASS_FSUBR_DEFINED XED_ICLASS_FSUB_DEFINED XED_ICLASS_FTST_DEFINED XED_ICLASS_FUCOMIP_DEFINED XED_ICLASS_FUCOMI_DEFINED XED_ICLASS_FUCOMPP_DEFINED XED_ICLASS_FUCOMP_DEFINED XED_ICLASS_FUCOM_DEFINED XED_ICLASS_FWAIT_DEFINED XED_ICLASS_FXAM_DEFINED XED_ICLASS_FXCH_DEFINED XED_ICLASS_FXRSTOR64_DEFINED XED_ICLASS_FXRSTOR_DEFINED XED_ICLASS_FXSAVE64_DEFINED XED_ICLASS_FXSAVE_DEFINED XED_ICLASS_FXTRACT_DEFINED XED_ICLASS_FYL2XP1_DEFINED XED_ICLASS_FYL2X_DEFINED XED_ICLASS_GETSEC_DEFINED XED_ICLASS_GF2P8AFFINEINVQB_DEFINED XED_ICLASS_GF2P8AFFINEQB_DEFINED XED_ICLASS_GF2P8MULB_DEFINED XED_ICLASS_HADDPD_DEFINED XED_ICLASS_HADDPS_DEFINED XED_ICLASS_HLT_DEFINED XED_ICLASS_HRESET_DEFINED XED_ICLASS_HSUBPD_DEFINED XED_ICLASS_HSUBPS_DEFINED XED_ICLASS_IDIV_DEFINED XED_ICLASS_IMUL_DEFINED XED_ICLASS_INCSSPD_DEFINED XED_ICLASS_INCSSPQ_DEFINED XED_ICLASS_INC_DEFINED XED_ICLASS_INC_LOCK_DEFINED XED_ICLASS_INSB_DEFINED XED_ICLASS_INSD_DEFINED XED_ICLASS_INSERTPS_DEFINED XED_ICLASS_INSERTQ_DEFINED XED_ICLASS_INSW_DEFINED XED_ICLASS_INT1_DEFINED XED_ICLASS_INT3_DEFINED XED_ICLASS_INTO_DEFINED XED_ICLASS_INT_DEFINED XED_ICLASS_INVALID_DEFINED XED_ICLASS_INVD_DEFINED XED_ICLASS_INVEPT_DEFINED XED_ICLASS_INVLPGA_DEFINED XED_ICLASS_INVLPGB_DEFINED XED_ICLASS_INVLPG_DEFINED XED_ICLASS_INVPCID_DEFINED XED_ICLASS_INVVPID_DEFINED XED_ICLASS_IN_DEFINED XED_ICLASS_IRETD_DEFINED XED_ICLASS_IRETQ_DEFINED XED_ICLASS_IRET_DEFINED XED_ICLASS_JBE_DEFINED XED_ICLASS_JB_DEFINED XED_ICLASS_JCXZ_DEFINED XED_ICLASS_JECXZ_DEFINED XED_ICLASS_JLE_DEFINED XED_ICLASS_JL_DEFINED XED_ICLASS_JMPABS_DEFINED XED_ICLASS_JMP_DEFINED XED_ICLASS_JMP_FAR_DEFINED XED_ICLASS_JNBE_DEFINED XED_ICLASS_JNB_DEFINED XED_ICLASS_JNLE_DEFINED XED_ICLASS_JNL_DEFINED XED_ICLASS_JNO_DEFINED XED_ICLASS_JNP_DEFINED XED_ICLASS_JNS_DEFINED XED_ICLASS_JNZ_DEFINED XED_ICLASS_JO_DEFINED XED_ICLASS_JP_DEFINED XED_ICLASS_JRCXZ_DEFINED XED_ICLASS_JS_DEFINED XED_ICLASS_JZ_DEFINED XED_ICLASS_KADDB_DEFINED XED_ICLASS_KADDD_DEFINED XED_ICLASS_KADDQ_DEFINED XED_ICLASS_KADDW_DEFINED XED_ICLASS_KANDB_DEFINED XED_ICLASS_KANDD_DEFINED XED_ICLASS_KANDNB_DEFINED XED_ICLASS_KANDND_DEFINED XED_ICLASS_KANDNQ_DEFINED XED_ICLASS_KANDNW_DEFINED XED_ICLASS_KANDQ_DEFINED XED_ICLASS_KANDW_DEFINED XED_ICLASS_KMOVB_DEFINED XED_ICLASS_KMOVD_DEFINED XED_ICLASS_KMOVQ_DEFINED XED_ICLASS_KMOVW_DEFINED XED_ICLASS_KNOTB_DEFINED XED_ICLASS_KNOTD_DEFINED XED_ICLASS_KNOTQ_DEFINED XED_ICLASS_KNOTW_DEFINED XED_ICLASS_KORB_DEFINED XED_ICLASS_KORD_DEFINED XED_ICLASS_KORQ_DEFINED XED_ICLASS_KORTESTB_DEFINED XED_ICLASS_KORTESTD_DEFINED XED_ICLASS_KORTESTQ_DEFINED XED_ICLASS_KORTESTW_DEFINED XED_ICLASS_KORW_DEFINED XED_ICLASS_KSHIFTLB_DEFINED XED_ICLASS_KSHIFTLD_DEFINED XED_ICLASS_KSHIFTLQ_DEFINED XED_ICLASS_KSHIFTLW_DEFINED XED_ICLASS_KSHIFTRB_DEFINED XED_ICLASS_KSHIFTRD_DEFINED XED_ICLASS_KSHIFTRQ_DEFINED XED_ICLASS_KSHIFTRW_DEFINED XED_ICLASS_KTESTB_DEFINED XED_ICLASS_KTESTD_DEFINED XED_ICLASS_KTESTQ_DEFINED XED_ICLASS_KTESTW_DEFINED XED_ICLASS_KUNPCKBW_DEFINED XED_ICLASS_KUNPCKDQ_DEFINED XED_ICLASS_KUNPCKWD_DEFINED XED_ICLASS_KXNORB_DEFINED XED_ICLASS_KXNORD_DEFINED XED_ICLASS_KXNORQ_DEFINED XED_ICLASS_KXNORW_DEFINED XED_ICLASS_KXORB_DEFINED XED_ICLASS_KXORD_DEFINED XED_ICLASS_KXORQ_DEFINED XED_ICLASS_KXORW_DEFINED XED_ICLASS_LAHF_DEFINED XED_ICLASS_LAR_DEFINED XED_ICLASS_LAST_DEFINED XED_ICLASS_LDDQU_DEFINED XED_ICLASS_LDMXCSR_DEFINED XED_ICLASS_LDS_DEFINED XED_ICLASS_LDTILECFG_DEFINED XED_ICLASS_LEAVE_DEFINED XED_ICLASS_LEA_DEFINED XED_ICLASS_LES_DEFINED XED_ICLASS_LFENCE_DEFINED XED_ICLASS_LFS_DEFINED XED_ICLASS_LGDT_DEFINED XED_ICLASS_LGS_DEFINED XED_ICLASS_LIDT_DEFINED XED_ICLASS_LKGS_DEFINED XED_ICLASS_LLDT_DEFINED XED_ICLASS_LLWPCB_DEFINED XED_ICLASS_LMSW_DEFINED XED_ICLASS_LOADIWKEY_DEFINED XED_ICLASS_LODSB_DEFINED XED_ICLASS_LODSD_DEFINED XED_ICLASS_LODSQ_DEFINED XED_ICLASS_LODSW_DEFINED XED_ICLASS_LOOPE_DEFINED XED_ICLASS_LOOPNE_DEFINED XED_ICLASS_LOOP_DEFINED XED_ICLASS_LSL_DEFINED XED_ICLASS_LSS_DEFINED XED_ICLASS_LTR_DEFINED XED_ICLASS_LWPINS_DEFINED XED_ICLASS_LWPVAL_DEFINED XED_ICLASS_LZCNT_DEFINED XED_ICLASS_MASKMOVDQU_DEFINED XED_ICLASS_MASKMOVQ_DEFINED XED_ICLASS_MAXPD_DEFINED XED_ICLASS_MAXPS_DEFINED XED_ICLASS_MAXSD_DEFINED XED_ICLASS_MAXSS_DEFINED XED_ICLASS_MCOMMIT_DEFINED XED_ICLASS_MFENCE_DEFINED XED_ICLASS_MINPD_DEFINED XED_ICLASS_MINPS_DEFINED XED_ICLASS_MINSD_DEFINED XED_ICLASS_MINSS_DEFINED XED_ICLASS_MONITORX_DEFINED XED_ICLASS_MONITOR_DEFINED XED_ICLASS_MOVAPD_DEFINED XED_ICLASS_MOVAPS_DEFINED XED_ICLASS_MOVBE_DEFINED XED_ICLASS_MOVDDUP_DEFINED XED_ICLASS_MOVDIR64B_DEFINED XED_ICLASS_MOVDIRI_DEFINED XED_ICLASS_MOVDQ2Q_DEFINED XED_ICLASS_MOVDQA_DEFINED XED_ICLASS_MOVDQU_DEFINED XED_ICLASS_MOVD_DEFINED XED_ICLASS_MOVHLPS_DEFINED XED_ICLASS_MOVHPD_DEFINED XED_ICLASS_MOVHPS_DEFINED XED_ICLASS_MOVLHPS_DEFINED XED_ICLASS_MOVLPD_DEFINED XED_ICLASS_MOVLPS_DEFINED XED_ICLASS_MOVMSKPD_DEFINED XED_ICLASS_MOVMSKPS_DEFINED XED_ICLASS_MOVNTDQA_DEFINED XED_ICLASS_MOVNTDQ_DEFINED XED_ICLASS_MOVNTI_DEFINED XED_ICLASS_MOVNTPD_DEFINED XED_ICLASS_MOVNTPS_DEFINED XED_ICLASS_MOVNTQ_DEFINED XED_ICLASS_MOVNTSD_DEFINED XED_ICLASS_MOVNTSS_DEFINED XED_ICLASS_MOVQ2DQ_DEFINED XED_ICLASS_MOVQ_DEFINED XED_ICLASS_MOVSB_DEFINED XED_ICLASS_MOVSD_DEFINED XED_ICLASS_MOVSD_XMM_DEFINED XED_ICLASS_MOVSHDUP_DEFINED XED_ICLASS_MOVSLDUP_DEFINED XED_ICLASS_MOVSQ_DEFINED XED_ICLASS_MOVSS_DEFINED XED_ICLASS_MOVSW_DEFINED XED_ICLASS_MOVSXD_DEFINED XED_ICLASS_MOVSX_DEFINED XED_ICLASS_MOVUPD_DEFINED XED_ICLASS_MOVUPS_DEFINED XED_ICLASS_MOVZX_DEFINED XED_ICLASS_MOV_CR_DEFINED XED_ICLASS_MOV_DEFINED XED_ICLASS_MOV_DR_DEFINED XED_ICLASS_MPSADBW_DEFINED XED_ICLASS_MULPD_DEFINED XED_ICLASS_MULPS_DEFINED XED_ICLASS_MULSD_DEFINED XED_ICLASS_MULSS_DEFINED XED_ICLASS_MULX_DEFINED XED_ICLASS_MUL_DEFINED XED_ICLASS_MWAITX_DEFINED XED_ICLASS_MWAIT_DEFINED XED_ICLASS_NAME_STR_MAX XED_ICLASS_NEG_DEFINED XED_ICLASS_NEG_LOCK_DEFINED XED_ICLASS_NOP2_DEFINED XED_ICLASS_NOP3_DEFINED XED_ICLASS_NOP4_DEFINED XED_ICLASS_NOP5_DEFINED XED_ICLASS_NOP6_DEFINED XED_ICLASS_NOP7_DEFINED XED_ICLASS_NOP8_DEFINED XED_ICLASS_NOP9_DEFINED XED_ICLASS_NOP_DEFINED XED_ICLASS_NOT_DEFINED XED_ICLASS_NOT_LOCK_DEFINED XED_ICLASS_ORPD_DEFINED XED_ICLASS_ORPS_DEFINED XED_ICLASS_OR_DEFINED XED_ICLASS_OR_LOCK_DEFINED XED_ICLASS_OUTSB_DEFINED XED_ICLASS_OUTSD_DEFINED XED_ICLASS_OUTSW_DEFINED XED_ICLASS_OUT_DEFINED XED_ICLASS_PABSB_DEFINED XED_ICLASS_PABSD_DEFINED XED_ICLASS_PABSW_DEFINED XED_ICLASS_PACKSSDW_DEFINED XED_ICLASS_PACKSSWB_DEFINED XED_ICLASS_PACKUSDW_DEFINED XED_ICLASS_PACKUSWB_DEFINED XED_ICLASS_PADDB_DEFINED XED_ICLASS_PADDD_DEFINED XED_ICLASS_PADDQ_DEFINED XED_ICLASS_PADDSB_DEFINED XED_ICLASS_PADDSW_DEFINED XED_ICLASS_PADDUSB_DEFINED XED_ICLASS_PADDUSW_DEFINED XED_ICLASS_PADDW_DEFINED XED_ICLASS_PALIGNR_DEFINED XED_ICLASS_PANDN_DEFINED XED_ICLASS_PAND_DEFINED XED_ICLASS_PAUSE_DEFINED XED_ICLASS_PAVGB_DEFINED XED_ICLASS_PAVGUSB_DEFINED XED_ICLASS_PAVGW_DEFINED XED_ICLASS_PBLENDVB_DEFINED XED_ICLASS_PBLENDW_DEFINED XED_ICLASS_PBNDKB_DEFINED XED_ICLASS_PCLMULQDQ_DEFINED XED_ICLASS_PCMPEQB_DEFINED XED_ICLASS_PCMPEQD_DEFINED XED_ICLASS_PCMPEQQ_DEFINED XED_ICLASS_PCMPEQW_DEFINED XED_ICLASS_PCMPESTRI64_DEFINED XED_ICLASS_PCMPESTRI_DEFINED XED_ICLASS_PCMPESTRM64_DEFINED XED_ICLASS_PCMPESTRM_DEFINED XED_ICLASS_PCMPGTB_DEFINED XED_ICLASS_PCMPGTD_DEFINED XED_ICLASS_PCMPGTQ_DEFINED XED_ICLASS_PCMPGTW_DEFINED XED_ICLASS_PCMPISTRI64_DEFINED XED_ICLASS_PCMPISTRI_DEFINED XED_ICLASS_PCMPISTRM_DEFINED XED_ICLASS_PCONFIG_DEFINED XED_ICLASS_PDEP_DEFINED XED_ICLASS_PEXTRB_DEFINED XED_ICLASS_PEXTRD_DEFINED XED_ICLASS_PEXTRQ_DEFINED XED_ICLASS_PEXTRW_DEFINED XED_ICLASS_PEXTRW_SSE4_DEFINED XED_ICLASS_PEXT_DEFINED XED_ICLASS_PF2ID_DEFINED XED_ICLASS_PF2IW_DEFINED XED_ICLASS_PFACC_DEFINED XED_ICLASS_PFADD_DEFINED XED_ICLASS_PFCMPEQ_DEFINED XED_ICLASS_PFCMPGE_DEFINED XED_ICLASS_PFCMPGT_DEFINED XED_ICLASS_PFMAX_DEFINED XED_ICLASS_PFMIN_DEFINED XED_ICLASS_PFMUL_DEFINED XED_ICLASS_PFNACC_DEFINED XED_ICLASS_PFPNACC_DEFINED XED_ICLASS_PFRCPIT1_DEFINED XED_ICLASS_PFRCPIT2_DEFINED XED_ICLASS_PFRCP_DEFINED XED_ICLASS_PFRSQIT1_DEFINED XED_ICLASS_PFRSQRT_DEFINED XED_ICLASS_PFSUBR_DEFINED XED_ICLASS_PFSUB_DEFINED XED_ICLASS_PHADDD_DEFINED XED_ICLASS_PHADDSW_DEFINED XED_ICLASS_PHADDW_DEFINED XED_ICLASS_PHMINPOSUW_DEFINED XED_ICLASS_PHSUBD_DEFINED XED_ICLASS_PHSUBSW_DEFINED XED_ICLASS_PHSUBW_DEFINED XED_ICLASS_PI2FD_DEFINED XED_ICLASS_PI2FW_DEFINED XED_ICLASS_PINSRB_DEFINED XED_ICLASS_PINSRD_DEFINED XED_ICLASS_PINSRQ_DEFINED XED_ICLASS_PINSRW_DEFINED XED_ICLASS_PMADDUBSW_DEFINED XED_ICLASS_PMADDWD_DEFINED XED_ICLASS_PMAXSB_DEFINED XED_ICLASS_PMAXSD_DEFINED XED_ICLASS_PMAXSW_DEFINED XED_ICLASS_PMAXUB_DEFINED XED_ICLASS_PMAXUD_DEFINED XED_ICLASS_PMAXUW_DEFINED XED_ICLASS_PMINSB_DEFINED XED_ICLASS_PMINSD_DEFINED XED_ICLASS_PMINSW_DEFINED XED_ICLASS_PMINUB_DEFINED XED_ICLASS_PMINUD_DEFINED XED_ICLASS_PMINUW_DEFINED XED_ICLASS_PMOVMSKB_DEFINED XED_ICLASS_PMOVSXBD_DEFINED XED_ICLASS_PMOVSXBQ_DEFINED XED_ICLASS_PMOVSXBW_DEFINED XED_ICLASS_PMOVSXDQ_DEFINED XED_ICLASS_PMOVSXWD_DEFINED XED_ICLASS_PMOVSXWQ_DEFINED XED_ICLASS_PMOVZXBD_DEFINED XED_ICLASS_PMOVZXBQ_DEFINED XED_ICLASS_PMOVZXBW_DEFINED XED_ICLASS_PMOVZXDQ_DEFINED XED_ICLASS_PMOVZXWD_DEFINED XED_ICLASS_PMOVZXWQ_DEFINED XED_ICLASS_PMULDQ_DEFINED XED_ICLASS_PMULHRSW_DEFINED XED_ICLASS_PMULHRW_DEFINED XED_ICLASS_PMULHUW_DEFINED XED_ICLASS_PMULHW_DEFINED XED_ICLASS_PMULLD_DEFINED XED_ICLASS_PMULLW_DEFINED XED_ICLASS_PMULUDQ_DEFINED XED_ICLASS_POP2P_DEFINED XED_ICLASS_POP2_DEFINED XED_ICLASS_POPAD_DEFINED XED_ICLASS_POPA_DEFINED XED_ICLASS_POPCNT_DEFINED XED_ICLASS_POPFD_DEFINED XED_ICLASS_POPFQ_DEFINED XED_ICLASS_POPF_DEFINED XED_ICLASS_POPP_DEFINED XED_ICLASS_POP_DEFINED XED_ICLASS_POR_DEFINED XED_ICLASS_PREFETCHIT0_DEFINED XED_ICLASS_PREFETCHIT1_DEFINED XED_ICLASS_PREFETCHNTA_DEFINED XED_ICLASS_PREFETCHT0_DEFINED XED_ICLASS_PREFETCHT1_DEFINED XED_ICLASS_PREFETCHT2_DEFINED XED_ICLASS_PREFETCHWT1_DEFINED XED_ICLASS_PREFETCHW_DEFINED XED_ICLASS_PREFETCH_EXCLUSIVE_DEFINED XED_ICLASS_PREFETCH_RESERVED_DEFINED XED_ICLASS_PSADBW_DEFINED XED_ICLASS_PSHUFB_DEFINED XED_ICLASS_PSHUFD_DEFINED XED_ICLASS_PSHUFHW_DEFINED XED_ICLASS_PSHUFLW_DEFINED XED_ICLASS_PSHUFW_DEFINED XED_ICLASS_PSIGNB_DEFINED XED_ICLASS_PSIGND_DEFINED XED_ICLASS_PSIGNW_DEFINED XED_ICLASS_PSLLDQ_DEFINED XED_ICLASS_PSLLD_DEFINED XED_ICLASS_PSLLQ_DEFINED XED_ICLASS_PSLLW_DEFINED XED_ICLASS_PSMASH_DEFINED XED_ICLASS_PSRAD_DEFINED XED_ICLASS_PSRAW_DEFINED XED_ICLASS_PSRLDQ_DEFINED XED_ICLASS_PSRLD_DEFINED XED_ICLASS_PSRLQ_DEFINED XED_ICLASS_PSRLW_DEFINED XED_ICLASS_PSUBB_DEFINED XED_ICLASS_PSUBD_DEFINED XED_ICLASS_PSUBQ_DEFINED XED_ICLASS_PSUBSB_DEFINED XED_ICLASS_PSUBSW_DEFINED XED_ICLASS_PSUBUSB_DEFINED XED_ICLASS_PSUBUSW_DEFINED XED_ICLASS_PSUBW_DEFINED XED_ICLASS_PSWAPD_DEFINED XED_ICLASS_PTEST_DEFINED XED_ICLASS_PTWRITE_DEFINED XED_ICLASS_PUNPCKHBW_DEFINED XED_ICLASS_PUNPCKHDQ_DEFINED XED_ICLASS_PUNPCKHQDQ_DEFINED XED_ICLASS_PUNPCKHWD_DEFINED XED_ICLASS_PUNPCKLBW_DEFINED XED_ICLASS_PUNPCKLDQ_DEFINED XED_ICLASS_PUNPCKLQDQ_DEFINED XED_ICLASS_PUNPCKLWD_DEFINED XED_ICLASS_PUSH2P_DEFINED XED_ICLASS_PUSH2_DEFINED XED_ICLASS_PUSHAD_DEFINED XED_ICLASS_PUSHA_DEFINED XED_ICLASS_PUSHFD_DEFINED XED_ICLASS_PUSHFQ_DEFINED XED_ICLASS_PUSHF_DEFINED XED_ICLASS_PUSHP_DEFINED XED_ICLASS_PUSH_DEFINED XED_ICLASS_PVALIDATE_DEFINED XED_ICLASS_PXOR_DEFINED XED_ICLASS_RCL_DEFINED XED_ICLASS_RCPPS_DEFINED XED_ICLASS_RCPSS_DEFINED XED_ICLASS_RCR_DEFINED XED_ICLASS_RDFSBASE_DEFINED XED_ICLASS_RDGSBASE_DEFINED XED_ICLASS_RDMSRLIST_DEFINED XED_ICLASS_RDMSR_DEFINED XED_ICLASS_RDPID_DEFINED XED_ICLASS_RDPKRU_DEFINED XED_ICLASS_RDPMC_DEFINED XED_ICLASS_RDPRU_DEFINED XED_ICLASS_RDRAND_DEFINED XED_ICLASS_RDSEED_DEFINED XED_ICLASS_RDSSPD_DEFINED XED_ICLASS_RDSSPQ_DEFINED XED_ICLASS_RDTSCP_DEFINED XED_ICLASS_RDTSC_DEFINED XED_ICLASS_REPE_CMPSB_DEFINED XED_ICLASS_REPE_CMPSD_DEFINED XED_ICLASS_REPE_CMPSQ_DEFINED XED_ICLASS_REPE_CMPSW_DEFINED XED_ICLASS_REPE_SCASB_DEFINED XED_ICLASS_REPE_SCASD_DEFINED XED_ICLASS_REPE_SCASQ_DEFINED XED_ICLASS_REPE_SCASW_DEFINED XED_ICLASS_REPNE_CMPSB_DEFINED XED_ICLASS_REPNE_CMPSD_DEFINED XED_ICLASS_REPNE_CMPSQ_DEFINED XED_ICLASS_REPNE_CMPSW_DEFINED XED_ICLASS_REPNE_SCASB_DEFINED XED_ICLASS_REPNE_SCASD_DEFINED XED_ICLASS_REPNE_SCASQ_DEFINED XED_ICLASS_REPNE_SCASW_DEFINED XED_ICLASS_REP_INSB_DEFINED XED_ICLASS_REP_INSD_DEFINED XED_ICLASS_REP_INSW_DEFINED XED_ICLASS_REP_LODSB_DEFINED XED_ICLASS_REP_LODSD_DEFINED XED_ICLASS_REP_LODSQ_DEFINED XED_ICLASS_REP_LODSW_DEFINED XED_ICLASS_REP_MONTMUL_DEFINED XED_ICLASS_REP_MOVSB_DEFINED XED_ICLASS_REP_MOVSD_DEFINED XED_ICLASS_REP_MOVSQ_DEFINED XED_ICLASS_REP_MOVSW_DEFINED XED_ICLASS_REP_OUTSB_DEFINED XED_ICLASS_REP_OUTSD_DEFINED XED_ICLASS_REP_OUTSW_DEFINED XED_ICLASS_REP_STOSB_DEFINED XED_ICLASS_REP_STOSD_DEFINED XED_ICLASS_REP_STOSQ_DEFINED XED_ICLASS_REP_STOSW_DEFINED XED_ICLASS_REP_XCRYPTCBC_DEFINED XED_ICLASS_REP_XCRYPTCFB_DEFINED XED_ICLASS_REP_XCRYPTCTR_DEFINED XED_ICLASS_REP_XCRYPTECB_DEFINED XED_ICLASS_REP_XCRYPTOFB_DEFINED XED_ICLASS_REP_XSHA1_DEFINED XED_ICLASS_REP_XSHA256_DEFINED XED_ICLASS_REP_XSTORE_DEFINED XED_ICLASS_RET_FAR_DEFINED XED_ICLASS_RET_NEAR_DEFINED XED_ICLASS_RMPADJUST_DEFINED XED_ICLASS_RMPUPDATE_DEFINED XED_ICLASS_ROL_DEFINED XED_ICLASS_RORX_DEFINED XED_ICLASS_ROR_DEFINED XED_ICLASS_ROUNDPD_DEFINED XED_ICLASS_ROUNDPS_DEFINED XED_ICLASS_ROUNDSD_DEFINED XED_ICLASS_ROUNDSS_DEFINED XED_ICLASS_RSM_DEFINED XED_ICLASS_RSQRTPS_DEFINED XED_ICLASS_RSQRTSS_DEFINED XED_ICLASS_RSTORSSP_DEFINED XED_ICLASS_SAHF_DEFINED XED_ICLASS_SALC_DEFINED XED_ICLASS_SARX_DEFINED XED_ICLASS_SAR_DEFINED XED_ICLASS_SAVEPREVSSP_DEFINED XED_ICLASS_SBB_DEFINED XED_ICLASS_SBB_LOCK_DEFINED XED_ICLASS_SCASB_DEFINED XED_ICLASS_SCASD_DEFINED XED_ICLASS_SCASQ_DEFINED XED_ICLASS_SCASW_DEFINED XED_ICLASS_SEAMCALL_DEFINED XED_ICLASS_SEAMOPS_DEFINED XED_ICLASS_SEAMRET_DEFINED XED_ICLASS_SENDUIPI_DEFINED XED_ICLASS_SERIALIZE_DEFINED XED_ICLASS_SETBE_DEFINED XED_ICLASS_SETB_DEFINED XED_ICLASS_SETLE_DEFINED XED_ICLASS_SETL_DEFINED XED_ICLASS_SETNBE_DEFINED XED_ICLASS_SETNB_DEFINED XED_ICLASS_SETNLE_DEFINED XED_ICLASS_SETNL_DEFINED XED_ICLASS_SETNO_DEFINED XED_ICLASS_SETNP_DEFINED XED_ICLASS_SETNS_DEFINED XED_ICLASS_SETNZ_DEFINED XED_ICLASS_SETO_DEFINED XED_ICLASS_SETP_DEFINED XED_ICLASS_SETSSBSY_DEFINED XED_ICLASS_SETS_DEFINED XED_ICLASS_SETZ_DEFINED XED_ICLASS_SFENCE_DEFINED XED_ICLASS_SGDT_DEFINED XED_ICLASS_SHA1MSG1_DEFINED XED_ICLASS_SHA1MSG2_DEFINED XED_ICLASS_SHA1NEXTE_DEFINED XED_ICLASS_SHA1RNDS4_DEFINED XED_ICLASS_SHA256MSG1_DEFINED XED_ICLASS_SHA256MSG2_DEFINED XED_ICLASS_SHA256RNDS2_DEFINED XED_ICLASS_SHLD_DEFINED XED_ICLASS_SHLX_DEFINED XED_ICLASS_SHL_DEFINED XED_ICLASS_SHRD_DEFINED XED_ICLASS_SHRX_DEFINED XED_ICLASS_SHR_DEFINED XED_ICLASS_SHUFPD_DEFINED XED_ICLASS_SHUFPS_DEFINED XED_ICLASS_SIDT_DEFINED XED_ICLASS_SKINIT_DEFINED XED_ICLASS_SLDT_DEFINED XED_ICLASS_SLWPCB_DEFINED XED_ICLASS_SMSW_DEFINED XED_ICLASS_SQRTPD_DEFINED XED_ICLASS_SQRTPS_DEFINED XED_ICLASS_SQRTSD_DEFINED XED_ICLASS_SQRTSS_DEFINED XED_ICLASS_STAC_DEFINED XED_ICLASS_STC_DEFINED XED_ICLASS_STD_DEFINED XED_ICLASS_STGI_DEFINED XED_ICLASS_STI_DEFINED XED_ICLASS_STMXCSR_DEFINED XED_ICLASS_STOSB_DEFINED XED_ICLASS_STOSD_DEFINED XED_ICLASS_STOSQ_DEFINED XED_ICLASS_STOSW_DEFINED XED_ICLASS_STR_DEFINED XED_ICLASS_STTILECFG_DEFINED XED_ICLASS_STUI_DEFINED XED_ICLASS_SUBPD_DEFINED XED_ICLASS_SUBPS_DEFINED XED_ICLASS_SUBSD_DEFINED XED_ICLASS_SUBSS_DEFINED XED_ICLASS_SUB_DEFINED XED_ICLASS_SUB_LOCK_DEFINED XED_ICLASS_SWAPGS_DEFINED XED_ICLASS_SYSCALL_AMD_DEFINED XED_ICLASS_SYSCALL_DEFINED XED_ICLASS_SYSENTER_DEFINED XED_ICLASS_SYSEXIT_DEFINED XED_ICLASS_SYSRET64_DEFINED XED_ICLASS_SYSRET_AMD_DEFINED XED_ICLASS_SYSRET_DEFINED XED_ICLASS_T1MSKC_DEFINED XED_ICLASS_TCMMIMFP16PS_DEFINED XED_ICLASS_TCMMRLFP16PS_DEFINED XED_ICLASS_TDCALL_DEFINED XED_ICLASS_TDPBF16PS_DEFINED XED_ICLASS_TDPBSSD_DEFINED XED_ICLASS_TDPBSUD_DEFINED XED_ICLASS_TDPBUSD_DEFINED XED_ICLASS_TDPBUUD_DEFINED XED_ICLASS_TDPFP16PS_DEFINED XED_ICLASS_TESTUI_DEFINED XED_ICLASS_TEST_DEFINED XED_ICLASS_TILELOADDT1_DEFINED XED_ICLASS_TILELOADD_DEFINED XED_ICLASS_TILERELEASE_DEFINED XED_ICLASS_TILESTORED_DEFINED XED_ICLASS_TILEZERO_DEFINED XED_ICLASS_TLBSYNC_DEFINED XED_ICLASS_TPAUSE_DEFINED XED_ICLASS_TZCNT_DEFINED XED_ICLASS_TZMSK_DEFINED XED_ICLASS_UCOMISD_DEFINED XED_ICLASS_UCOMISS_DEFINED XED_ICLASS_UD0_DEFINED XED_ICLASS_UD1_DEFINED XED_ICLASS_UD2_DEFINED XED_ICLASS_UIRET_DEFINED XED_ICLASS_UMONITOR_DEFINED XED_ICLASS_UMWAIT_DEFINED XED_ICLASS_UNPCKHPD_DEFINED XED_ICLASS_UNPCKHPS_DEFINED XED_ICLASS_UNPCKLPD_DEFINED XED_ICLASS_UNPCKLPS_DEFINED XED_ICLASS_URDMSR_DEFINED XED_ICLASS_UWRMSR_DEFINED XED_ICLASS_V4FMADDPS_DEFINED XED_ICLASS_V4FMADDSS_DEFINED XED_ICLASS_V4FNMADDPS_DEFINED XED_ICLASS_V4FNMADDSS_DEFINED XED_ICLASS_VADDPD_DEFINED XED_ICLASS_VADDPH_DEFINED XED_ICLASS_VADDPS_DEFINED XED_ICLASS_VADDSD_DEFINED XED_ICLASS_VADDSH_DEFINED XED_ICLASS_VADDSS_DEFINED XED_ICLASS_VADDSUBPD_DEFINED XED_ICLASS_VADDSUBPS_DEFINED XED_ICLASS_VAESDECLAST_DEFINED XED_ICLASS_VAESDEC_DEFINED XED_ICLASS_VAESENCLAST_DEFINED XED_ICLASS_VAESENC_DEFINED XED_ICLASS_VAESIMC_DEFINED XED_ICLASS_VAESKEYGENASSIST_DEFINED XED_ICLASS_VALIGND_DEFINED XED_ICLASS_VALIGNQ_DEFINED XED_ICLASS_VANDNPD_DEFINED XED_ICLASS_VANDNPS_DEFINED XED_ICLASS_VANDPD_DEFINED XED_ICLASS_VANDPS_DEFINED XED_ICLASS_VBCSTNEBF162PS_DEFINED XED_ICLASS_VBCSTNESH2PS_DEFINED XED_ICLASS_VBLENDMPD_DEFINED XED_ICLASS_VBLENDMPS_DEFINED XED_ICLASS_VBLENDPD_DEFINED XED_ICLASS_VBLENDPS_DEFINED XED_ICLASS_VBLENDVPD_DEFINED XED_ICLASS_VBLENDVPS_DEFINED XED_ICLASS_VBROADCASTF32X2_DEFINED XED_ICLASS_VBROADCASTF32X4_DEFINED XED_ICLASS_VBROADCASTF32X8_DEFINED XED_ICLASS_VBROADCASTF64X2_DEFINED XED_ICLASS_VBROADCASTF64X4_DEFINED XED_ICLASS_VBROADCASTF128_DEFINED XED_ICLASS_VBROADCASTI32X2_DEFINED XED_ICLASS_VBROADCASTI32X4_DEFINED XED_ICLASS_VBROADCASTI32X8_DEFINED XED_ICLASS_VBROADCASTI64X2_DEFINED XED_ICLASS_VBROADCASTI64X4_DEFINED XED_ICLASS_VBROADCASTI128_DEFINED XED_ICLASS_VBROADCASTSD_DEFINED XED_ICLASS_VBROADCASTSS_DEFINED XED_ICLASS_VCMPPD_DEFINED XED_ICLASS_VCMPPH_DEFINED XED_ICLASS_VCMPPS_DEFINED XED_ICLASS_VCMPSD_DEFINED XED_ICLASS_VCMPSH_DEFINED XED_ICLASS_VCMPSS_DEFINED XED_ICLASS_VCOMISD_DEFINED XED_ICLASS_VCOMISH_DEFINED XED_ICLASS_VCOMISS_DEFINED XED_ICLASS_VCOMPRESSPD_DEFINED XED_ICLASS_VCOMPRESSPS_DEFINED XED_ICLASS_VCVTDQ2PD_DEFINED XED_ICLASS_VCVTDQ2PH_DEFINED XED_ICLASS_VCVTDQ2PS_DEFINED XED_ICLASS_VCVTNE2PS2BF16_DEFINED XED_ICLASS_VCVTNEEBF162PS_DEFINED XED_ICLASS_VCVTNEEPH2PS_DEFINED XED_ICLASS_VCVTNEOBF162PS_DEFINED XED_ICLASS_VCVTNEOPH2PS_DEFINED XED_ICLASS_VCVTNEPS2BF16_DEFINED XED_ICLASS_VCVTPD2DQ_DEFINED XED_ICLASS_VCVTPD2PH_DEFINED XED_ICLASS_VCVTPD2PS_DEFINED XED_ICLASS_VCVTPD2QQ_DEFINED XED_ICLASS_VCVTPD2UDQ_DEFINED XED_ICLASS_VCVTPD2UQQ_DEFINED XED_ICLASS_VCVTPH2DQ_DEFINED XED_ICLASS_VCVTPH2PD_DEFINED XED_ICLASS_VCVTPH2PSX_DEFINED XED_ICLASS_VCVTPH2PS_DEFINED XED_ICLASS_VCVTPH2QQ_DEFINED XED_ICLASS_VCVTPH2UDQ_DEFINED XED_ICLASS_VCVTPH2UQQ_DEFINED XED_ICLASS_VCVTPH2UW_DEFINED XED_ICLASS_VCVTPH2W_DEFINED XED_ICLASS_VCVTPS2DQ_DEFINED XED_ICLASS_VCVTPS2PD_DEFINED XED_ICLASS_VCVTPS2PHX_DEFINED XED_ICLASS_VCVTPS2PH_DEFINED XED_ICLASS_VCVTPS2QQ_DEFINED XED_ICLASS_VCVTPS2UDQ_DEFINED XED_ICLASS_VCVTPS2UQQ_DEFINED XED_ICLASS_VCVTQQ2PD_DEFINED XED_ICLASS_VCVTQQ2PH_DEFINED XED_ICLASS_VCVTQQ2PS_DEFINED XED_ICLASS_VCVTSD2SH_DEFINED XED_ICLASS_VCVTSD2SI_DEFINED XED_ICLASS_VCVTSD2SS_DEFINED XED_ICLASS_VCVTSD2USI_DEFINED XED_ICLASS_VCVTSH2SD_DEFINED XED_ICLASS_VCVTSH2SI_DEFINED XED_ICLASS_VCVTSH2SS_DEFINED XED_ICLASS_VCVTSH2USI_DEFINED XED_ICLASS_VCVTSI2SD_DEFINED XED_ICLASS_VCVTSI2SH_DEFINED XED_ICLASS_VCVTSI2SS_DEFINED XED_ICLASS_VCVTSS2SD_DEFINED XED_ICLASS_VCVTSS2SH_DEFINED XED_ICLASS_VCVTSS2SI_DEFINED XED_ICLASS_VCVTSS2USI_DEFINED XED_ICLASS_VCVTTPD2DQ_DEFINED XED_ICLASS_VCVTTPD2QQ_DEFINED XED_ICLASS_VCVTTPD2UDQ_DEFINED XED_ICLASS_VCVTTPD2UQQ_DEFINED XED_ICLASS_VCVTTPH2DQ_DEFINED XED_ICLASS_VCVTTPH2QQ_DEFINED XED_ICLASS_VCVTTPH2UDQ_DEFINED XED_ICLASS_VCVTTPH2UQQ_DEFINED XED_ICLASS_VCVTTPH2UW_DEFINED XED_ICLASS_VCVTTPH2W_DEFINED XED_ICLASS_VCVTTPS2DQ_DEFINED XED_ICLASS_VCVTTPS2QQ_DEFINED XED_ICLASS_VCVTTPS2UDQ_DEFINED XED_ICLASS_VCVTTPS2UQQ_DEFINED XED_ICLASS_VCVTTSD2SI_DEFINED XED_ICLASS_VCVTTSD2USI_DEFINED XED_ICLASS_VCVTTSH2SI_DEFINED XED_ICLASS_VCVTTSH2USI_DEFINED XED_ICLASS_VCVTTSS2SI_DEFINED XED_ICLASS_VCVTTSS2USI_DEFINED XED_ICLASS_VCVTUDQ2PD_DEFINED XED_ICLASS_VCVTUDQ2PH_DEFINED XED_ICLASS_VCVTUDQ2PS_DEFINED XED_ICLASS_VCVTUQQ2PD_DEFINED XED_ICLASS_VCVTUQQ2PH_DEFINED XED_ICLASS_VCVTUQQ2PS_DEFINED XED_ICLASS_VCVTUSI2SD_DEFINED XED_ICLASS_VCVTUSI2SH_DEFINED XED_ICLASS_VCVTUSI2SS_DEFINED XED_ICLASS_VCVTUW2PH_DEFINED XED_ICLASS_VCVTW2PH_DEFINED XED_ICLASS_VDBPSADBW_DEFINED XED_ICLASS_VDIVPD_DEFINED XED_ICLASS_VDIVPH_DEFINED XED_ICLASS_VDIVPS_DEFINED XED_ICLASS_VDIVSD_DEFINED XED_ICLASS_VDIVSH_DEFINED XED_ICLASS_VDIVSS_DEFINED XED_ICLASS_VDPBF16PS_DEFINED XED_ICLASS_VDPPD_DEFINED XED_ICLASS_VDPPS_DEFINED XED_ICLASS_VERR_DEFINED XED_ICLASS_VERW_DEFINED XED_ICLASS_VEXP2PD_DEFINED XED_ICLASS_VEXP2PS_DEFINED XED_ICLASS_VEXPANDPD_DEFINED XED_ICLASS_VEXPANDPS_DEFINED XED_ICLASS_VEXTRACTF32X4_DEFINED XED_ICLASS_VEXTRACTF32X8_DEFINED XED_ICLASS_VEXTRACTF64X2_DEFINED XED_ICLASS_VEXTRACTF64X4_DEFINED XED_ICLASS_VEXTRACTF128_DEFINED XED_ICLASS_VEXTRACTI32X4_DEFINED XED_ICLASS_VEXTRACTI32X8_DEFINED XED_ICLASS_VEXTRACTI64X2_DEFINED XED_ICLASS_VEXTRACTI64X4_DEFINED XED_ICLASS_VEXTRACTI128_DEFINED XED_ICLASS_VEXTRACTPS_DEFINED XED_ICLASS_VFCMADDCPH_DEFINED XED_ICLASS_VFCMADDCSH_DEFINED XED_ICLASS_VFCMULCPH_DEFINED XED_ICLASS_VFCMULCSH_DEFINED XED_ICLASS_VFIXUPIMMPD_DEFINED XED_ICLASS_VFIXUPIMMPS_DEFINED XED_ICLASS_VFIXUPIMMSD_DEFINED XED_ICLASS_VFIXUPIMMSS_DEFINED XED_ICLASS_VFMADD132PD_DEFINED XED_ICLASS_VFMADD132PH_DEFINED XED_ICLASS_VFMADD132PS_DEFINED XED_ICLASS_VFMADD132SD_DEFINED XED_ICLASS_VFMADD132SH_DEFINED XED_ICLASS_VFMADD132SS_DEFINED XED_ICLASS_VFMADD213PD_DEFINED XED_ICLASS_VFMADD213PH_DEFINED XED_ICLASS_VFMADD213PS_DEFINED XED_ICLASS_VFMADD213SD_DEFINED XED_ICLASS_VFMADD213SH_DEFINED XED_ICLASS_VFMADD213SS_DEFINED XED_ICLASS_VFMADD231PD_DEFINED XED_ICLASS_VFMADD231PH_DEFINED XED_ICLASS_VFMADD231PS_DEFINED XED_ICLASS_VFMADD231SD_DEFINED XED_ICLASS_VFMADD231SH_DEFINED XED_ICLASS_VFMADD231SS_DEFINED XED_ICLASS_VFMADDCPH_DEFINED XED_ICLASS_VFMADDCSH_DEFINED XED_ICLASS_VFMADDPD_DEFINED XED_ICLASS_VFMADDPS_DEFINED XED_ICLASS_VFMADDSD_DEFINED XED_ICLASS_VFMADDSS_DEFINED XED_ICLASS_VFMADDSUB132PD_DEFINED XED_ICLASS_VFMADDSUB132PH_DEFINED XED_ICLASS_VFMADDSUB132PS_DEFINED XED_ICLASS_VFMADDSUB213PD_DEFINED XED_ICLASS_VFMADDSUB213PH_DEFINED XED_ICLASS_VFMADDSUB213PS_DEFINED XED_ICLASS_VFMADDSUB231PD_DEFINED XED_ICLASS_VFMADDSUB231PH_DEFINED XED_ICLASS_VFMADDSUB231PS_DEFINED XED_ICLASS_VFMADDSUBPD_DEFINED XED_ICLASS_VFMADDSUBPS_DEFINED XED_ICLASS_VFMSUB132PD_DEFINED XED_ICLASS_VFMSUB132PH_DEFINED XED_ICLASS_VFMSUB132PS_DEFINED XED_ICLASS_VFMSUB132SD_DEFINED XED_ICLASS_VFMSUB132SH_DEFINED XED_ICLASS_VFMSUB132SS_DEFINED XED_ICLASS_VFMSUB213PD_DEFINED XED_ICLASS_VFMSUB213PH_DEFINED XED_ICLASS_VFMSUB213PS_DEFINED XED_ICLASS_VFMSUB213SD_DEFINED XED_ICLASS_VFMSUB213SH_DEFINED XED_ICLASS_VFMSUB213SS_DEFINED XED_ICLASS_VFMSUB231PD_DEFINED XED_ICLASS_VFMSUB231PH_DEFINED XED_ICLASS_VFMSUB231PS_DEFINED XED_ICLASS_VFMSUB231SD_DEFINED XED_ICLASS_VFMSUB231SH_DEFINED XED_ICLASS_VFMSUB231SS_DEFINED XED_ICLASS_VFMSUBADD132PD_DEFINED XED_ICLASS_VFMSUBADD132PH_DEFINED XED_ICLASS_VFMSUBADD132PS_DEFINED XED_ICLASS_VFMSUBADD213PD_DEFINED XED_ICLASS_VFMSUBADD213PH_DEFINED XED_ICLASS_VFMSUBADD213PS_DEFINED XED_ICLASS_VFMSUBADD231PD_DEFINED XED_ICLASS_VFMSUBADD231PH_DEFINED XED_ICLASS_VFMSUBADD231PS_DEFINED XED_ICLASS_VFMSUBADDPD_DEFINED XED_ICLASS_VFMSUBADDPS_DEFINED XED_ICLASS_VFMSUBPD_DEFINED XED_ICLASS_VFMSUBPS_DEFINED XED_ICLASS_VFMSUBSD_DEFINED XED_ICLASS_VFMSUBSS_DEFINED XED_ICLASS_VFMULCPH_DEFINED XED_ICLASS_VFMULCSH_DEFINED XED_ICLASS_VFNMADD132PD_DEFINED XED_ICLASS_VFNMADD132PH_DEFINED XED_ICLASS_VFNMADD132PS_DEFINED XED_ICLASS_VFNMADD132SD_DEFINED XED_ICLASS_VFNMADD132SH_DEFINED XED_ICLASS_VFNMADD132SS_DEFINED XED_ICLASS_VFNMADD213PD_DEFINED XED_ICLASS_VFNMADD213PH_DEFINED XED_ICLASS_VFNMADD213PS_DEFINED XED_ICLASS_VFNMADD213SD_DEFINED XED_ICLASS_VFNMADD213SH_DEFINED XED_ICLASS_VFNMADD213SS_DEFINED XED_ICLASS_VFNMADD231PD_DEFINED XED_ICLASS_VFNMADD231PH_DEFINED XED_ICLASS_VFNMADD231PS_DEFINED XED_ICLASS_VFNMADD231SD_DEFINED XED_ICLASS_VFNMADD231SH_DEFINED XED_ICLASS_VFNMADD231SS_DEFINED XED_ICLASS_VFNMADDPD_DEFINED XED_ICLASS_VFNMADDPS_DEFINED XED_ICLASS_VFNMADDSD_DEFINED XED_ICLASS_VFNMADDSS_DEFINED XED_ICLASS_VFNMSUB132PD_DEFINED XED_ICLASS_VFNMSUB132PH_DEFINED XED_ICLASS_VFNMSUB132PS_DEFINED XED_ICLASS_VFNMSUB132SD_DEFINED XED_ICLASS_VFNMSUB132SH_DEFINED XED_ICLASS_VFNMSUB132SS_DEFINED XED_ICLASS_VFNMSUB213PD_DEFINED XED_ICLASS_VFNMSUB213PH_DEFINED XED_ICLASS_VFNMSUB213PS_DEFINED XED_ICLASS_VFNMSUB213SD_DEFINED XED_ICLASS_VFNMSUB213SH_DEFINED XED_ICLASS_VFNMSUB213SS_DEFINED XED_ICLASS_VFNMSUB231PD_DEFINED XED_ICLASS_VFNMSUB231PH_DEFINED XED_ICLASS_VFNMSUB231PS_DEFINED XED_ICLASS_VFNMSUB231SD_DEFINED XED_ICLASS_VFNMSUB231SH_DEFINED XED_ICLASS_VFNMSUB231SS_DEFINED XED_ICLASS_VFNMSUBPD_DEFINED XED_ICLASS_VFNMSUBPS_DEFINED XED_ICLASS_VFNMSUBSD_DEFINED XED_ICLASS_VFNMSUBSS_DEFINED XED_ICLASS_VFPCLASSPD_DEFINED XED_ICLASS_VFPCLASSPH_DEFINED XED_ICLASS_VFPCLASSPS_DEFINED XED_ICLASS_VFPCLASSSD_DEFINED XED_ICLASS_VFPCLASSSH_DEFINED XED_ICLASS_VFPCLASSSS_DEFINED XED_ICLASS_VFRCZPD_DEFINED XED_ICLASS_VFRCZPS_DEFINED XED_ICLASS_VFRCZSD_DEFINED XED_ICLASS_VFRCZSS_DEFINED XED_ICLASS_VGATHERDPD_DEFINED XED_ICLASS_VGATHERDPS_DEFINED XED_ICLASS_VGATHERPF0DPD_DEFINED XED_ICLASS_VGATHERPF0DPS_DEFINED XED_ICLASS_VGATHERPF0QPD_DEFINED XED_ICLASS_VGATHERPF0QPS_DEFINED XED_ICLASS_VGATHERPF1DPD_DEFINED XED_ICLASS_VGATHERPF1DPS_DEFINED XED_ICLASS_VGATHERPF1QPD_DEFINED XED_ICLASS_VGATHERPF1QPS_DEFINED XED_ICLASS_VGATHERQPD_DEFINED XED_ICLASS_VGATHERQPS_DEFINED XED_ICLASS_VGETEXPPD_DEFINED XED_ICLASS_VGETEXPPH_DEFINED XED_ICLASS_VGETEXPPS_DEFINED XED_ICLASS_VGETEXPSD_DEFINED XED_ICLASS_VGETEXPSH_DEFINED XED_ICLASS_VGETEXPSS_DEFINED XED_ICLASS_VGETMANTPD_DEFINED XED_ICLASS_VGETMANTPH_DEFINED XED_ICLASS_VGETMANTPS_DEFINED XED_ICLASS_VGETMANTSD_DEFINED XED_ICLASS_VGETMANTSH_DEFINED XED_ICLASS_VGETMANTSS_DEFINED XED_ICLASS_VGF2P8AFFINEINVQB_DEFINED XED_ICLASS_VGF2P8AFFINEQB_DEFINED XED_ICLASS_VGF2P8MULB_DEFINED XED_ICLASS_VHADDPD_DEFINED XED_ICLASS_VHADDPS_DEFINED XED_ICLASS_VHSUBPD_DEFINED XED_ICLASS_VHSUBPS_DEFINED XED_ICLASS_VINSERTF32X4_DEFINED XED_ICLASS_VINSERTF32X8_DEFINED XED_ICLASS_VINSERTF64X2_DEFINED XED_ICLASS_VINSERTF64X4_DEFINED XED_ICLASS_VINSERTF128_DEFINED XED_ICLASS_VINSERTI32X4_DEFINED XED_ICLASS_VINSERTI32X8_DEFINED XED_ICLASS_VINSERTI64X2_DEFINED XED_ICLASS_VINSERTI64X4_DEFINED XED_ICLASS_VINSERTI128_DEFINED XED_ICLASS_VINSERTPS_DEFINED XED_ICLASS_VLDDQU_DEFINED XED_ICLASS_VLDMXCSR_DEFINED XED_ICLASS_VMASKMOVDQU_DEFINED XED_ICLASS_VMASKMOVPD_DEFINED XED_ICLASS_VMASKMOVPS_DEFINED XED_ICLASS_VMAXPD_DEFINED XED_ICLASS_VMAXPH_DEFINED XED_ICLASS_VMAXPS_DEFINED XED_ICLASS_VMAXSD_DEFINED XED_ICLASS_VMAXSH_DEFINED XED_ICLASS_VMAXSS_DEFINED XED_ICLASS_VMCALL_DEFINED XED_ICLASS_VMCLEAR_DEFINED XED_ICLASS_VMFUNC_DEFINED XED_ICLASS_VMINPD_DEFINED XED_ICLASS_VMINPH_DEFINED XED_ICLASS_VMINPS_DEFINED XED_ICLASS_VMINSD_DEFINED XED_ICLASS_VMINSH_DEFINED XED_ICLASS_VMINSS_DEFINED XED_ICLASS_VMLAUNCH_DEFINED XED_ICLASS_VMLOAD_DEFINED XED_ICLASS_VMMCALL_DEFINED XED_ICLASS_VMOVAPD_DEFINED XED_ICLASS_VMOVAPS_DEFINED XED_ICLASS_VMOVDDUP_DEFINED XED_ICLASS_VMOVDQA32_DEFINED XED_ICLASS_VMOVDQA64_DEFINED XED_ICLASS_VMOVDQA_DEFINED XED_ICLASS_VMOVDQU8_DEFINED XED_ICLASS_VMOVDQU16_DEFINED XED_ICLASS_VMOVDQU32_DEFINED XED_ICLASS_VMOVDQU64_DEFINED XED_ICLASS_VMOVDQU_DEFINED XED_ICLASS_VMOVD_DEFINED XED_ICLASS_VMOVHLPS_DEFINED XED_ICLASS_VMOVHPD_DEFINED XED_ICLASS_VMOVHPS_DEFINED XED_ICLASS_VMOVLHPS_DEFINED XED_ICLASS_VMOVLPD_DEFINED XED_ICLASS_VMOVLPS_DEFINED XED_ICLASS_VMOVMSKPD_DEFINED XED_ICLASS_VMOVMSKPS_DEFINED XED_ICLASS_VMOVNTDQA_DEFINED XED_ICLASS_VMOVNTDQ_DEFINED XED_ICLASS_VMOVNTPD_DEFINED XED_ICLASS_VMOVNTPS_DEFINED XED_ICLASS_VMOVQ_DEFINED XED_ICLASS_VMOVSD_DEFINED XED_ICLASS_VMOVSHDUP_DEFINED XED_ICLASS_VMOVSH_DEFINED XED_ICLASS_VMOVSLDUP_DEFINED XED_ICLASS_VMOVSS_DEFINED XED_ICLASS_VMOVUPD_DEFINED XED_ICLASS_VMOVUPS_DEFINED XED_ICLASS_VMOVW_DEFINED XED_ICLASS_VMPSADBW_DEFINED XED_ICLASS_VMPTRLD_DEFINED XED_ICLASS_VMPTRST_DEFINED XED_ICLASS_VMREAD_DEFINED XED_ICLASS_VMRESUME_DEFINED XED_ICLASS_VMRUN_DEFINED XED_ICLASS_VMSAVE_DEFINED XED_ICLASS_VMULPD_DEFINED XED_ICLASS_VMULPH_DEFINED XED_ICLASS_VMULPS_DEFINED XED_ICLASS_VMULSD_DEFINED XED_ICLASS_VMULSH_DEFINED XED_ICLASS_VMULSS_DEFINED XED_ICLASS_VMWRITE_DEFINED XED_ICLASS_VMXOFF_DEFINED XED_ICLASS_VMXON_DEFINED XED_ICLASS_VORPD_DEFINED XED_ICLASS_VORPS_DEFINED XED_ICLASS_VP2INTERSECTD_DEFINED XED_ICLASS_VP2INTERSECTQ_DEFINED XED_ICLASS_VP4DPWSSDS_DEFINED XED_ICLASS_VP4DPWSSD_DEFINED XED_ICLASS_VPABSB_DEFINED XED_ICLASS_VPABSD_DEFINED XED_ICLASS_VPABSQ_DEFINED XED_ICLASS_VPABSW_DEFINED XED_ICLASS_VPACKSSDW_DEFINED XED_ICLASS_VPACKSSWB_DEFINED XED_ICLASS_VPACKUSDW_DEFINED XED_ICLASS_VPACKUSWB_DEFINED XED_ICLASS_VPADDB_DEFINED XED_ICLASS_VPADDD_DEFINED XED_ICLASS_VPADDQ_DEFINED XED_ICLASS_VPADDSB_DEFINED XED_ICLASS_VPADDSW_DEFINED XED_ICLASS_VPADDUSB_DEFINED XED_ICLASS_VPADDUSW_DEFINED XED_ICLASS_VPADDW_DEFINED XED_ICLASS_VPALIGNR_DEFINED XED_ICLASS_VPANDD_DEFINED XED_ICLASS_VPANDND_DEFINED XED_ICLASS_VPANDNQ_DEFINED XED_ICLASS_VPANDN_DEFINED XED_ICLASS_VPANDQ_DEFINED XED_ICLASS_VPAND_DEFINED XED_ICLASS_VPAVGB_DEFINED XED_ICLASS_VPAVGW_DEFINED XED_ICLASS_VPBLENDD_DEFINED XED_ICLASS_VPBLENDMB_DEFINED XED_ICLASS_VPBLENDMD_DEFINED XED_ICLASS_VPBLENDMQ_DEFINED XED_ICLASS_VPBLENDMW_DEFINED XED_ICLASS_VPBLENDVB_DEFINED XED_ICLASS_VPBLENDW_DEFINED XED_ICLASS_VPBROADCASTB_DEFINED XED_ICLASS_VPBROADCASTD_DEFINED XED_ICLASS_VPBROADCASTMB2Q_DEFINED XED_ICLASS_VPBROADCASTMW2D_DEFINED XED_ICLASS_VPBROADCASTQ_DEFINED XED_ICLASS_VPBROADCASTW_DEFINED XED_ICLASS_VPCLMULQDQ_DEFINED XED_ICLASS_VPCMOV_DEFINED XED_ICLASS_VPCMPB_DEFINED XED_ICLASS_VPCMPD_DEFINED XED_ICLASS_VPCMPEQB_DEFINED XED_ICLASS_VPCMPEQD_DEFINED XED_ICLASS_VPCMPEQQ_DEFINED XED_ICLASS_VPCMPEQW_DEFINED XED_ICLASS_VPCMPESTRI64_DEFINED XED_ICLASS_VPCMPESTRI_DEFINED XED_ICLASS_VPCMPESTRM64_DEFINED XED_ICLASS_VPCMPESTRM_DEFINED XED_ICLASS_VPCMPGTB_DEFINED XED_ICLASS_VPCMPGTD_DEFINED XED_ICLASS_VPCMPGTQ_DEFINED XED_ICLASS_VPCMPGTW_DEFINED XED_ICLASS_VPCMPISTRI64_DEFINED XED_ICLASS_VPCMPISTRI_DEFINED XED_ICLASS_VPCMPISTRM_DEFINED XED_ICLASS_VPCMPQ_DEFINED XED_ICLASS_VPCMPUB_DEFINED XED_ICLASS_VPCMPUD_DEFINED XED_ICLASS_VPCMPUQ_DEFINED XED_ICLASS_VPCMPUW_DEFINED XED_ICLASS_VPCMPW_DEFINED XED_ICLASS_VPCOMB_DEFINED XED_ICLASS_VPCOMD_DEFINED XED_ICLASS_VPCOMPRESSB_DEFINED XED_ICLASS_VPCOMPRESSD_DEFINED XED_ICLASS_VPCOMPRESSQ_DEFINED XED_ICLASS_VPCOMPRESSW_DEFINED XED_ICLASS_VPCOMQ_DEFINED XED_ICLASS_VPCOMUB_DEFINED XED_ICLASS_VPCOMUD_DEFINED XED_ICLASS_VPCOMUQ_DEFINED XED_ICLASS_VPCOMUW_DEFINED XED_ICLASS_VPCOMW_DEFINED XED_ICLASS_VPCONFLICTD_DEFINED XED_ICLASS_VPCONFLICTQ_DEFINED XED_ICLASS_VPDPBSSDS_DEFINED XED_ICLASS_VPDPBSSD_DEFINED XED_ICLASS_VPDPBSUDS_DEFINED XED_ICLASS_VPDPBSUD_DEFINED XED_ICLASS_VPDPBUSDS_DEFINED XED_ICLASS_VPDPBUSD_DEFINED XED_ICLASS_VPDPBUUDS_DEFINED XED_ICLASS_VPDPBUUD_DEFINED XED_ICLASS_VPDPWSSDS_DEFINED XED_ICLASS_VPDPWSSD_DEFINED XED_ICLASS_VPDPWSUDS_DEFINED XED_ICLASS_VPDPWSUD_DEFINED XED_ICLASS_VPDPWUSDS_DEFINED XED_ICLASS_VPDPWUSD_DEFINED XED_ICLASS_VPDPWUUDS_DEFINED XED_ICLASS_VPDPWUUD_DEFINED XED_ICLASS_VPERM2F128_DEFINED XED_ICLASS_VPERM2I128_DEFINED XED_ICLASS_VPERMB_DEFINED XED_ICLASS_VPERMD_DEFINED XED_ICLASS_VPERMI2B_DEFINED XED_ICLASS_VPERMI2D_DEFINED XED_ICLASS_VPERMI2PD_DEFINED XED_ICLASS_VPERMI2PS_DEFINED XED_ICLASS_VPERMI2Q_DEFINED XED_ICLASS_VPERMI2W_DEFINED XED_ICLASS_VPERMIL2PD_DEFINED XED_ICLASS_VPERMIL2PS_DEFINED XED_ICLASS_VPERMILPD_DEFINED XED_ICLASS_VPERMILPS_DEFINED XED_ICLASS_VPERMPD_DEFINED XED_ICLASS_VPERMPS_DEFINED XED_ICLASS_VPERMQ_DEFINED XED_ICLASS_VPERMT2B_DEFINED XED_ICLASS_VPERMT2D_DEFINED XED_ICLASS_VPERMT2PD_DEFINED XED_ICLASS_VPERMT2PS_DEFINED XED_ICLASS_VPERMT2Q_DEFINED XED_ICLASS_VPERMT2W_DEFINED XED_ICLASS_VPERMW_DEFINED XED_ICLASS_VPEXPANDB_DEFINED XED_ICLASS_VPEXPANDD_DEFINED XED_ICLASS_VPEXPANDQ_DEFINED XED_ICLASS_VPEXPANDW_DEFINED XED_ICLASS_VPEXTRB_DEFINED XED_ICLASS_VPEXTRD_DEFINED XED_ICLASS_VPEXTRQ_DEFINED XED_ICLASS_VPEXTRW_C5_DEFINED XED_ICLASS_VPEXTRW_DEFINED XED_ICLASS_VPGATHERDD_DEFINED XED_ICLASS_VPGATHERDQ_DEFINED XED_ICLASS_VPGATHERQD_DEFINED XED_ICLASS_VPGATHERQQ_DEFINED XED_ICLASS_VPHADDBD_DEFINED XED_ICLASS_VPHADDBQ_DEFINED XED_ICLASS_VPHADDBW_DEFINED XED_ICLASS_VPHADDDQ_DEFINED XED_ICLASS_VPHADDD_DEFINED XED_ICLASS_VPHADDSW_DEFINED XED_ICLASS_VPHADDUBD_DEFINED XED_ICLASS_VPHADDUBQ_DEFINED XED_ICLASS_VPHADDUBW_DEFINED XED_ICLASS_VPHADDUDQ_DEFINED XED_ICLASS_VPHADDUWD_DEFINED XED_ICLASS_VPHADDUWQ_DEFINED XED_ICLASS_VPHADDWD_DEFINED XED_ICLASS_VPHADDWQ_DEFINED XED_ICLASS_VPHADDW_DEFINED XED_ICLASS_VPHMINPOSUW_DEFINED XED_ICLASS_VPHSUBBW_DEFINED XED_ICLASS_VPHSUBDQ_DEFINED XED_ICLASS_VPHSUBD_DEFINED XED_ICLASS_VPHSUBSW_DEFINED XED_ICLASS_VPHSUBWD_DEFINED XED_ICLASS_VPHSUBW_DEFINED XED_ICLASS_VPINSRB_DEFINED XED_ICLASS_VPINSRD_DEFINED XED_ICLASS_VPINSRQ_DEFINED XED_ICLASS_VPINSRW_DEFINED XED_ICLASS_VPLZCNTD_DEFINED XED_ICLASS_VPLZCNTQ_DEFINED XED_ICLASS_VPMACSDD_DEFINED XED_ICLASS_VPMACSDQH_DEFINED XED_ICLASS_VPMACSDQL_DEFINED XED_ICLASS_VPMACSSDD_DEFINED XED_ICLASS_VPMACSSDQH_DEFINED XED_ICLASS_VPMACSSDQL_DEFINED XED_ICLASS_VPMACSSWD_DEFINED XED_ICLASS_VPMACSSWW_DEFINED XED_ICLASS_VPMACSWD_DEFINED XED_ICLASS_VPMACSWW_DEFINED XED_ICLASS_VPMADCSSWD_DEFINED XED_ICLASS_VPMADCSWD_DEFINED XED_ICLASS_VPMADD52HUQ_DEFINED XED_ICLASS_VPMADD52LUQ_DEFINED XED_ICLASS_VPMADDUBSW_DEFINED XED_ICLASS_VPMADDWD_DEFINED XED_ICLASS_VPMASKMOVD_DEFINED XED_ICLASS_VPMASKMOVQ_DEFINED XED_ICLASS_VPMAXSB_DEFINED XED_ICLASS_VPMAXSD_DEFINED XED_ICLASS_VPMAXSQ_DEFINED XED_ICLASS_VPMAXSW_DEFINED XED_ICLASS_VPMAXUB_DEFINED XED_ICLASS_VPMAXUD_DEFINED XED_ICLASS_VPMAXUQ_DEFINED XED_ICLASS_VPMAXUW_DEFINED XED_ICLASS_VPMINSB_DEFINED XED_ICLASS_VPMINSD_DEFINED XED_ICLASS_VPMINSQ_DEFINED XED_ICLASS_VPMINSW_DEFINED XED_ICLASS_VPMINUB_DEFINED XED_ICLASS_VPMINUD_DEFINED XED_ICLASS_VPMINUQ_DEFINED XED_ICLASS_VPMINUW_DEFINED XED_ICLASS_VPMOVB2M_DEFINED XED_ICLASS_VPMOVD2M_DEFINED XED_ICLASS_VPMOVDB_DEFINED XED_ICLASS_VPMOVDW_DEFINED XED_ICLASS_VPMOVM2B_DEFINED XED_ICLASS_VPMOVM2D_DEFINED XED_ICLASS_VPMOVM2Q_DEFINED XED_ICLASS_VPMOVM2W_DEFINED XED_ICLASS_VPMOVMSKB_DEFINED XED_ICLASS_VPMOVQ2M_DEFINED XED_ICLASS_VPMOVQB_DEFINED XED_ICLASS_VPMOVQD_DEFINED XED_ICLASS_VPMOVQW_DEFINED XED_ICLASS_VPMOVSDB_DEFINED XED_ICLASS_VPMOVSDW_DEFINED XED_ICLASS_VPMOVSQB_DEFINED XED_ICLASS_VPMOVSQD_DEFINED XED_ICLASS_VPMOVSQW_DEFINED XED_ICLASS_VPMOVSWB_DEFINED XED_ICLASS_VPMOVSXBD_DEFINED XED_ICLASS_VPMOVSXBQ_DEFINED XED_ICLASS_VPMOVSXBW_DEFINED XED_ICLASS_VPMOVSXDQ_DEFINED XED_ICLASS_VPMOVSXWD_DEFINED XED_ICLASS_VPMOVSXWQ_DEFINED XED_ICLASS_VPMOVUSDB_DEFINED XED_ICLASS_VPMOVUSDW_DEFINED XED_ICLASS_VPMOVUSQB_DEFINED XED_ICLASS_VPMOVUSQD_DEFINED XED_ICLASS_VPMOVUSQW_DEFINED XED_ICLASS_VPMOVUSWB_DEFINED XED_ICLASS_VPMOVW2M_DEFINED XED_ICLASS_VPMOVWB_DEFINED XED_ICLASS_VPMOVZXBD_DEFINED XED_ICLASS_VPMOVZXBQ_DEFINED XED_ICLASS_VPMOVZXBW_DEFINED XED_ICLASS_VPMOVZXDQ_DEFINED XED_ICLASS_VPMOVZXWD_DEFINED XED_ICLASS_VPMOVZXWQ_DEFINED XED_ICLASS_VPMULDQ_DEFINED XED_ICLASS_VPMULHRSW_DEFINED XED_ICLASS_VPMULHUW_DEFINED XED_ICLASS_VPMULHW_DEFINED XED_ICLASS_VPMULLD_DEFINED XED_ICLASS_VPMULLQ_DEFINED XED_ICLASS_VPMULLW_DEFINED XED_ICLASS_VPMULTISHIFTQB_DEFINED XED_ICLASS_VPMULUDQ_DEFINED XED_ICLASS_VPOPCNTB_DEFINED XED_ICLASS_VPOPCNTD_DEFINED XED_ICLASS_VPOPCNTQ_DEFINED XED_ICLASS_VPOPCNTW_DEFINED XED_ICLASS_VPORD_DEFINED XED_ICLASS_VPORQ_DEFINED XED_ICLASS_VPOR_DEFINED XED_ICLASS_VPPERM_DEFINED XED_ICLASS_VPROLD_DEFINED XED_ICLASS_VPROLQ_DEFINED XED_ICLASS_VPROLVD_DEFINED XED_ICLASS_VPROLVQ_DEFINED XED_ICLASS_VPRORD_DEFINED XED_ICLASS_VPRORQ_DEFINED XED_ICLASS_VPRORVD_DEFINED XED_ICLASS_VPRORVQ_DEFINED XED_ICLASS_VPROTB_DEFINED XED_ICLASS_VPROTD_DEFINED XED_ICLASS_VPROTQ_DEFINED XED_ICLASS_VPROTW_DEFINED XED_ICLASS_VPSADBW_DEFINED XED_ICLASS_VPSCATTERDD_DEFINED XED_ICLASS_VPSCATTERDQ_DEFINED XED_ICLASS_VPSCATTERQD_DEFINED XED_ICLASS_VPSCATTERQQ_DEFINED XED_ICLASS_VPSHAB_DEFINED XED_ICLASS_VPSHAD_DEFINED XED_ICLASS_VPSHAQ_DEFINED XED_ICLASS_VPSHAW_DEFINED XED_ICLASS_VPSHLB_DEFINED XED_ICLASS_VPSHLDD_DEFINED XED_ICLASS_VPSHLDQ_DEFINED XED_ICLASS_VPSHLDVD_DEFINED XED_ICLASS_VPSHLDVQ_DEFINED XED_ICLASS_VPSHLDVW_DEFINED XED_ICLASS_VPSHLDW_DEFINED XED_ICLASS_VPSHLD_DEFINED XED_ICLASS_VPSHLQ_DEFINED XED_ICLASS_VPSHLW_DEFINED XED_ICLASS_VPSHRDD_DEFINED XED_ICLASS_VPSHRDQ_DEFINED XED_ICLASS_VPSHRDVD_DEFINED XED_ICLASS_VPSHRDVQ_DEFINED XED_ICLASS_VPSHRDVW_DEFINED XED_ICLASS_VPSHRDW_DEFINED XED_ICLASS_VPSHUFBITQMB_DEFINED XED_ICLASS_VPSHUFB_DEFINED XED_ICLASS_VPSHUFD_DEFINED XED_ICLASS_VPSHUFHW_DEFINED XED_ICLASS_VPSHUFLW_DEFINED XED_ICLASS_VPSIGNB_DEFINED XED_ICLASS_VPSIGND_DEFINED XED_ICLASS_VPSIGNW_DEFINED XED_ICLASS_VPSLLDQ_DEFINED XED_ICLASS_VPSLLD_DEFINED XED_ICLASS_VPSLLQ_DEFINED XED_ICLASS_VPSLLVD_DEFINED XED_ICLASS_VPSLLVQ_DEFINED XED_ICLASS_VPSLLVW_DEFINED XED_ICLASS_VPSLLW_DEFINED XED_ICLASS_VPSRAD_DEFINED XED_ICLASS_VPSRAQ_DEFINED XED_ICLASS_VPSRAVD_DEFINED XED_ICLASS_VPSRAVQ_DEFINED XED_ICLASS_VPSRAVW_DEFINED XED_ICLASS_VPSRAW_DEFINED XED_ICLASS_VPSRLDQ_DEFINED XED_ICLASS_VPSRLD_DEFINED XED_ICLASS_VPSRLQ_DEFINED XED_ICLASS_VPSRLVD_DEFINED XED_ICLASS_VPSRLVQ_DEFINED XED_ICLASS_VPSRLVW_DEFINED XED_ICLASS_VPSRLW_DEFINED XED_ICLASS_VPSUBB_DEFINED XED_ICLASS_VPSUBD_DEFINED XED_ICLASS_VPSUBQ_DEFINED XED_ICLASS_VPSUBSB_DEFINED XED_ICLASS_VPSUBSW_DEFINED XED_ICLASS_VPSUBUSB_DEFINED XED_ICLASS_VPSUBUSW_DEFINED XED_ICLASS_VPSUBW_DEFINED XED_ICLASS_VPTERNLOGD_DEFINED XED_ICLASS_VPTERNLOGQ_DEFINED XED_ICLASS_VPTESTMB_DEFINED XED_ICLASS_VPTESTMD_DEFINED XED_ICLASS_VPTESTMQ_DEFINED XED_ICLASS_VPTESTMW_DEFINED XED_ICLASS_VPTESTNMB_DEFINED XED_ICLASS_VPTESTNMD_DEFINED XED_ICLASS_VPTESTNMQ_DEFINED XED_ICLASS_VPTESTNMW_DEFINED XED_ICLASS_VPTEST_DEFINED XED_ICLASS_VPUNPCKHBW_DEFINED XED_ICLASS_VPUNPCKHDQ_DEFINED XED_ICLASS_VPUNPCKHQDQ_DEFINED XED_ICLASS_VPUNPCKHWD_DEFINED XED_ICLASS_VPUNPCKLBW_DEFINED XED_ICLASS_VPUNPCKLDQ_DEFINED XED_ICLASS_VPUNPCKLQDQ_DEFINED XED_ICLASS_VPUNPCKLWD_DEFINED XED_ICLASS_VPXORD_DEFINED XED_ICLASS_VPXORQ_DEFINED XED_ICLASS_VPXOR_DEFINED XED_ICLASS_VRANGEPD_DEFINED XED_ICLASS_VRANGEPS_DEFINED XED_ICLASS_VRANGESD_DEFINED XED_ICLASS_VRANGESS_DEFINED XED_ICLASS_VRCP14PD_DEFINED XED_ICLASS_VRCP14PS_DEFINED XED_ICLASS_VRCP14SD_DEFINED XED_ICLASS_VRCP14SS_DEFINED XED_ICLASS_VRCP28PD_DEFINED XED_ICLASS_VRCP28PS_DEFINED XED_ICLASS_VRCP28SD_DEFINED XED_ICLASS_VRCP28SS_DEFINED XED_ICLASS_VRCPPH_DEFINED XED_ICLASS_VRCPPS_DEFINED XED_ICLASS_VRCPSH_DEFINED XED_ICLASS_VRCPSS_DEFINED XED_ICLASS_VREDUCEPD_DEFINED XED_ICLASS_VREDUCEPH_DEFINED XED_ICLASS_VREDUCEPS_DEFINED XED_ICLASS_VREDUCESD_DEFINED XED_ICLASS_VREDUCESH_DEFINED XED_ICLASS_VREDUCESS_DEFINED XED_ICLASS_VRNDSCALEPD_DEFINED XED_ICLASS_VRNDSCALEPH_DEFINED XED_ICLASS_VRNDSCALEPS_DEFINED XED_ICLASS_VRNDSCALESD_DEFINED XED_ICLASS_VRNDSCALESH_DEFINED XED_ICLASS_VRNDSCALESS_DEFINED XED_ICLASS_VROUNDPD_DEFINED XED_ICLASS_VROUNDPS_DEFINED XED_ICLASS_VROUNDSD_DEFINED XED_ICLASS_VROUNDSS_DEFINED XED_ICLASS_VRSQRT14PD_DEFINED XED_ICLASS_VRSQRT14PS_DEFINED XED_ICLASS_VRSQRT14SD_DEFINED XED_ICLASS_VRSQRT14SS_DEFINED XED_ICLASS_VRSQRT28PD_DEFINED XED_ICLASS_VRSQRT28PS_DEFINED XED_ICLASS_VRSQRT28SD_DEFINED XED_ICLASS_VRSQRT28SS_DEFINED XED_ICLASS_VRSQRTPH_DEFINED XED_ICLASS_VRSQRTPS_DEFINED XED_ICLASS_VRSQRTSH_DEFINED XED_ICLASS_VRSQRTSS_DEFINED XED_ICLASS_VSCALEFPD_DEFINED XED_ICLASS_VSCALEFPH_DEFINED XED_ICLASS_VSCALEFPS_DEFINED XED_ICLASS_VSCALEFSD_DEFINED XED_ICLASS_VSCALEFSH_DEFINED XED_ICLASS_VSCALEFSS_DEFINED XED_ICLASS_VSCATTERDPD_DEFINED XED_ICLASS_VSCATTERDPS_DEFINED XED_ICLASS_VSCATTERPF0DPD_DEFINED XED_ICLASS_VSCATTERPF0DPS_DEFINED XED_ICLASS_VSCATTERPF0QPD_DEFINED XED_ICLASS_VSCATTERPF0QPS_DEFINED XED_ICLASS_VSCATTERPF1DPD_DEFINED XED_ICLASS_VSCATTERPF1DPS_DEFINED XED_ICLASS_VSCATTERPF1QPD_DEFINED XED_ICLASS_VSCATTERPF1QPS_DEFINED XED_ICLASS_VSCATTERQPD_DEFINED XED_ICLASS_VSCATTERQPS_DEFINED XED_ICLASS_VSHA512MSG1_DEFINED XED_ICLASS_VSHA512MSG2_DEFINED XED_ICLASS_VSHA512RNDS2_DEFINED XED_ICLASS_VSHUFF32X4_DEFINED XED_ICLASS_VSHUFF64X2_DEFINED XED_ICLASS_VSHUFI32X4_DEFINED XED_ICLASS_VSHUFI64X2_DEFINED XED_ICLASS_VSHUFPD_DEFINED XED_ICLASS_VSHUFPS_DEFINED XED_ICLASS_VSM3MSG1_DEFINED XED_ICLASS_VSM3MSG2_DEFINED XED_ICLASS_VSM3RNDS2_DEFINED XED_ICLASS_VSM4KEY4_DEFINED XED_ICLASS_VSM4RNDS4_DEFINED XED_ICLASS_VSQRTPD_DEFINED XED_ICLASS_VSQRTPH_DEFINED XED_ICLASS_VSQRTPS_DEFINED XED_ICLASS_VSQRTSD_DEFINED XED_ICLASS_VSQRTSH_DEFINED XED_ICLASS_VSQRTSS_DEFINED XED_ICLASS_VSTMXCSR_DEFINED XED_ICLASS_VSUBPD_DEFINED XED_ICLASS_VSUBPH_DEFINED XED_ICLASS_VSUBPS_DEFINED XED_ICLASS_VSUBSD_DEFINED XED_ICLASS_VSUBSH_DEFINED XED_ICLASS_VSUBSS_DEFINED XED_ICLASS_VTESTPD_DEFINED XED_ICLASS_VTESTPS_DEFINED XED_ICLASS_VUCOMISD_DEFINED XED_ICLASS_VUCOMISH_DEFINED XED_ICLASS_VUCOMISS_DEFINED XED_ICLASS_VUNPCKHPD_DEFINED XED_ICLASS_VUNPCKHPS_DEFINED XED_ICLASS_VUNPCKLPD_DEFINED XED_ICLASS_VUNPCKLPS_DEFINED XED_ICLASS_VXORPD_DEFINED XED_ICLASS_VXORPS_DEFINED XED_ICLASS_VZEROALL_DEFINED XED_ICLASS_VZEROUPPER_DEFINED XED_ICLASS_WBINVD_DEFINED XED_ICLASS_WBNOINVD_DEFINED XED_ICLASS_WRFSBASE_DEFINED XED_ICLASS_WRGSBASE_DEFINED XED_ICLASS_WRMSRLIST_DEFINED XED_ICLASS_WRMSRNS_DEFINED XED_ICLASS_WRMSR_DEFINED XED_ICLASS_WRPKRU_DEFINED XED_ICLASS_WRSSD_DEFINED XED_ICLASS_WRSSQ_DEFINED XED_ICLASS_WRUSSD_DEFINED XED_ICLASS_WRUSSQ_DEFINED XED_ICLASS_XABORT_DEFINED XED_ICLASS_XADD_DEFINED XED_ICLASS_XADD_LOCK_DEFINED XED_ICLASS_XBEGIN_DEFINED XED_ICLASS_XCHG_DEFINED XED_ICLASS_XEND_DEFINED XED_ICLASS_XGETBV_DEFINED XED_ICLASS_XLAT_DEFINED XED_ICLASS_XORPD_DEFINED XED_ICLASS_XORPS_DEFINED XED_ICLASS_XOR_DEFINED XED_ICLASS_XOR_LOCK_DEFINED XED_ICLASS_XRESLDTRK_DEFINED XED_ICLASS_XRSTOR64_DEFINED XED_ICLASS_XRSTORS64_DEFINED XED_ICLASS_XRSTORS_DEFINED XED_ICLASS_XRSTOR_DEFINED XED_ICLASS_XSAVE64_DEFINED XED_ICLASS_XSAVEC64_DEFINED XED_ICLASS_XSAVEC_DEFINED XED_ICLASS_XSAVEOPT64_DEFINED XED_ICLASS_XSAVEOPT_DEFINED XED_ICLASS_XSAVES64_DEFINED XED_ICLASS_XSAVES_DEFINED XED_ICLASS_XSAVE_DEFINED XED_ICLASS_XSETBV_DEFINED XED_ICLASS_XSTORE_DEFINED XED_ICLASS_XSUSLDTRK_DEFINED XED_ICLASS_XTEST_DEFINED XED_IFORMFL_AAA_FIRST_DEFINED XED_IFORMFL_AAA_LAST_DEFINED XED_IFORMFL_AADD_FIRST_DEFINED XED_IFORMFL_AADD_LAST_DEFINED XED_IFORMFL_AAD_FIRST_DEFINED XED_IFORMFL_AAD_LAST_DEFINED XED_IFORMFL_AAM_FIRST_DEFINED XED_IFORMFL_AAM_LAST_DEFINED XED_IFORMFL_AAND_FIRST_DEFINED XED_IFORMFL_AAND_LAST_DEFINED XED_IFORMFL_AAS_FIRST_DEFINED XED_IFORMFL_AAS_LAST_DEFINED XED_IFORMFL_ADCX_FIRST_DEFINED XED_IFORMFL_ADCX_LAST_DEFINED XED_IFORMFL_ADC_FIRST_DEFINED XED_IFORMFL_ADC_LAST_DEFINED XED_IFORMFL_ADC_LOCK_FIRST_DEFINED XED_IFORMFL_ADC_LOCK_LAST_DEFINED XED_IFORMFL_ADDPD_FIRST_DEFINED XED_IFORMFL_ADDPD_LAST_DEFINED XED_IFORMFL_ADDPS_FIRST_DEFINED XED_IFORMFL_ADDPS_LAST_DEFINED XED_IFORMFL_ADDSD_FIRST_DEFINED XED_IFORMFL_ADDSD_LAST_DEFINED XED_IFORMFL_ADDSS_FIRST_DEFINED XED_IFORMFL_ADDSS_LAST_DEFINED XED_IFORMFL_ADDSUBPD_FIRST_DEFINED XED_IFORMFL_ADDSUBPD_LAST_DEFINED XED_IFORMFL_ADDSUBPS_FIRST_DEFINED XED_IFORMFL_ADDSUBPS_LAST_DEFINED XED_IFORMFL_ADD_FIRST_DEFINED XED_IFORMFL_ADD_LAST_DEFINED XED_IFORMFL_ADD_LOCK_FIRST_DEFINED XED_IFORMFL_ADD_LOCK_LAST_DEFINED XED_IFORMFL_ADOX_FIRST_DEFINED XED_IFORMFL_ADOX_LAST_DEFINED XED_IFORMFL_AESDEC128KL_FIRST_DEFINED XED_IFORMFL_AESDEC128KL_LAST_DEFINED XED_IFORMFL_AESDEC256KL_FIRST_DEFINED XED_IFORMFL_AESDEC256KL_LAST_DEFINED XED_IFORMFL_AESDECLAST_FIRST_DEFINED XED_IFORMFL_AESDECLAST_LAST_DEFINED XED_IFORMFL_AESDECWIDE128KL_FIRST_DEFINED XED_IFORMFL_AESDECWIDE128KL_LAST_DEFINED XED_IFORMFL_AESDECWIDE256KL_FIRST_DEFINED XED_IFORMFL_AESDECWIDE256KL_LAST_DEFINED XED_IFORMFL_AESDEC_FIRST_DEFINED XED_IFORMFL_AESDEC_LAST_DEFINED XED_IFORMFL_AESENC128KL_FIRST_DEFINED XED_IFORMFL_AESENC128KL_LAST_DEFINED XED_IFORMFL_AESENC256KL_FIRST_DEFINED XED_IFORMFL_AESENC256KL_LAST_DEFINED XED_IFORMFL_AESENCLAST_FIRST_DEFINED XED_IFORMFL_AESENCLAST_LAST_DEFINED XED_IFORMFL_AESENCWIDE128KL_FIRST_DEFINED XED_IFORMFL_AESENCWIDE128KL_LAST_DEFINED XED_IFORMFL_AESENCWIDE256KL_FIRST_DEFINED XED_IFORMFL_AESENCWIDE256KL_LAST_DEFINED XED_IFORMFL_AESENC_FIRST_DEFINED XED_IFORMFL_AESENC_LAST_DEFINED XED_IFORMFL_AESIMC_FIRST_DEFINED XED_IFORMFL_AESIMC_LAST_DEFINED XED_IFORMFL_AESKEYGENASSIST_FIRST_DEFINED XED_IFORMFL_AESKEYGENASSIST_LAST_DEFINED XED_IFORMFL_ANDNPD_FIRST_DEFINED XED_IFORMFL_ANDNPD_LAST_DEFINED XED_IFORMFL_ANDNPS_FIRST_DEFINED XED_IFORMFL_ANDNPS_LAST_DEFINED XED_IFORMFL_ANDN_FIRST_DEFINED XED_IFORMFL_ANDN_LAST_DEFINED XED_IFORMFL_ANDPD_FIRST_DEFINED XED_IFORMFL_ANDPD_LAST_DEFINED XED_IFORMFL_ANDPS_FIRST_DEFINED XED_IFORMFL_ANDPS_LAST_DEFINED XED_IFORMFL_AND_FIRST_DEFINED XED_IFORMFL_AND_LAST_DEFINED XED_IFORMFL_AND_LOCK_FIRST_DEFINED XED_IFORMFL_AND_LOCK_LAST_DEFINED XED_IFORMFL_AOR_FIRST_DEFINED XED_IFORMFL_AOR_LAST_DEFINED XED_IFORMFL_ARPL_FIRST_DEFINED XED_IFORMFL_ARPL_LAST_DEFINED XED_IFORMFL_AXOR_FIRST_DEFINED XED_IFORMFL_AXOR_LAST_DEFINED XED_IFORMFL_BEXTR_FIRST_DEFINED XED_IFORMFL_BEXTR_LAST_DEFINED XED_IFORMFL_BEXTR_XOP_FIRST_DEFINED XED_IFORMFL_BEXTR_XOP_LAST_DEFINED XED_IFORMFL_BLCFILL_FIRST_DEFINED XED_IFORMFL_BLCFILL_LAST_DEFINED XED_IFORMFL_BLCIC_FIRST_DEFINED XED_IFORMFL_BLCIC_LAST_DEFINED XED_IFORMFL_BLCI_FIRST_DEFINED XED_IFORMFL_BLCI_LAST_DEFINED XED_IFORMFL_BLCMSK_FIRST_DEFINED XED_IFORMFL_BLCMSK_LAST_DEFINED XED_IFORMFL_BLCS_FIRST_DEFINED XED_IFORMFL_BLCS_LAST_DEFINED XED_IFORMFL_BLENDPD_FIRST_DEFINED XED_IFORMFL_BLENDPD_LAST_DEFINED XED_IFORMFL_BLENDPS_FIRST_DEFINED XED_IFORMFL_BLENDPS_LAST_DEFINED XED_IFORMFL_BLENDVPD_FIRST_DEFINED XED_IFORMFL_BLENDVPD_LAST_DEFINED XED_IFORMFL_BLENDVPS_FIRST_DEFINED XED_IFORMFL_BLENDVPS_LAST_DEFINED XED_IFORMFL_BLSFILL_FIRST_DEFINED XED_IFORMFL_BLSFILL_LAST_DEFINED XED_IFORMFL_BLSIC_FIRST_DEFINED XED_IFORMFL_BLSIC_LAST_DEFINED XED_IFORMFL_BLSI_FIRST_DEFINED XED_IFORMFL_BLSI_LAST_DEFINED XED_IFORMFL_BLSMSK_FIRST_DEFINED XED_IFORMFL_BLSMSK_LAST_DEFINED XED_IFORMFL_BLSR_FIRST_DEFINED XED_IFORMFL_BLSR_LAST_DEFINED XED_IFORMFL_BNDCL_FIRST_DEFINED XED_IFORMFL_BNDCL_LAST_DEFINED XED_IFORMFL_BNDCN_FIRST_DEFINED XED_IFORMFL_BNDCN_LAST_DEFINED XED_IFORMFL_BNDCU_FIRST_DEFINED XED_IFORMFL_BNDCU_LAST_DEFINED XED_IFORMFL_BNDLDX_FIRST_DEFINED XED_IFORMFL_BNDLDX_LAST_DEFINED XED_IFORMFL_BNDMK_FIRST_DEFINED XED_IFORMFL_BNDMK_LAST_DEFINED XED_IFORMFL_BNDMOV_FIRST_DEFINED XED_IFORMFL_BNDMOV_LAST_DEFINED XED_IFORMFL_BNDSTX_FIRST_DEFINED XED_IFORMFL_BNDSTX_LAST_DEFINED XED_IFORMFL_BOUND_FIRST_DEFINED XED_IFORMFL_BOUND_LAST_DEFINED XED_IFORMFL_BSF_FIRST_DEFINED XED_IFORMFL_BSF_LAST_DEFINED XED_IFORMFL_BSR_FIRST_DEFINED XED_IFORMFL_BSR_LAST_DEFINED XED_IFORMFL_BSWAP_FIRST_DEFINED XED_IFORMFL_BSWAP_LAST_DEFINED XED_IFORMFL_BTC_FIRST_DEFINED XED_IFORMFL_BTC_LAST_DEFINED XED_IFORMFL_BTC_LOCK_FIRST_DEFINED XED_IFORMFL_BTC_LOCK_LAST_DEFINED XED_IFORMFL_BTR_FIRST_DEFINED XED_IFORMFL_BTR_LAST_DEFINED XED_IFORMFL_BTR_LOCK_FIRST_DEFINED XED_IFORMFL_BTR_LOCK_LAST_DEFINED XED_IFORMFL_BTS_FIRST_DEFINED XED_IFORMFL_BTS_LAST_DEFINED XED_IFORMFL_BTS_LOCK_FIRST_DEFINED XED_IFORMFL_BTS_LOCK_LAST_DEFINED XED_IFORMFL_BT_FIRST_DEFINED XED_IFORMFL_BT_LAST_DEFINED XED_IFORMFL_BZHI_FIRST_DEFINED XED_IFORMFL_BZHI_LAST_DEFINED XED_IFORMFL_CALL_FAR_FIRST_DEFINED XED_IFORMFL_CALL_FAR_LAST_DEFINED XED_IFORMFL_CALL_NEAR_FIRST_DEFINED XED_IFORMFL_CALL_NEAR_LAST_DEFINED XED_IFORMFL_CBW_FIRST_DEFINED XED_IFORMFL_CBW_LAST_DEFINED XED_IFORMFL_CCMPBE_FIRST_DEFINED XED_IFORMFL_CCMPBE_LAST_DEFINED XED_IFORMFL_CCMPB_FIRST_DEFINED XED_IFORMFL_CCMPB_LAST_DEFINED XED_IFORMFL_CCMPF_FIRST_DEFINED XED_IFORMFL_CCMPF_LAST_DEFINED XED_IFORMFL_CCMPLE_FIRST_DEFINED XED_IFORMFL_CCMPLE_LAST_DEFINED XED_IFORMFL_CCMPL_FIRST_DEFINED XED_IFORMFL_CCMPL_LAST_DEFINED XED_IFORMFL_CCMPNBE_FIRST_DEFINED XED_IFORMFL_CCMPNBE_LAST_DEFINED XED_IFORMFL_CCMPNB_FIRST_DEFINED XED_IFORMFL_CCMPNB_LAST_DEFINED XED_IFORMFL_CCMPNLE_FIRST_DEFINED XED_IFORMFL_CCMPNLE_LAST_DEFINED XED_IFORMFL_CCMPNL_FIRST_DEFINED XED_IFORMFL_CCMPNL_LAST_DEFINED XED_IFORMFL_CCMPNO_FIRST_DEFINED XED_IFORMFL_CCMPNO_LAST_DEFINED XED_IFORMFL_CCMPNS_FIRST_DEFINED XED_IFORMFL_CCMPNS_LAST_DEFINED XED_IFORMFL_CCMPNZ_FIRST_DEFINED XED_IFORMFL_CCMPNZ_LAST_DEFINED XED_IFORMFL_CCMPO_FIRST_DEFINED XED_IFORMFL_CCMPO_LAST_DEFINED XED_IFORMFL_CCMPS_FIRST_DEFINED XED_IFORMFL_CCMPS_LAST_DEFINED XED_IFORMFL_CCMPT_FIRST_DEFINED XED_IFORMFL_CCMPT_LAST_DEFINED XED_IFORMFL_CCMPZ_FIRST_DEFINED XED_IFORMFL_CCMPZ_LAST_DEFINED XED_IFORMFL_CDQE_FIRST_DEFINED XED_IFORMFL_CDQE_LAST_DEFINED XED_IFORMFL_CDQ_FIRST_DEFINED XED_IFORMFL_CDQ_LAST_DEFINED XED_IFORMFL_CFCMOVBE_FIRST_DEFINED XED_IFORMFL_CFCMOVBE_LAST_DEFINED XED_IFORMFL_CFCMOVB_FIRST_DEFINED XED_IFORMFL_CFCMOVB_LAST_DEFINED XED_IFORMFL_CFCMOVLE_FIRST_DEFINED XED_IFORMFL_CFCMOVLE_LAST_DEFINED XED_IFORMFL_CFCMOVL_FIRST_DEFINED XED_IFORMFL_CFCMOVL_LAST_DEFINED XED_IFORMFL_CFCMOVNBE_FIRST_DEFINED XED_IFORMFL_CFCMOVNBE_LAST_DEFINED XED_IFORMFL_CFCMOVNB_FIRST_DEFINED XED_IFORMFL_CFCMOVNB_LAST_DEFINED XED_IFORMFL_CFCMOVNLE_FIRST_DEFINED XED_IFORMFL_CFCMOVNLE_LAST_DEFINED XED_IFORMFL_CFCMOVNL_FIRST_DEFINED XED_IFORMFL_CFCMOVNL_LAST_DEFINED XED_IFORMFL_CFCMOVNO_FIRST_DEFINED XED_IFORMFL_CFCMOVNO_LAST_DEFINED XED_IFORMFL_CFCMOVNP_FIRST_DEFINED XED_IFORMFL_CFCMOVNP_LAST_DEFINED XED_IFORMFL_CFCMOVNS_FIRST_DEFINED XED_IFORMFL_CFCMOVNS_LAST_DEFINED XED_IFORMFL_CFCMOVNZ_FIRST_DEFINED XED_IFORMFL_CFCMOVNZ_LAST_DEFINED XED_IFORMFL_CFCMOVO_FIRST_DEFINED XED_IFORMFL_CFCMOVO_LAST_DEFINED XED_IFORMFL_CFCMOVP_FIRST_DEFINED XED_IFORMFL_CFCMOVP_LAST_DEFINED XED_IFORMFL_CFCMOVS_FIRST_DEFINED XED_IFORMFL_CFCMOVS_LAST_DEFINED XED_IFORMFL_CFCMOVZ_FIRST_DEFINED XED_IFORMFL_CFCMOVZ_LAST_DEFINED XED_IFORMFL_CLAC_FIRST_DEFINED XED_IFORMFL_CLAC_LAST_DEFINED XED_IFORMFL_CLC_FIRST_DEFINED XED_IFORMFL_CLC_LAST_DEFINED XED_IFORMFL_CLDEMOTE_FIRST_DEFINED XED_IFORMFL_CLDEMOTE_LAST_DEFINED XED_IFORMFL_CLD_FIRST_DEFINED XED_IFORMFL_CLD_LAST_DEFINED XED_IFORMFL_CLFLUSHOPT_FIRST_DEFINED XED_IFORMFL_CLFLUSHOPT_LAST_DEFINED XED_IFORMFL_CLFLUSH_FIRST_DEFINED XED_IFORMFL_CLFLUSH_LAST_DEFINED XED_IFORMFL_CLGI_FIRST_DEFINED XED_IFORMFL_CLGI_LAST_DEFINED XED_IFORMFL_CLI_FIRST_DEFINED XED_IFORMFL_CLI_LAST_DEFINED XED_IFORMFL_CLRSSBSY_FIRST_DEFINED XED_IFORMFL_CLRSSBSY_LAST_DEFINED XED_IFORMFL_CLTS_FIRST_DEFINED XED_IFORMFL_CLTS_LAST_DEFINED XED_IFORMFL_CLUI_FIRST_DEFINED XED_IFORMFL_CLUI_LAST_DEFINED XED_IFORMFL_CLWB_FIRST_DEFINED XED_IFORMFL_CLWB_LAST_DEFINED XED_IFORMFL_CLZERO_FIRST_DEFINED XED_IFORMFL_CLZERO_LAST_DEFINED XED_IFORMFL_CMC_FIRST_DEFINED XED_IFORMFL_CMC_LAST_DEFINED XED_IFORMFL_CMOVBE_FIRST_DEFINED XED_IFORMFL_CMOVBE_LAST_DEFINED XED_IFORMFL_CMOVB_FIRST_DEFINED XED_IFORMFL_CMOVB_LAST_DEFINED XED_IFORMFL_CMOVLE_FIRST_DEFINED XED_IFORMFL_CMOVLE_LAST_DEFINED XED_IFORMFL_CMOVL_FIRST_DEFINED XED_IFORMFL_CMOVL_LAST_DEFINED XED_IFORMFL_CMOVNBE_FIRST_DEFINED XED_IFORMFL_CMOVNBE_LAST_DEFINED XED_IFORMFL_CMOVNB_FIRST_DEFINED XED_IFORMFL_CMOVNB_LAST_DEFINED XED_IFORMFL_CMOVNLE_FIRST_DEFINED XED_IFORMFL_CMOVNLE_LAST_DEFINED XED_IFORMFL_CMOVNL_FIRST_DEFINED XED_IFORMFL_CMOVNL_LAST_DEFINED XED_IFORMFL_CMOVNO_FIRST_DEFINED XED_IFORMFL_CMOVNO_LAST_DEFINED XED_IFORMFL_CMOVNP_FIRST_DEFINED XED_IFORMFL_CMOVNP_LAST_DEFINED XED_IFORMFL_CMOVNS_FIRST_DEFINED XED_IFORMFL_CMOVNS_LAST_DEFINED XED_IFORMFL_CMOVNZ_FIRST_DEFINED XED_IFORMFL_CMOVNZ_LAST_DEFINED XED_IFORMFL_CMOVO_FIRST_DEFINED XED_IFORMFL_CMOVO_LAST_DEFINED XED_IFORMFL_CMOVP_FIRST_DEFINED XED_IFORMFL_CMOVP_LAST_DEFINED XED_IFORMFL_CMOVS_FIRST_DEFINED XED_IFORMFL_CMOVS_LAST_DEFINED XED_IFORMFL_CMOVZ_FIRST_DEFINED XED_IFORMFL_CMOVZ_LAST_DEFINED XED_IFORMFL_CMPBEXADD_FIRST_DEFINED XED_IFORMFL_CMPBEXADD_LAST_DEFINED XED_IFORMFL_CMPBXADD_FIRST_DEFINED XED_IFORMFL_CMPBXADD_LAST_DEFINED XED_IFORMFL_CMPLEXADD_FIRST_DEFINED XED_IFORMFL_CMPLEXADD_LAST_DEFINED XED_IFORMFL_CMPLXADD_FIRST_DEFINED XED_IFORMFL_CMPLXADD_LAST_DEFINED XED_IFORMFL_CMPNBEXADD_FIRST_DEFINED XED_IFORMFL_CMPNBEXADD_LAST_DEFINED XED_IFORMFL_CMPNBXADD_FIRST_DEFINED XED_IFORMFL_CMPNBXADD_LAST_DEFINED XED_IFORMFL_CMPNLEXADD_FIRST_DEFINED XED_IFORMFL_CMPNLEXADD_LAST_DEFINED XED_IFORMFL_CMPNLXADD_FIRST_DEFINED XED_IFORMFL_CMPNLXADD_LAST_DEFINED XED_IFORMFL_CMPNOXADD_FIRST_DEFINED XED_IFORMFL_CMPNOXADD_LAST_DEFINED XED_IFORMFL_CMPNPXADD_FIRST_DEFINED XED_IFORMFL_CMPNPXADD_LAST_DEFINED XED_IFORMFL_CMPNSXADD_FIRST_DEFINED XED_IFORMFL_CMPNSXADD_LAST_DEFINED XED_IFORMFL_CMPNZXADD_FIRST_DEFINED XED_IFORMFL_CMPNZXADD_LAST_DEFINED XED_IFORMFL_CMPOXADD_FIRST_DEFINED XED_IFORMFL_CMPOXADD_LAST_DEFINED XED_IFORMFL_CMPPD_FIRST_DEFINED XED_IFORMFL_CMPPD_LAST_DEFINED XED_IFORMFL_CMPPS_FIRST_DEFINED XED_IFORMFL_CMPPS_LAST_DEFINED XED_IFORMFL_CMPPXADD_FIRST_DEFINED XED_IFORMFL_CMPPXADD_LAST_DEFINED XED_IFORMFL_CMPSB_FIRST_DEFINED XED_IFORMFL_CMPSB_LAST_DEFINED XED_IFORMFL_CMPSD_FIRST_DEFINED XED_IFORMFL_CMPSD_LAST_DEFINED XED_IFORMFL_CMPSD_XMM_FIRST_DEFINED XED_IFORMFL_CMPSD_XMM_LAST_DEFINED XED_IFORMFL_CMPSQ_FIRST_DEFINED XED_IFORMFL_CMPSQ_LAST_DEFINED XED_IFORMFL_CMPSS_FIRST_DEFINED XED_IFORMFL_CMPSS_LAST_DEFINED XED_IFORMFL_CMPSW_FIRST_DEFINED XED_IFORMFL_CMPSW_LAST_DEFINED XED_IFORMFL_CMPSXADD_FIRST_DEFINED XED_IFORMFL_CMPSXADD_LAST_DEFINED XED_IFORMFL_CMPXCHG8B_FIRST_DEFINED XED_IFORMFL_CMPXCHG8B_LAST_DEFINED XED_IFORMFL_CMPXCHG8B_LOCK_FIRST_DEFINED XED_IFORMFL_CMPXCHG8B_LOCK_LAST_DEFINED XED_IFORMFL_CMPXCHG16B_FIRST_DEFINED XED_IFORMFL_CMPXCHG16B_LAST_DEFINED XED_IFORMFL_CMPXCHG16B_LOCK_FIRST_DEFINED XED_IFORMFL_CMPXCHG16B_LOCK_LAST_DEFINED XED_IFORMFL_CMPXCHG_FIRST_DEFINED XED_IFORMFL_CMPXCHG_LAST_DEFINED XED_IFORMFL_CMPXCHG_LOCK_FIRST_DEFINED XED_IFORMFL_CMPXCHG_LOCK_LAST_DEFINED XED_IFORMFL_CMPZXADD_FIRST_DEFINED XED_IFORMFL_CMPZXADD_LAST_DEFINED XED_IFORMFL_CMP_FIRST_DEFINED XED_IFORMFL_CMP_LAST_DEFINED XED_IFORMFL_COMISD_FIRST_DEFINED XED_IFORMFL_COMISD_LAST_DEFINED XED_IFORMFL_COMISS_FIRST_DEFINED XED_IFORMFL_COMISS_LAST_DEFINED XED_IFORMFL_CPUID_FIRST_DEFINED XED_IFORMFL_CPUID_LAST_DEFINED XED_IFORMFL_CQO_FIRST_DEFINED XED_IFORMFL_CQO_LAST_DEFINED XED_IFORMFL_CRC32_FIRST_DEFINED XED_IFORMFL_CRC32_LAST_DEFINED XED_IFORMFL_CTESTBE_FIRST_DEFINED XED_IFORMFL_CTESTBE_LAST_DEFINED XED_IFORMFL_CTESTB_FIRST_DEFINED XED_IFORMFL_CTESTB_LAST_DEFINED XED_IFORMFL_CTESTF_FIRST_DEFINED XED_IFORMFL_CTESTF_LAST_DEFINED XED_IFORMFL_CTESTLE_FIRST_DEFINED XED_IFORMFL_CTESTLE_LAST_DEFINED XED_IFORMFL_CTESTL_FIRST_DEFINED XED_IFORMFL_CTESTL_LAST_DEFINED XED_IFORMFL_CTESTNBE_FIRST_DEFINED XED_IFORMFL_CTESTNBE_LAST_DEFINED XED_IFORMFL_CTESTNB_FIRST_DEFINED XED_IFORMFL_CTESTNB_LAST_DEFINED XED_IFORMFL_CTESTNLE_FIRST_DEFINED XED_IFORMFL_CTESTNLE_LAST_DEFINED XED_IFORMFL_CTESTNL_FIRST_DEFINED XED_IFORMFL_CTESTNL_LAST_DEFINED XED_IFORMFL_CTESTNO_FIRST_DEFINED XED_IFORMFL_CTESTNO_LAST_DEFINED XED_IFORMFL_CTESTNS_FIRST_DEFINED XED_IFORMFL_CTESTNS_LAST_DEFINED XED_IFORMFL_CTESTNZ_FIRST_DEFINED XED_IFORMFL_CTESTNZ_LAST_DEFINED XED_IFORMFL_CTESTO_FIRST_DEFINED XED_IFORMFL_CTESTO_LAST_DEFINED XED_IFORMFL_CTESTS_FIRST_DEFINED XED_IFORMFL_CTESTS_LAST_DEFINED XED_IFORMFL_CTESTT_FIRST_DEFINED XED_IFORMFL_CTESTT_LAST_DEFINED XED_IFORMFL_CTESTZ_FIRST_DEFINED XED_IFORMFL_CTESTZ_LAST_DEFINED XED_IFORMFL_CVTDQ2PD_FIRST_DEFINED XED_IFORMFL_CVTDQ2PD_LAST_DEFINED XED_IFORMFL_CVTDQ2PS_FIRST_DEFINED XED_IFORMFL_CVTDQ2PS_LAST_DEFINED XED_IFORMFL_CVTPD2DQ_FIRST_DEFINED XED_IFORMFL_CVTPD2DQ_LAST_DEFINED XED_IFORMFL_CVTPD2PI_FIRST_DEFINED XED_IFORMFL_CVTPD2PI_LAST_DEFINED XED_IFORMFL_CVTPD2PS_FIRST_DEFINED XED_IFORMFL_CVTPD2PS_LAST_DEFINED XED_IFORMFL_CVTPI2PD_FIRST_DEFINED XED_IFORMFL_CVTPI2PD_LAST_DEFINED XED_IFORMFL_CVTPI2PS_FIRST_DEFINED XED_IFORMFL_CVTPI2PS_LAST_DEFINED XED_IFORMFL_CVTPS2DQ_FIRST_DEFINED XED_IFORMFL_CVTPS2DQ_LAST_DEFINED XED_IFORMFL_CVTPS2PD_FIRST_DEFINED XED_IFORMFL_CVTPS2PD_LAST_DEFINED XED_IFORMFL_CVTPS2PI_FIRST_DEFINED XED_IFORMFL_CVTPS2PI_LAST_DEFINED XED_IFORMFL_CVTSD2SI_FIRST_DEFINED XED_IFORMFL_CVTSD2SI_LAST_DEFINED XED_IFORMFL_CVTSD2SS_FIRST_DEFINED XED_IFORMFL_CVTSD2SS_LAST_DEFINED XED_IFORMFL_CVTSI2SD_FIRST_DEFINED XED_IFORMFL_CVTSI2SD_LAST_DEFINED XED_IFORMFL_CVTSI2SS_FIRST_DEFINED XED_IFORMFL_CVTSI2SS_LAST_DEFINED XED_IFORMFL_CVTSS2SD_FIRST_DEFINED XED_IFORMFL_CVTSS2SD_LAST_DEFINED XED_IFORMFL_CVTSS2SI_FIRST_DEFINED XED_IFORMFL_CVTSS2SI_LAST_DEFINED XED_IFORMFL_CVTTPD2DQ_FIRST_DEFINED XED_IFORMFL_CVTTPD2DQ_LAST_DEFINED XED_IFORMFL_CVTTPD2PI_FIRST_DEFINED XED_IFORMFL_CVTTPD2PI_LAST_DEFINED XED_IFORMFL_CVTTPS2DQ_FIRST_DEFINED XED_IFORMFL_CVTTPS2DQ_LAST_DEFINED XED_IFORMFL_CVTTPS2PI_FIRST_DEFINED XED_IFORMFL_CVTTPS2PI_LAST_DEFINED XED_IFORMFL_CVTTSD2SI_FIRST_DEFINED XED_IFORMFL_CVTTSD2SI_LAST_DEFINED XED_IFORMFL_CVTTSS2SI_FIRST_DEFINED XED_IFORMFL_CVTTSS2SI_LAST_DEFINED XED_IFORMFL_CWDE_FIRST_DEFINED XED_IFORMFL_CWDE_LAST_DEFINED XED_IFORMFL_CWD_FIRST_DEFINED XED_IFORMFL_CWD_LAST_DEFINED XED_IFORMFL_DAA_FIRST_DEFINED XED_IFORMFL_DAA_LAST_DEFINED XED_IFORMFL_DAS_FIRST_DEFINED XED_IFORMFL_DAS_LAST_DEFINED XED_IFORMFL_DEC_FIRST_DEFINED XED_IFORMFL_DEC_LAST_DEFINED XED_IFORMFL_DEC_LOCK_FIRST_DEFINED XED_IFORMFL_DEC_LOCK_LAST_DEFINED XED_IFORMFL_DIVPD_FIRST_DEFINED XED_IFORMFL_DIVPD_LAST_DEFINED XED_IFORMFL_DIVPS_FIRST_DEFINED XED_IFORMFL_DIVPS_LAST_DEFINED XED_IFORMFL_DIVSD_FIRST_DEFINED XED_IFORMFL_DIVSD_LAST_DEFINED XED_IFORMFL_DIVSS_FIRST_DEFINED XED_IFORMFL_DIVSS_LAST_DEFINED XED_IFORMFL_DIV_FIRST_DEFINED XED_IFORMFL_DIV_LAST_DEFINED XED_IFORMFL_DPPD_FIRST_DEFINED XED_IFORMFL_DPPD_LAST_DEFINED XED_IFORMFL_DPPS_FIRST_DEFINED XED_IFORMFL_DPPS_LAST_DEFINED XED_IFORMFL_EMMS_FIRST_DEFINED XED_IFORMFL_EMMS_LAST_DEFINED XED_IFORMFL_ENCLS_FIRST_DEFINED XED_IFORMFL_ENCLS_LAST_DEFINED XED_IFORMFL_ENCLU_FIRST_DEFINED XED_IFORMFL_ENCLU_LAST_DEFINED XED_IFORMFL_ENCLV_FIRST_DEFINED XED_IFORMFL_ENCLV_LAST_DEFINED XED_IFORMFL_ENCODEKEY128_FIRST_DEFINED XED_IFORMFL_ENCODEKEY128_LAST_DEFINED XED_IFORMFL_ENCODEKEY256_FIRST_DEFINED XED_IFORMFL_ENCODEKEY256_LAST_DEFINED XED_IFORMFL_ENDBR32_FIRST_DEFINED XED_IFORMFL_ENDBR32_LAST_DEFINED XED_IFORMFL_ENDBR64_FIRST_DEFINED XED_IFORMFL_ENDBR64_LAST_DEFINED XED_IFORMFL_ENQCMDS_FIRST_DEFINED XED_IFORMFL_ENQCMDS_LAST_DEFINED XED_IFORMFL_ENQCMD_FIRST_DEFINED XED_IFORMFL_ENQCMD_LAST_DEFINED XED_IFORMFL_ENTER_FIRST_DEFINED XED_IFORMFL_ENTER_LAST_DEFINED XED_IFORMFL_ERETS_FIRST_DEFINED XED_IFORMFL_ERETS_LAST_DEFINED XED_IFORMFL_ERETU_FIRST_DEFINED XED_IFORMFL_ERETU_LAST_DEFINED XED_IFORMFL_EXTRACTPS_FIRST_DEFINED XED_IFORMFL_EXTRACTPS_LAST_DEFINED XED_IFORMFL_EXTRQ_FIRST_DEFINED XED_IFORMFL_EXTRQ_LAST_DEFINED XED_IFORMFL_F2XM1_FIRST_DEFINED XED_IFORMFL_F2XM1_LAST_DEFINED XED_IFORMFL_FABS_FIRST_DEFINED XED_IFORMFL_FABS_LAST_DEFINED XED_IFORMFL_FADDP_FIRST_DEFINED XED_IFORMFL_FADDP_LAST_DEFINED XED_IFORMFL_FADD_FIRST_DEFINED XED_IFORMFL_FADD_LAST_DEFINED XED_IFORMFL_FBLD_FIRST_DEFINED XED_IFORMFL_FBLD_LAST_DEFINED XED_IFORMFL_FBSTP_FIRST_DEFINED XED_IFORMFL_FBSTP_LAST_DEFINED XED_IFORMFL_FCHS_FIRST_DEFINED XED_IFORMFL_FCHS_LAST_DEFINED XED_IFORMFL_FCMOVBE_FIRST_DEFINED XED_IFORMFL_FCMOVBE_LAST_DEFINED XED_IFORMFL_FCMOVB_FIRST_DEFINED XED_IFORMFL_FCMOVB_LAST_DEFINED XED_IFORMFL_FCMOVE_FIRST_DEFINED XED_IFORMFL_FCMOVE_LAST_DEFINED XED_IFORMFL_FCMOVNBE_FIRST_DEFINED XED_IFORMFL_FCMOVNBE_LAST_DEFINED XED_IFORMFL_FCMOVNB_FIRST_DEFINED XED_IFORMFL_FCMOVNB_LAST_DEFINED XED_IFORMFL_FCMOVNE_FIRST_DEFINED XED_IFORMFL_FCMOVNE_LAST_DEFINED XED_IFORMFL_FCMOVNU_FIRST_DEFINED XED_IFORMFL_FCMOVNU_LAST_DEFINED XED_IFORMFL_FCMOVU_FIRST_DEFINED XED_IFORMFL_FCMOVU_LAST_DEFINED XED_IFORMFL_FCOMIP_FIRST_DEFINED XED_IFORMFL_FCOMIP_LAST_DEFINED XED_IFORMFL_FCOMI_FIRST_DEFINED XED_IFORMFL_FCOMI_LAST_DEFINED XED_IFORMFL_FCOMPP_FIRST_DEFINED XED_IFORMFL_FCOMPP_LAST_DEFINED XED_IFORMFL_FCOMP_FIRST_DEFINED XED_IFORMFL_FCOMP_LAST_DEFINED XED_IFORMFL_FCOM_FIRST_DEFINED XED_IFORMFL_FCOM_LAST_DEFINED XED_IFORMFL_FCOS_FIRST_DEFINED XED_IFORMFL_FCOS_LAST_DEFINED XED_IFORMFL_FDECSTP_FIRST_DEFINED XED_IFORMFL_FDECSTP_LAST_DEFINED XED_IFORMFL_FDISI8087_NOP_FIRST_DEFINED XED_IFORMFL_FDISI8087_NOP_LAST_DEFINED XED_IFORMFL_FDIVP_FIRST_DEFINED XED_IFORMFL_FDIVP_LAST_DEFINED XED_IFORMFL_FDIVRP_FIRST_DEFINED XED_IFORMFL_FDIVRP_LAST_DEFINED XED_IFORMFL_FDIVR_FIRST_DEFINED XED_IFORMFL_FDIVR_LAST_DEFINED XED_IFORMFL_FDIV_FIRST_DEFINED XED_IFORMFL_FDIV_LAST_DEFINED XED_IFORMFL_FEMMS_FIRST_DEFINED XED_IFORMFL_FEMMS_LAST_DEFINED XED_IFORMFL_FENI8087_NOP_FIRST_DEFINED XED_IFORMFL_FENI8087_NOP_LAST_DEFINED XED_IFORMFL_FFREEP_FIRST_DEFINED XED_IFORMFL_FFREEP_LAST_DEFINED XED_IFORMFL_FFREE_FIRST_DEFINED XED_IFORMFL_FFREE_LAST_DEFINED XED_IFORMFL_FIADD_FIRST_DEFINED XED_IFORMFL_FIADD_LAST_DEFINED XED_IFORMFL_FICOMP_FIRST_DEFINED XED_IFORMFL_FICOMP_LAST_DEFINED XED_IFORMFL_FICOM_FIRST_DEFINED XED_IFORMFL_FICOM_LAST_DEFINED XED_IFORMFL_FIDIVR_FIRST_DEFINED XED_IFORMFL_FIDIVR_LAST_DEFINED XED_IFORMFL_FIDIV_FIRST_DEFINED XED_IFORMFL_FIDIV_LAST_DEFINED XED_IFORMFL_FILD_FIRST_DEFINED XED_IFORMFL_FILD_LAST_DEFINED XED_IFORMFL_FIMUL_FIRST_DEFINED XED_IFORMFL_FIMUL_LAST_DEFINED XED_IFORMFL_FINCSTP_FIRST_DEFINED XED_IFORMFL_FINCSTP_LAST_DEFINED XED_IFORMFL_FISTP_FIRST_DEFINED XED_IFORMFL_FISTP_LAST_DEFINED XED_IFORMFL_FISTTP_FIRST_DEFINED XED_IFORMFL_FISTTP_LAST_DEFINED XED_IFORMFL_FIST_FIRST_DEFINED XED_IFORMFL_FIST_LAST_DEFINED XED_IFORMFL_FISUBR_FIRST_DEFINED XED_IFORMFL_FISUBR_LAST_DEFINED XED_IFORMFL_FISUB_FIRST_DEFINED XED_IFORMFL_FISUB_LAST_DEFINED XED_IFORMFL_FLD1_FIRST_DEFINED XED_IFORMFL_FLD1_LAST_DEFINED XED_IFORMFL_FLDCW_FIRST_DEFINED XED_IFORMFL_FLDCW_LAST_DEFINED XED_IFORMFL_FLDENV_FIRST_DEFINED XED_IFORMFL_FLDENV_LAST_DEFINED XED_IFORMFL_FLDL2E_FIRST_DEFINED XED_IFORMFL_FLDL2E_LAST_DEFINED XED_IFORMFL_FLDL2T_FIRST_DEFINED XED_IFORMFL_FLDL2T_LAST_DEFINED XED_IFORMFL_FLDLG2_FIRST_DEFINED XED_IFORMFL_FLDLG2_LAST_DEFINED XED_IFORMFL_FLDLN2_FIRST_DEFINED XED_IFORMFL_FLDLN2_LAST_DEFINED XED_IFORMFL_FLDPI_FIRST_DEFINED XED_IFORMFL_FLDPI_LAST_DEFINED XED_IFORMFL_FLDZ_FIRST_DEFINED XED_IFORMFL_FLDZ_LAST_DEFINED XED_IFORMFL_FLD_FIRST_DEFINED XED_IFORMFL_FLD_LAST_DEFINED XED_IFORMFL_FMULP_FIRST_DEFINED XED_IFORMFL_FMULP_LAST_DEFINED XED_IFORMFL_FMUL_FIRST_DEFINED XED_IFORMFL_FMUL_LAST_DEFINED XED_IFORMFL_FNCLEX_FIRST_DEFINED XED_IFORMFL_FNCLEX_LAST_DEFINED XED_IFORMFL_FNINIT_FIRST_DEFINED XED_IFORMFL_FNINIT_LAST_DEFINED XED_IFORMFL_FNOP_FIRST_DEFINED XED_IFORMFL_FNOP_LAST_DEFINED XED_IFORMFL_FNSAVE_FIRST_DEFINED XED_IFORMFL_FNSAVE_LAST_DEFINED XED_IFORMFL_FNSTCW_FIRST_DEFINED XED_IFORMFL_FNSTCW_LAST_DEFINED XED_IFORMFL_FNSTENV_FIRST_DEFINED XED_IFORMFL_FNSTENV_LAST_DEFINED XED_IFORMFL_FNSTSW_FIRST_DEFINED XED_IFORMFL_FNSTSW_LAST_DEFINED XED_IFORMFL_FPATAN_FIRST_DEFINED XED_IFORMFL_FPATAN_LAST_DEFINED XED_IFORMFL_FPREM1_FIRST_DEFINED XED_IFORMFL_FPREM1_LAST_DEFINED XED_IFORMFL_FPREM_FIRST_DEFINED XED_IFORMFL_FPREM_LAST_DEFINED XED_IFORMFL_FPTAN_FIRST_DEFINED XED_IFORMFL_FPTAN_LAST_DEFINED XED_IFORMFL_FRNDINT_FIRST_DEFINED XED_IFORMFL_FRNDINT_LAST_DEFINED XED_IFORMFL_FRSTOR_FIRST_DEFINED XED_IFORMFL_FRSTOR_LAST_DEFINED XED_IFORMFL_FSCALE_FIRST_DEFINED XED_IFORMFL_FSCALE_LAST_DEFINED XED_IFORMFL_FSETPM287_NOP_FIRST_DEFINED XED_IFORMFL_FSETPM287_NOP_LAST_DEFINED XED_IFORMFL_FSINCOS_FIRST_DEFINED XED_IFORMFL_FSINCOS_LAST_DEFINED XED_IFORMFL_FSIN_FIRST_DEFINED XED_IFORMFL_FSIN_LAST_DEFINED XED_IFORMFL_FSQRT_FIRST_DEFINED XED_IFORMFL_FSQRT_LAST_DEFINED XED_IFORMFL_FSTPNCE_FIRST_DEFINED XED_IFORMFL_FSTPNCE_LAST_DEFINED XED_IFORMFL_FSTP_FIRST_DEFINED XED_IFORMFL_FSTP_LAST_DEFINED XED_IFORMFL_FST_FIRST_DEFINED XED_IFORMFL_FST_LAST_DEFINED XED_IFORMFL_FSUBP_FIRST_DEFINED XED_IFORMFL_FSUBP_LAST_DEFINED XED_IFORMFL_FSUBRP_FIRST_DEFINED XED_IFORMFL_FSUBRP_LAST_DEFINED XED_IFORMFL_FSUBR_FIRST_DEFINED XED_IFORMFL_FSUBR_LAST_DEFINED XED_IFORMFL_FSUB_FIRST_DEFINED XED_IFORMFL_FSUB_LAST_DEFINED XED_IFORMFL_FTST_FIRST_DEFINED XED_IFORMFL_FTST_LAST_DEFINED XED_IFORMFL_FUCOMIP_FIRST_DEFINED XED_IFORMFL_FUCOMIP_LAST_DEFINED XED_IFORMFL_FUCOMI_FIRST_DEFINED XED_IFORMFL_FUCOMI_LAST_DEFINED XED_IFORMFL_FUCOMPP_FIRST_DEFINED XED_IFORMFL_FUCOMPP_LAST_DEFINED XED_IFORMFL_FUCOMP_FIRST_DEFINED XED_IFORMFL_FUCOMP_LAST_DEFINED XED_IFORMFL_FUCOM_FIRST_DEFINED XED_IFORMFL_FUCOM_LAST_DEFINED XED_IFORMFL_FWAIT_FIRST_DEFINED XED_IFORMFL_FWAIT_LAST_DEFINED XED_IFORMFL_FXAM_FIRST_DEFINED XED_IFORMFL_FXAM_LAST_DEFINED XED_IFORMFL_FXCH_FIRST_DEFINED XED_IFORMFL_FXCH_LAST_DEFINED XED_IFORMFL_FXRSTOR64_FIRST_DEFINED XED_IFORMFL_FXRSTOR64_LAST_DEFINED XED_IFORMFL_FXRSTOR_FIRST_DEFINED XED_IFORMFL_FXRSTOR_LAST_DEFINED XED_IFORMFL_FXSAVE64_FIRST_DEFINED XED_IFORMFL_FXSAVE64_LAST_DEFINED XED_IFORMFL_FXSAVE_FIRST_DEFINED XED_IFORMFL_FXSAVE_LAST_DEFINED XED_IFORMFL_FXTRACT_FIRST_DEFINED XED_IFORMFL_FXTRACT_LAST_DEFINED XED_IFORMFL_FYL2XP1_FIRST_DEFINED XED_IFORMFL_FYL2XP1_LAST_DEFINED XED_IFORMFL_FYL2X_FIRST_DEFINED XED_IFORMFL_FYL2X_LAST_DEFINED XED_IFORMFL_GETSEC_FIRST_DEFINED XED_IFORMFL_GETSEC_LAST_DEFINED XED_IFORMFL_GF2P8AFFINEINVQB_FIRST_DEFINED XED_IFORMFL_GF2P8AFFINEINVQB_LAST_DEFINED XED_IFORMFL_GF2P8AFFINEQB_FIRST_DEFINED XED_IFORMFL_GF2P8AFFINEQB_LAST_DEFINED XED_IFORMFL_GF2P8MULB_FIRST_DEFINED XED_IFORMFL_GF2P8MULB_LAST_DEFINED XED_IFORMFL_HADDPD_FIRST_DEFINED XED_IFORMFL_HADDPD_LAST_DEFINED XED_IFORMFL_HADDPS_FIRST_DEFINED XED_IFORMFL_HADDPS_LAST_DEFINED XED_IFORMFL_HLT_FIRST_DEFINED XED_IFORMFL_HLT_LAST_DEFINED XED_IFORMFL_HRESET_FIRST_DEFINED XED_IFORMFL_HRESET_LAST_DEFINED XED_IFORMFL_HSUBPD_FIRST_DEFINED XED_IFORMFL_HSUBPD_LAST_DEFINED XED_IFORMFL_HSUBPS_FIRST_DEFINED XED_IFORMFL_HSUBPS_LAST_DEFINED XED_IFORMFL_IDIV_FIRST_DEFINED XED_IFORMFL_IDIV_LAST_DEFINED XED_IFORMFL_IMUL_FIRST_DEFINED XED_IFORMFL_IMUL_LAST_DEFINED XED_IFORMFL_INCSSPD_FIRST_DEFINED XED_IFORMFL_INCSSPD_LAST_DEFINED XED_IFORMFL_INCSSPQ_FIRST_DEFINED XED_IFORMFL_INCSSPQ_LAST_DEFINED XED_IFORMFL_INC_FIRST_DEFINED XED_IFORMFL_INC_LAST_DEFINED XED_IFORMFL_INC_LOCK_FIRST_DEFINED XED_IFORMFL_INC_LOCK_LAST_DEFINED XED_IFORMFL_INSB_FIRST_DEFINED XED_IFORMFL_INSB_LAST_DEFINED XED_IFORMFL_INSD_FIRST_DEFINED XED_IFORMFL_INSD_LAST_DEFINED XED_IFORMFL_INSERTPS_FIRST_DEFINED XED_IFORMFL_INSERTPS_LAST_DEFINED XED_IFORMFL_INSERTQ_FIRST_DEFINED XED_IFORMFL_INSERTQ_LAST_DEFINED XED_IFORMFL_INSW_FIRST_DEFINED XED_IFORMFL_INSW_LAST_DEFINED XED_IFORMFL_INT1_FIRST_DEFINED XED_IFORMFL_INT1_LAST_DEFINED XED_IFORMFL_INT3_FIRST_DEFINED XED_IFORMFL_INT3_LAST_DEFINED XED_IFORMFL_INTO_FIRST_DEFINED XED_IFORMFL_INTO_LAST_DEFINED XED_IFORMFL_INT_FIRST_DEFINED XED_IFORMFL_INT_LAST_DEFINED XED_IFORMFL_INVD_FIRST_DEFINED XED_IFORMFL_INVD_LAST_DEFINED XED_IFORMFL_INVEPT_FIRST_DEFINED XED_IFORMFL_INVEPT_LAST_DEFINED XED_IFORMFL_INVLPGA_FIRST_DEFINED XED_IFORMFL_INVLPGA_LAST_DEFINED XED_IFORMFL_INVLPGB_FIRST_DEFINED XED_IFORMFL_INVLPGB_LAST_DEFINED XED_IFORMFL_INVLPG_FIRST_DEFINED XED_IFORMFL_INVLPG_LAST_DEFINED XED_IFORMFL_INVPCID_FIRST_DEFINED XED_IFORMFL_INVPCID_LAST_DEFINED XED_IFORMFL_INVVPID_FIRST_DEFINED XED_IFORMFL_INVVPID_LAST_DEFINED XED_IFORMFL_IN_FIRST_DEFINED XED_IFORMFL_IN_LAST_DEFINED XED_IFORMFL_IRETD_FIRST_DEFINED XED_IFORMFL_IRETD_LAST_DEFINED XED_IFORMFL_IRETQ_FIRST_DEFINED XED_IFORMFL_IRETQ_LAST_DEFINED XED_IFORMFL_IRET_FIRST_DEFINED XED_IFORMFL_IRET_LAST_DEFINED XED_IFORMFL_JBE_FIRST_DEFINED XED_IFORMFL_JBE_LAST_DEFINED XED_IFORMFL_JB_FIRST_DEFINED XED_IFORMFL_JB_LAST_DEFINED XED_IFORMFL_JCXZ_FIRST_DEFINED XED_IFORMFL_JCXZ_LAST_DEFINED XED_IFORMFL_JECXZ_FIRST_DEFINED XED_IFORMFL_JECXZ_LAST_DEFINED XED_IFORMFL_JLE_FIRST_DEFINED XED_IFORMFL_JLE_LAST_DEFINED XED_IFORMFL_JL_FIRST_DEFINED XED_IFORMFL_JL_LAST_DEFINED XED_IFORMFL_JMPABS_FIRST_DEFINED XED_IFORMFL_JMPABS_LAST_DEFINED XED_IFORMFL_JMP_FAR_FIRST_DEFINED XED_IFORMFL_JMP_FAR_LAST_DEFINED XED_IFORMFL_JMP_FIRST_DEFINED XED_IFORMFL_JMP_LAST_DEFINED XED_IFORMFL_JNBE_FIRST_DEFINED XED_IFORMFL_JNBE_LAST_DEFINED XED_IFORMFL_JNB_FIRST_DEFINED XED_IFORMFL_JNB_LAST_DEFINED XED_IFORMFL_JNLE_FIRST_DEFINED XED_IFORMFL_JNLE_LAST_DEFINED XED_IFORMFL_JNL_FIRST_DEFINED XED_IFORMFL_JNL_LAST_DEFINED XED_IFORMFL_JNO_FIRST_DEFINED XED_IFORMFL_JNO_LAST_DEFINED XED_IFORMFL_JNP_FIRST_DEFINED XED_IFORMFL_JNP_LAST_DEFINED XED_IFORMFL_JNS_FIRST_DEFINED XED_IFORMFL_JNS_LAST_DEFINED XED_IFORMFL_JNZ_FIRST_DEFINED XED_IFORMFL_JNZ_LAST_DEFINED XED_IFORMFL_JO_FIRST_DEFINED XED_IFORMFL_JO_LAST_DEFINED XED_IFORMFL_JP_FIRST_DEFINED XED_IFORMFL_JP_LAST_DEFINED XED_IFORMFL_JRCXZ_FIRST_DEFINED XED_IFORMFL_JRCXZ_LAST_DEFINED XED_IFORMFL_JS_FIRST_DEFINED XED_IFORMFL_JS_LAST_DEFINED XED_IFORMFL_JZ_FIRST_DEFINED XED_IFORMFL_JZ_LAST_DEFINED XED_IFORMFL_KADDB_FIRST_DEFINED XED_IFORMFL_KADDB_LAST_DEFINED XED_IFORMFL_KADDD_FIRST_DEFINED XED_IFORMFL_KADDD_LAST_DEFINED XED_IFORMFL_KADDQ_FIRST_DEFINED XED_IFORMFL_KADDQ_LAST_DEFINED XED_IFORMFL_KADDW_FIRST_DEFINED XED_IFORMFL_KADDW_LAST_DEFINED XED_IFORMFL_KANDB_FIRST_DEFINED XED_IFORMFL_KANDB_LAST_DEFINED XED_IFORMFL_KANDD_FIRST_DEFINED XED_IFORMFL_KANDD_LAST_DEFINED XED_IFORMFL_KANDNB_FIRST_DEFINED XED_IFORMFL_KANDNB_LAST_DEFINED XED_IFORMFL_KANDND_FIRST_DEFINED XED_IFORMFL_KANDND_LAST_DEFINED XED_IFORMFL_KANDNQ_FIRST_DEFINED XED_IFORMFL_KANDNQ_LAST_DEFINED XED_IFORMFL_KANDNW_FIRST_DEFINED XED_IFORMFL_KANDNW_LAST_DEFINED XED_IFORMFL_KANDQ_FIRST_DEFINED XED_IFORMFL_KANDQ_LAST_DEFINED XED_IFORMFL_KANDW_FIRST_DEFINED XED_IFORMFL_KANDW_LAST_DEFINED XED_IFORMFL_KMOVB_FIRST_DEFINED XED_IFORMFL_KMOVB_LAST_DEFINED XED_IFORMFL_KMOVD_FIRST_DEFINED XED_IFORMFL_KMOVD_LAST_DEFINED XED_IFORMFL_KMOVQ_FIRST_DEFINED XED_IFORMFL_KMOVQ_LAST_DEFINED XED_IFORMFL_KMOVW_FIRST_DEFINED XED_IFORMFL_KMOVW_LAST_DEFINED XED_IFORMFL_KNOTB_FIRST_DEFINED XED_IFORMFL_KNOTB_LAST_DEFINED XED_IFORMFL_KNOTD_FIRST_DEFINED XED_IFORMFL_KNOTD_LAST_DEFINED XED_IFORMFL_KNOTQ_FIRST_DEFINED XED_IFORMFL_KNOTQ_LAST_DEFINED XED_IFORMFL_KNOTW_FIRST_DEFINED XED_IFORMFL_KNOTW_LAST_DEFINED XED_IFORMFL_KORB_FIRST_DEFINED XED_IFORMFL_KORB_LAST_DEFINED XED_IFORMFL_KORD_FIRST_DEFINED XED_IFORMFL_KORD_LAST_DEFINED XED_IFORMFL_KORQ_FIRST_DEFINED XED_IFORMFL_KORQ_LAST_DEFINED XED_IFORMFL_KORTESTB_FIRST_DEFINED XED_IFORMFL_KORTESTB_LAST_DEFINED XED_IFORMFL_KORTESTD_FIRST_DEFINED XED_IFORMFL_KORTESTD_LAST_DEFINED XED_IFORMFL_KORTESTQ_FIRST_DEFINED XED_IFORMFL_KORTESTQ_LAST_DEFINED XED_IFORMFL_KORTESTW_FIRST_DEFINED XED_IFORMFL_KORTESTW_LAST_DEFINED XED_IFORMFL_KORW_FIRST_DEFINED XED_IFORMFL_KORW_LAST_DEFINED XED_IFORMFL_KSHIFTLB_FIRST_DEFINED XED_IFORMFL_KSHIFTLB_LAST_DEFINED XED_IFORMFL_KSHIFTLD_FIRST_DEFINED XED_IFORMFL_KSHIFTLD_LAST_DEFINED XED_IFORMFL_KSHIFTLQ_FIRST_DEFINED XED_IFORMFL_KSHIFTLQ_LAST_DEFINED XED_IFORMFL_KSHIFTLW_FIRST_DEFINED XED_IFORMFL_KSHIFTLW_LAST_DEFINED XED_IFORMFL_KSHIFTRB_FIRST_DEFINED XED_IFORMFL_KSHIFTRB_LAST_DEFINED XED_IFORMFL_KSHIFTRD_FIRST_DEFINED XED_IFORMFL_KSHIFTRD_LAST_DEFINED XED_IFORMFL_KSHIFTRQ_FIRST_DEFINED XED_IFORMFL_KSHIFTRQ_LAST_DEFINED XED_IFORMFL_KSHIFTRW_FIRST_DEFINED XED_IFORMFL_KSHIFTRW_LAST_DEFINED XED_IFORMFL_KTESTB_FIRST_DEFINED XED_IFORMFL_KTESTB_LAST_DEFINED XED_IFORMFL_KTESTD_FIRST_DEFINED XED_IFORMFL_KTESTD_LAST_DEFINED XED_IFORMFL_KTESTQ_FIRST_DEFINED XED_IFORMFL_KTESTQ_LAST_DEFINED XED_IFORMFL_KTESTW_FIRST_DEFINED XED_IFORMFL_KTESTW_LAST_DEFINED XED_IFORMFL_KUNPCKBW_FIRST_DEFINED XED_IFORMFL_KUNPCKBW_LAST_DEFINED XED_IFORMFL_KUNPCKDQ_FIRST_DEFINED XED_IFORMFL_KUNPCKDQ_LAST_DEFINED XED_IFORMFL_KUNPCKWD_FIRST_DEFINED XED_IFORMFL_KUNPCKWD_LAST_DEFINED XED_IFORMFL_KXNORB_FIRST_DEFINED XED_IFORMFL_KXNORB_LAST_DEFINED XED_IFORMFL_KXNORD_FIRST_DEFINED XED_IFORMFL_KXNORD_LAST_DEFINED XED_IFORMFL_KXNORQ_FIRST_DEFINED XED_IFORMFL_KXNORQ_LAST_DEFINED XED_IFORMFL_KXNORW_FIRST_DEFINED XED_IFORMFL_KXNORW_LAST_DEFINED XED_IFORMFL_KXORB_FIRST_DEFINED XED_IFORMFL_KXORB_LAST_DEFINED XED_IFORMFL_KXORD_FIRST_DEFINED XED_IFORMFL_KXORD_LAST_DEFINED XED_IFORMFL_KXORQ_FIRST_DEFINED XED_IFORMFL_KXORQ_LAST_DEFINED XED_IFORMFL_KXORW_FIRST_DEFINED XED_IFORMFL_KXORW_LAST_DEFINED XED_IFORMFL_LAHF_FIRST_DEFINED XED_IFORMFL_LAHF_LAST_DEFINED XED_IFORMFL_LAR_FIRST_DEFINED XED_IFORMFL_LAR_LAST_DEFINED XED_IFORMFL_LAST_DEFINED XED_IFORMFL_LDDQU_FIRST_DEFINED XED_IFORMFL_LDDQU_LAST_DEFINED XED_IFORMFL_LDMXCSR_FIRST_DEFINED XED_IFORMFL_LDMXCSR_LAST_DEFINED XED_IFORMFL_LDS_FIRST_DEFINED XED_IFORMFL_LDS_LAST_DEFINED XED_IFORMFL_LDTILECFG_FIRST_DEFINED XED_IFORMFL_LDTILECFG_LAST_DEFINED XED_IFORMFL_LEAVE_FIRST_DEFINED XED_IFORMFL_LEAVE_LAST_DEFINED XED_IFORMFL_LEA_FIRST_DEFINED XED_IFORMFL_LEA_LAST_DEFINED XED_IFORMFL_LES_FIRST_DEFINED XED_IFORMFL_LES_LAST_DEFINED XED_IFORMFL_LFENCE_FIRST_DEFINED XED_IFORMFL_LFENCE_LAST_DEFINED XED_IFORMFL_LFS_FIRST_DEFINED XED_IFORMFL_LFS_LAST_DEFINED XED_IFORMFL_LGDT_FIRST_DEFINED XED_IFORMFL_LGDT_LAST_DEFINED XED_IFORMFL_LGS_FIRST_DEFINED XED_IFORMFL_LGS_LAST_DEFINED XED_IFORMFL_LIDT_FIRST_DEFINED XED_IFORMFL_LIDT_LAST_DEFINED XED_IFORMFL_LKGS_FIRST_DEFINED XED_IFORMFL_LKGS_LAST_DEFINED XED_IFORMFL_LLDT_FIRST_DEFINED XED_IFORMFL_LLDT_LAST_DEFINED XED_IFORMFL_LLWPCB_FIRST_DEFINED XED_IFORMFL_LLWPCB_LAST_DEFINED XED_IFORMFL_LMSW_FIRST_DEFINED XED_IFORMFL_LMSW_LAST_DEFINED XED_IFORMFL_LOADIWKEY_FIRST_DEFINED XED_IFORMFL_LOADIWKEY_LAST_DEFINED XED_IFORMFL_LODSB_FIRST_DEFINED XED_IFORMFL_LODSB_LAST_DEFINED XED_IFORMFL_LODSD_FIRST_DEFINED XED_IFORMFL_LODSD_LAST_DEFINED XED_IFORMFL_LODSQ_FIRST_DEFINED XED_IFORMFL_LODSQ_LAST_DEFINED XED_IFORMFL_LODSW_FIRST_DEFINED XED_IFORMFL_LODSW_LAST_DEFINED XED_IFORMFL_LOOPE_FIRST_DEFINED XED_IFORMFL_LOOPE_LAST_DEFINED XED_IFORMFL_LOOPNE_FIRST_DEFINED XED_IFORMFL_LOOPNE_LAST_DEFINED XED_IFORMFL_LOOP_FIRST_DEFINED XED_IFORMFL_LOOP_LAST_DEFINED XED_IFORMFL_LSL_FIRST_DEFINED XED_IFORMFL_LSL_LAST_DEFINED XED_IFORMFL_LSS_FIRST_DEFINED XED_IFORMFL_LSS_LAST_DEFINED XED_IFORMFL_LTR_FIRST_DEFINED XED_IFORMFL_LTR_LAST_DEFINED XED_IFORMFL_LWPINS_FIRST_DEFINED XED_IFORMFL_LWPINS_LAST_DEFINED XED_IFORMFL_LWPVAL_FIRST_DEFINED XED_IFORMFL_LWPVAL_LAST_DEFINED XED_IFORMFL_LZCNT_FIRST_DEFINED XED_IFORMFL_LZCNT_LAST_DEFINED XED_IFORMFL_MASKMOVDQU_FIRST_DEFINED XED_IFORMFL_MASKMOVDQU_LAST_DEFINED XED_IFORMFL_MASKMOVQ_FIRST_DEFINED XED_IFORMFL_MASKMOVQ_LAST_DEFINED XED_IFORMFL_MAXPD_FIRST_DEFINED XED_IFORMFL_MAXPD_LAST_DEFINED XED_IFORMFL_MAXPS_FIRST_DEFINED XED_IFORMFL_MAXPS_LAST_DEFINED XED_IFORMFL_MAXSD_FIRST_DEFINED XED_IFORMFL_MAXSD_LAST_DEFINED XED_IFORMFL_MAXSS_FIRST_DEFINED XED_IFORMFL_MAXSS_LAST_DEFINED XED_IFORMFL_MCOMMIT_FIRST_DEFINED XED_IFORMFL_MCOMMIT_LAST_DEFINED XED_IFORMFL_MFENCE_FIRST_DEFINED XED_IFORMFL_MFENCE_LAST_DEFINED XED_IFORMFL_MINPD_FIRST_DEFINED XED_IFORMFL_MINPD_LAST_DEFINED XED_IFORMFL_MINPS_FIRST_DEFINED XED_IFORMFL_MINPS_LAST_DEFINED XED_IFORMFL_MINSD_FIRST_DEFINED XED_IFORMFL_MINSD_LAST_DEFINED XED_IFORMFL_MINSS_FIRST_DEFINED XED_IFORMFL_MINSS_LAST_DEFINED XED_IFORMFL_MONITORX_FIRST_DEFINED XED_IFORMFL_MONITORX_LAST_DEFINED XED_IFORMFL_MONITOR_FIRST_DEFINED XED_IFORMFL_MONITOR_LAST_DEFINED XED_IFORMFL_MOVAPD_FIRST_DEFINED XED_IFORMFL_MOVAPD_LAST_DEFINED XED_IFORMFL_MOVAPS_FIRST_DEFINED XED_IFORMFL_MOVAPS_LAST_DEFINED XED_IFORMFL_MOVBE_FIRST_DEFINED XED_IFORMFL_MOVBE_LAST_DEFINED XED_IFORMFL_MOVDDUP_FIRST_DEFINED XED_IFORMFL_MOVDDUP_LAST_DEFINED XED_IFORMFL_MOVDIR64B_FIRST_DEFINED XED_IFORMFL_MOVDIR64B_LAST_DEFINED XED_IFORMFL_MOVDIRI_FIRST_DEFINED XED_IFORMFL_MOVDIRI_LAST_DEFINED XED_IFORMFL_MOVDQ2Q_FIRST_DEFINED XED_IFORMFL_MOVDQ2Q_LAST_DEFINED XED_IFORMFL_MOVDQA_FIRST_DEFINED XED_IFORMFL_MOVDQA_LAST_DEFINED XED_IFORMFL_MOVDQU_FIRST_DEFINED XED_IFORMFL_MOVDQU_LAST_DEFINED XED_IFORMFL_MOVD_FIRST_DEFINED XED_IFORMFL_MOVD_LAST_DEFINED XED_IFORMFL_MOVHLPS_FIRST_DEFINED XED_IFORMFL_MOVHLPS_LAST_DEFINED XED_IFORMFL_MOVHPD_FIRST_DEFINED XED_IFORMFL_MOVHPD_LAST_DEFINED XED_IFORMFL_MOVHPS_FIRST_DEFINED XED_IFORMFL_MOVHPS_LAST_DEFINED XED_IFORMFL_MOVLHPS_FIRST_DEFINED XED_IFORMFL_MOVLHPS_LAST_DEFINED XED_IFORMFL_MOVLPD_FIRST_DEFINED XED_IFORMFL_MOVLPD_LAST_DEFINED XED_IFORMFL_MOVLPS_FIRST_DEFINED XED_IFORMFL_MOVLPS_LAST_DEFINED XED_IFORMFL_MOVMSKPD_FIRST_DEFINED XED_IFORMFL_MOVMSKPD_LAST_DEFINED XED_IFORMFL_MOVMSKPS_FIRST_DEFINED XED_IFORMFL_MOVMSKPS_LAST_DEFINED XED_IFORMFL_MOVNTDQA_FIRST_DEFINED XED_IFORMFL_MOVNTDQA_LAST_DEFINED XED_IFORMFL_MOVNTDQ_FIRST_DEFINED XED_IFORMFL_MOVNTDQ_LAST_DEFINED XED_IFORMFL_MOVNTI_FIRST_DEFINED XED_IFORMFL_MOVNTI_LAST_DEFINED XED_IFORMFL_MOVNTPD_FIRST_DEFINED XED_IFORMFL_MOVNTPD_LAST_DEFINED XED_IFORMFL_MOVNTPS_FIRST_DEFINED XED_IFORMFL_MOVNTPS_LAST_DEFINED XED_IFORMFL_MOVNTQ_FIRST_DEFINED XED_IFORMFL_MOVNTQ_LAST_DEFINED XED_IFORMFL_MOVNTSD_FIRST_DEFINED XED_IFORMFL_MOVNTSD_LAST_DEFINED XED_IFORMFL_MOVNTSS_FIRST_DEFINED XED_IFORMFL_MOVNTSS_LAST_DEFINED XED_IFORMFL_MOVQ2DQ_FIRST_DEFINED XED_IFORMFL_MOVQ2DQ_LAST_DEFINED XED_IFORMFL_MOVQ_FIRST_DEFINED XED_IFORMFL_MOVQ_LAST_DEFINED XED_IFORMFL_MOVSB_FIRST_DEFINED XED_IFORMFL_MOVSB_LAST_DEFINED XED_IFORMFL_MOVSD_FIRST_DEFINED XED_IFORMFL_MOVSD_LAST_DEFINED XED_IFORMFL_MOVSD_XMM_FIRST_DEFINED XED_IFORMFL_MOVSD_XMM_LAST_DEFINED XED_IFORMFL_MOVSHDUP_FIRST_DEFINED XED_IFORMFL_MOVSHDUP_LAST_DEFINED XED_IFORMFL_MOVSLDUP_FIRST_DEFINED XED_IFORMFL_MOVSLDUP_LAST_DEFINED XED_IFORMFL_MOVSQ_FIRST_DEFINED XED_IFORMFL_MOVSQ_LAST_DEFINED XED_IFORMFL_MOVSS_FIRST_DEFINED XED_IFORMFL_MOVSS_LAST_DEFINED XED_IFORMFL_MOVSW_FIRST_DEFINED XED_IFORMFL_MOVSW_LAST_DEFINED XED_IFORMFL_MOVSXD_FIRST_DEFINED XED_IFORMFL_MOVSXD_LAST_DEFINED XED_IFORMFL_MOVSX_FIRST_DEFINED XED_IFORMFL_MOVSX_LAST_DEFINED XED_IFORMFL_MOVUPD_FIRST_DEFINED XED_IFORMFL_MOVUPD_LAST_DEFINED XED_IFORMFL_MOVUPS_FIRST_DEFINED XED_IFORMFL_MOVUPS_LAST_DEFINED XED_IFORMFL_MOVZX_FIRST_DEFINED XED_IFORMFL_MOVZX_LAST_DEFINED XED_IFORMFL_MOV_CR_FIRST_DEFINED XED_IFORMFL_MOV_CR_LAST_DEFINED XED_IFORMFL_MOV_DR_FIRST_DEFINED XED_IFORMFL_MOV_DR_LAST_DEFINED XED_IFORMFL_MOV_FIRST_DEFINED XED_IFORMFL_MOV_LAST_DEFINED XED_IFORMFL_MPSADBW_FIRST_DEFINED XED_IFORMFL_MPSADBW_LAST_DEFINED XED_IFORMFL_MULPD_FIRST_DEFINED XED_IFORMFL_MULPD_LAST_DEFINED XED_IFORMFL_MULPS_FIRST_DEFINED XED_IFORMFL_MULPS_LAST_DEFINED XED_IFORMFL_MULSD_FIRST_DEFINED XED_IFORMFL_MULSD_LAST_DEFINED XED_IFORMFL_MULSS_FIRST_DEFINED XED_IFORMFL_MULSS_LAST_DEFINED XED_IFORMFL_MULX_FIRST_DEFINED XED_IFORMFL_MULX_LAST_DEFINED XED_IFORMFL_MUL_FIRST_DEFINED XED_IFORMFL_MUL_LAST_DEFINED XED_IFORMFL_MWAITX_FIRST_DEFINED XED_IFORMFL_MWAITX_LAST_DEFINED XED_IFORMFL_MWAIT_FIRST_DEFINED XED_IFORMFL_MWAIT_LAST_DEFINED XED_IFORMFL_NEG_FIRST_DEFINED XED_IFORMFL_NEG_LAST_DEFINED XED_IFORMFL_NEG_LOCK_FIRST_DEFINED XED_IFORMFL_NEG_LOCK_LAST_DEFINED XED_IFORMFL_NOP_FIRST_DEFINED XED_IFORMFL_NOP_LAST_DEFINED XED_IFORMFL_NOT_FIRST_DEFINED XED_IFORMFL_NOT_LAST_DEFINED XED_IFORMFL_NOT_LOCK_FIRST_DEFINED XED_IFORMFL_NOT_LOCK_LAST_DEFINED XED_IFORMFL_ORPD_FIRST_DEFINED XED_IFORMFL_ORPD_LAST_DEFINED XED_IFORMFL_ORPS_FIRST_DEFINED XED_IFORMFL_ORPS_LAST_DEFINED XED_IFORMFL_OR_FIRST_DEFINED XED_IFORMFL_OR_LAST_DEFINED XED_IFORMFL_OR_LOCK_FIRST_DEFINED XED_IFORMFL_OR_LOCK_LAST_DEFINED XED_IFORMFL_OUTSB_FIRST_DEFINED XED_IFORMFL_OUTSB_LAST_DEFINED XED_IFORMFL_OUTSD_FIRST_DEFINED XED_IFORMFL_OUTSD_LAST_DEFINED XED_IFORMFL_OUTSW_FIRST_DEFINED XED_IFORMFL_OUTSW_LAST_DEFINED XED_IFORMFL_OUT_FIRST_DEFINED XED_IFORMFL_OUT_LAST_DEFINED XED_IFORMFL_PABSB_FIRST_DEFINED XED_IFORMFL_PABSB_LAST_DEFINED XED_IFORMFL_PABSD_FIRST_DEFINED XED_IFORMFL_PABSD_LAST_DEFINED XED_IFORMFL_PABSW_FIRST_DEFINED XED_IFORMFL_PABSW_LAST_DEFINED XED_IFORMFL_PACKSSDW_FIRST_DEFINED XED_IFORMFL_PACKSSDW_LAST_DEFINED XED_IFORMFL_PACKSSWB_FIRST_DEFINED XED_IFORMFL_PACKSSWB_LAST_DEFINED XED_IFORMFL_PACKUSDW_FIRST_DEFINED XED_IFORMFL_PACKUSDW_LAST_DEFINED XED_IFORMFL_PACKUSWB_FIRST_DEFINED XED_IFORMFL_PACKUSWB_LAST_DEFINED XED_IFORMFL_PADDB_FIRST_DEFINED XED_IFORMFL_PADDB_LAST_DEFINED XED_IFORMFL_PADDD_FIRST_DEFINED XED_IFORMFL_PADDD_LAST_DEFINED XED_IFORMFL_PADDQ_FIRST_DEFINED XED_IFORMFL_PADDQ_LAST_DEFINED XED_IFORMFL_PADDSB_FIRST_DEFINED XED_IFORMFL_PADDSB_LAST_DEFINED XED_IFORMFL_PADDSW_FIRST_DEFINED XED_IFORMFL_PADDSW_LAST_DEFINED XED_IFORMFL_PADDUSB_FIRST_DEFINED XED_IFORMFL_PADDUSB_LAST_DEFINED XED_IFORMFL_PADDUSW_FIRST_DEFINED XED_IFORMFL_PADDUSW_LAST_DEFINED XED_IFORMFL_PADDW_FIRST_DEFINED XED_IFORMFL_PADDW_LAST_DEFINED XED_IFORMFL_PALIGNR_FIRST_DEFINED XED_IFORMFL_PALIGNR_LAST_DEFINED XED_IFORMFL_PANDN_FIRST_DEFINED XED_IFORMFL_PANDN_LAST_DEFINED XED_IFORMFL_PAND_FIRST_DEFINED XED_IFORMFL_PAND_LAST_DEFINED XED_IFORMFL_PAUSE_FIRST_DEFINED XED_IFORMFL_PAUSE_LAST_DEFINED XED_IFORMFL_PAVGB_FIRST_DEFINED XED_IFORMFL_PAVGB_LAST_DEFINED XED_IFORMFL_PAVGUSB_FIRST_DEFINED XED_IFORMFL_PAVGUSB_LAST_DEFINED XED_IFORMFL_PAVGW_FIRST_DEFINED XED_IFORMFL_PAVGW_LAST_DEFINED XED_IFORMFL_PBLENDVB_FIRST_DEFINED XED_IFORMFL_PBLENDVB_LAST_DEFINED XED_IFORMFL_PBLENDW_FIRST_DEFINED XED_IFORMFL_PBLENDW_LAST_DEFINED XED_IFORMFL_PBNDKB_FIRST_DEFINED XED_IFORMFL_PBNDKB_LAST_DEFINED XED_IFORMFL_PCLMULQDQ_FIRST_DEFINED XED_IFORMFL_PCLMULQDQ_LAST_DEFINED XED_IFORMFL_PCMPEQB_FIRST_DEFINED XED_IFORMFL_PCMPEQB_LAST_DEFINED XED_IFORMFL_PCMPEQD_FIRST_DEFINED XED_IFORMFL_PCMPEQD_LAST_DEFINED XED_IFORMFL_PCMPEQQ_FIRST_DEFINED XED_IFORMFL_PCMPEQQ_LAST_DEFINED XED_IFORMFL_PCMPEQW_FIRST_DEFINED XED_IFORMFL_PCMPEQW_LAST_DEFINED XED_IFORMFL_PCMPESTRI64_FIRST_DEFINED XED_IFORMFL_PCMPESTRI64_LAST_DEFINED XED_IFORMFL_PCMPESTRI_FIRST_DEFINED XED_IFORMFL_PCMPESTRI_LAST_DEFINED XED_IFORMFL_PCMPESTRM64_FIRST_DEFINED XED_IFORMFL_PCMPESTRM64_LAST_DEFINED XED_IFORMFL_PCMPESTRM_FIRST_DEFINED XED_IFORMFL_PCMPESTRM_LAST_DEFINED XED_IFORMFL_PCMPGTB_FIRST_DEFINED XED_IFORMFL_PCMPGTB_LAST_DEFINED XED_IFORMFL_PCMPGTD_FIRST_DEFINED XED_IFORMFL_PCMPGTD_LAST_DEFINED XED_IFORMFL_PCMPGTQ_FIRST_DEFINED XED_IFORMFL_PCMPGTQ_LAST_DEFINED XED_IFORMFL_PCMPGTW_FIRST_DEFINED XED_IFORMFL_PCMPGTW_LAST_DEFINED XED_IFORMFL_PCMPISTRI64_FIRST_DEFINED XED_IFORMFL_PCMPISTRI64_LAST_DEFINED XED_IFORMFL_PCMPISTRI_FIRST_DEFINED XED_IFORMFL_PCMPISTRI_LAST_DEFINED XED_IFORMFL_PCMPISTRM_FIRST_DEFINED XED_IFORMFL_PCMPISTRM_LAST_DEFINED XED_IFORMFL_PCONFIG_FIRST_DEFINED XED_IFORMFL_PCONFIG_LAST_DEFINED XED_IFORMFL_PDEP_FIRST_DEFINED XED_IFORMFL_PDEP_LAST_DEFINED XED_IFORMFL_PEXTRB_FIRST_DEFINED XED_IFORMFL_PEXTRB_LAST_DEFINED XED_IFORMFL_PEXTRD_FIRST_DEFINED XED_IFORMFL_PEXTRD_LAST_DEFINED XED_IFORMFL_PEXTRQ_FIRST_DEFINED XED_IFORMFL_PEXTRQ_LAST_DEFINED XED_IFORMFL_PEXTRW_FIRST_DEFINED XED_IFORMFL_PEXTRW_LAST_DEFINED XED_IFORMFL_PEXTRW_SSE4_FIRST_DEFINED XED_IFORMFL_PEXTRW_SSE4_LAST_DEFINED XED_IFORMFL_PEXT_FIRST_DEFINED XED_IFORMFL_PEXT_LAST_DEFINED XED_IFORMFL_PF2ID_FIRST_DEFINED XED_IFORMFL_PF2ID_LAST_DEFINED XED_IFORMFL_PF2IW_FIRST_DEFINED XED_IFORMFL_PF2IW_LAST_DEFINED XED_IFORMFL_PFACC_FIRST_DEFINED XED_IFORMFL_PFACC_LAST_DEFINED XED_IFORMFL_PFADD_FIRST_DEFINED XED_IFORMFL_PFADD_LAST_DEFINED XED_IFORMFL_PFCMPEQ_FIRST_DEFINED XED_IFORMFL_PFCMPEQ_LAST_DEFINED XED_IFORMFL_PFCMPGE_FIRST_DEFINED XED_IFORMFL_PFCMPGE_LAST_DEFINED XED_IFORMFL_PFCMPGT_FIRST_DEFINED XED_IFORMFL_PFCMPGT_LAST_DEFINED XED_IFORMFL_PFMAX_FIRST_DEFINED XED_IFORMFL_PFMAX_LAST_DEFINED XED_IFORMFL_PFMIN_FIRST_DEFINED XED_IFORMFL_PFMIN_LAST_DEFINED XED_IFORMFL_PFMUL_FIRST_DEFINED XED_IFORMFL_PFMUL_LAST_DEFINED XED_IFORMFL_PFNACC_FIRST_DEFINED XED_IFORMFL_PFNACC_LAST_DEFINED XED_IFORMFL_PFPNACC_FIRST_DEFINED XED_IFORMFL_PFPNACC_LAST_DEFINED XED_IFORMFL_PFRCPIT1_FIRST_DEFINED XED_IFORMFL_PFRCPIT1_LAST_DEFINED XED_IFORMFL_PFRCPIT2_FIRST_DEFINED XED_IFORMFL_PFRCPIT2_LAST_DEFINED XED_IFORMFL_PFRCP_FIRST_DEFINED XED_IFORMFL_PFRCP_LAST_DEFINED XED_IFORMFL_PFRSQIT1_FIRST_DEFINED XED_IFORMFL_PFRSQIT1_LAST_DEFINED XED_IFORMFL_PFRSQRT_FIRST_DEFINED XED_IFORMFL_PFRSQRT_LAST_DEFINED XED_IFORMFL_PFSUBR_FIRST_DEFINED XED_IFORMFL_PFSUBR_LAST_DEFINED XED_IFORMFL_PFSUB_FIRST_DEFINED XED_IFORMFL_PFSUB_LAST_DEFINED XED_IFORMFL_PHADDD_FIRST_DEFINED XED_IFORMFL_PHADDD_LAST_DEFINED XED_IFORMFL_PHADDSW_FIRST_DEFINED XED_IFORMFL_PHADDSW_LAST_DEFINED XED_IFORMFL_PHADDW_FIRST_DEFINED XED_IFORMFL_PHADDW_LAST_DEFINED XED_IFORMFL_PHMINPOSUW_FIRST_DEFINED XED_IFORMFL_PHMINPOSUW_LAST_DEFINED XED_IFORMFL_PHSUBD_FIRST_DEFINED XED_IFORMFL_PHSUBD_LAST_DEFINED XED_IFORMFL_PHSUBSW_FIRST_DEFINED XED_IFORMFL_PHSUBSW_LAST_DEFINED XED_IFORMFL_PHSUBW_FIRST_DEFINED XED_IFORMFL_PHSUBW_LAST_DEFINED XED_IFORMFL_PI2FD_FIRST_DEFINED XED_IFORMFL_PI2FD_LAST_DEFINED XED_IFORMFL_PI2FW_FIRST_DEFINED XED_IFORMFL_PI2FW_LAST_DEFINED XED_IFORMFL_PINSRB_FIRST_DEFINED XED_IFORMFL_PINSRB_LAST_DEFINED XED_IFORMFL_PINSRD_FIRST_DEFINED XED_IFORMFL_PINSRD_LAST_DEFINED XED_IFORMFL_PINSRQ_FIRST_DEFINED XED_IFORMFL_PINSRQ_LAST_DEFINED XED_IFORMFL_PINSRW_FIRST_DEFINED XED_IFORMFL_PINSRW_LAST_DEFINED XED_IFORMFL_PMADDUBSW_FIRST_DEFINED XED_IFORMFL_PMADDUBSW_LAST_DEFINED XED_IFORMFL_PMADDWD_FIRST_DEFINED XED_IFORMFL_PMADDWD_LAST_DEFINED XED_IFORMFL_PMAXSB_FIRST_DEFINED XED_IFORMFL_PMAXSB_LAST_DEFINED XED_IFORMFL_PMAXSD_FIRST_DEFINED XED_IFORMFL_PMAXSD_LAST_DEFINED XED_IFORMFL_PMAXSW_FIRST_DEFINED XED_IFORMFL_PMAXSW_LAST_DEFINED XED_IFORMFL_PMAXUB_FIRST_DEFINED XED_IFORMFL_PMAXUB_LAST_DEFINED XED_IFORMFL_PMAXUD_FIRST_DEFINED XED_IFORMFL_PMAXUD_LAST_DEFINED XED_IFORMFL_PMAXUW_FIRST_DEFINED XED_IFORMFL_PMAXUW_LAST_DEFINED XED_IFORMFL_PMINSB_FIRST_DEFINED XED_IFORMFL_PMINSB_LAST_DEFINED XED_IFORMFL_PMINSD_FIRST_DEFINED XED_IFORMFL_PMINSD_LAST_DEFINED XED_IFORMFL_PMINSW_FIRST_DEFINED XED_IFORMFL_PMINSW_LAST_DEFINED XED_IFORMFL_PMINUB_FIRST_DEFINED XED_IFORMFL_PMINUB_LAST_DEFINED XED_IFORMFL_PMINUD_FIRST_DEFINED XED_IFORMFL_PMINUD_LAST_DEFINED XED_IFORMFL_PMINUW_FIRST_DEFINED XED_IFORMFL_PMINUW_LAST_DEFINED XED_IFORMFL_PMOVMSKB_FIRST_DEFINED XED_IFORMFL_PMOVMSKB_LAST_DEFINED XED_IFORMFL_PMOVSXBD_FIRST_DEFINED XED_IFORMFL_PMOVSXBD_LAST_DEFINED XED_IFORMFL_PMOVSXBQ_FIRST_DEFINED XED_IFORMFL_PMOVSXBQ_LAST_DEFINED XED_IFORMFL_PMOVSXBW_FIRST_DEFINED XED_IFORMFL_PMOVSXBW_LAST_DEFINED XED_IFORMFL_PMOVSXDQ_FIRST_DEFINED XED_IFORMFL_PMOVSXDQ_LAST_DEFINED XED_IFORMFL_PMOVSXWD_FIRST_DEFINED XED_IFORMFL_PMOVSXWD_LAST_DEFINED XED_IFORMFL_PMOVSXWQ_FIRST_DEFINED XED_IFORMFL_PMOVSXWQ_LAST_DEFINED XED_IFORMFL_PMOVZXBD_FIRST_DEFINED XED_IFORMFL_PMOVZXBD_LAST_DEFINED XED_IFORMFL_PMOVZXBQ_FIRST_DEFINED XED_IFORMFL_PMOVZXBQ_LAST_DEFINED XED_IFORMFL_PMOVZXBW_FIRST_DEFINED XED_IFORMFL_PMOVZXBW_LAST_DEFINED XED_IFORMFL_PMOVZXDQ_FIRST_DEFINED XED_IFORMFL_PMOVZXDQ_LAST_DEFINED XED_IFORMFL_PMOVZXWD_FIRST_DEFINED XED_IFORMFL_PMOVZXWD_LAST_DEFINED XED_IFORMFL_PMOVZXWQ_FIRST_DEFINED XED_IFORMFL_PMOVZXWQ_LAST_DEFINED XED_IFORMFL_PMULDQ_FIRST_DEFINED XED_IFORMFL_PMULDQ_LAST_DEFINED XED_IFORMFL_PMULHRSW_FIRST_DEFINED XED_IFORMFL_PMULHRSW_LAST_DEFINED XED_IFORMFL_PMULHRW_FIRST_DEFINED XED_IFORMFL_PMULHRW_LAST_DEFINED XED_IFORMFL_PMULHUW_FIRST_DEFINED XED_IFORMFL_PMULHUW_LAST_DEFINED XED_IFORMFL_PMULHW_FIRST_DEFINED XED_IFORMFL_PMULHW_LAST_DEFINED XED_IFORMFL_PMULLD_FIRST_DEFINED XED_IFORMFL_PMULLD_LAST_DEFINED XED_IFORMFL_PMULLW_FIRST_DEFINED XED_IFORMFL_PMULLW_LAST_DEFINED XED_IFORMFL_PMULUDQ_FIRST_DEFINED XED_IFORMFL_PMULUDQ_LAST_DEFINED XED_IFORMFL_POP2P_FIRST_DEFINED XED_IFORMFL_POP2P_LAST_DEFINED XED_IFORMFL_POP2_FIRST_DEFINED XED_IFORMFL_POP2_LAST_DEFINED XED_IFORMFL_POPAD_FIRST_DEFINED XED_IFORMFL_POPAD_LAST_DEFINED XED_IFORMFL_POPA_FIRST_DEFINED XED_IFORMFL_POPA_LAST_DEFINED XED_IFORMFL_POPCNT_FIRST_DEFINED XED_IFORMFL_POPCNT_LAST_DEFINED XED_IFORMFL_POPFD_FIRST_DEFINED XED_IFORMFL_POPFD_LAST_DEFINED XED_IFORMFL_POPFQ_FIRST_DEFINED XED_IFORMFL_POPFQ_LAST_DEFINED XED_IFORMFL_POPF_FIRST_DEFINED XED_IFORMFL_POPF_LAST_DEFINED XED_IFORMFL_POPP_FIRST_DEFINED XED_IFORMFL_POPP_LAST_DEFINED XED_IFORMFL_POP_FIRST_DEFINED XED_IFORMFL_POP_LAST_DEFINED XED_IFORMFL_POR_FIRST_DEFINED XED_IFORMFL_POR_LAST_DEFINED XED_IFORMFL_PREFETCHIT0_FIRST_DEFINED XED_IFORMFL_PREFETCHIT0_LAST_DEFINED XED_IFORMFL_PREFETCHIT1_FIRST_DEFINED XED_IFORMFL_PREFETCHIT1_LAST_DEFINED XED_IFORMFL_PREFETCHNTA_FIRST_DEFINED XED_IFORMFL_PREFETCHNTA_LAST_DEFINED XED_IFORMFL_PREFETCHT0_FIRST_DEFINED XED_IFORMFL_PREFETCHT0_LAST_DEFINED XED_IFORMFL_PREFETCHT1_FIRST_DEFINED XED_IFORMFL_PREFETCHT1_LAST_DEFINED XED_IFORMFL_PREFETCHT2_FIRST_DEFINED XED_IFORMFL_PREFETCHT2_LAST_DEFINED XED_IFORMFL_PREFETCHWT1_FIRST_DEFINED XED_IFORMFL_PREFETCHWT1_LAST_DEFINED XED_IFORMFL_PREFETCHW_FIRST_DEFINED XED_IFORMFL_PREFETCHW_LAST_DEFINED XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST_DEFINED XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST_DEFINED XED_IFORMFL_PREFETCH_RESERVED_FIRST_DEFINED XED_IFORMFL_PREFETCH_RESERVED_LAST_DEFINED XED_IFORMFL_PSADBW_FIRST_DEFINED XED_IFORMFL_PSADBW_LAST_DEFINED XED_IFORMFL_PSHUFB_FIRST_DEFINED XED_IFORMFL_PSHUFB_LAST_DEFINED XED_IFORMFL_PSHUFD_FIRST_DEFINED XED_IFORMFL_PSHUFD_LAST_DEFINED XED_IFORMFL_PSHUFHW_FIRST_DEFINED XED_IFORMFL_PSHUFHW_LAST_DEFINED XED_IFORMFL_PSHUFLW_FIRST_DEFINED XED_IFORMFL_PSHUFLW_LAST_DEFINED XED_IFORMFL_PSHUFW_FIRST_DEFINED XED_IFORMFL_PSHUFW_LAST_DEFINED XED_IFORMFL_PSIGNB_FIRST_DEFINED XED_IFORMFL_PSIGNB_LAST_DEFINED XED_IFORMFL_PSIGND_FIRST_DEFINED XED_IFORMFL_PSIGND_LAST_DEFINED XED_IFORMFL_PSIGNW_FIRST_DEFINED XED_IFORMFL_PSIGNW_LAST_DEFINED XED_IFORMFL_PSLLDQ_FIRST_DEFINED XED_IFORMFL_PSLLDQ_LAST_DEFINED XED_IFORMFL_PSLLD_FIRST_DEFINED XED_IFORMFL_PSLLD_LAST_DEFINED XED_IFORMFL_PSLLQ_FIRST_DEFINED XED_IFORMFL_PSLLQ_LAST_DEFINED XED_IFORMFL_PSLLW_FIRST_DEFINED XED_IFORMFL_PSLLW_LAST_DEFINED XED_IFORMFL_PSMASH_FIRST_DEFINED XED_IFORMFL_PSMASH_LAST_DEFINED XED_IFORMFL_PSRAD_FIRST_DEFINED XED_IFORMFL_PSRAD_LAST_DEFINED XED_IFORMFL_PSRAW_FIRST_DEFINED XED_IFORMFL_PSRAW_LAST_DEFINED XED_IFORMFL_PSRLDQ_FIRST_DEFINED XED_IFORMFL_PSRLDQ_LAST_DEFINED XED_IFORMFL_PSRLD_FIRST_DEFINED XED_IFORMFL_PSRLD_LAST_DEFINED XED_IFORMFL_PSRLQ_FIRST_DEFINED XED_IFORMFL_PSRLQ_LAST_DEFINED XED_IFORMFL_PSRLW_FIRST_DEFINED XED_IFORMFL_PSRLW_LAST_DEFINED XED_IFORMFL_PSUBB_FIRST_DEFINED XED_IFORMFL_PSUBB_LAST_DEFINED XED_IFORMFL_PSUBD_FIRST_DEFINED XED_IFORMFL_PSUBD_LAST_DEFINED XED_IFORMFL_PSUBQ_FIRST_DEFINED XED_IFORMFL_PSUBQ_LAST_DEFINED XED_IFORMFL_PSUBSB_FIRST_DEFINED XED_IFORMFL_PSUBSB_LAST_DEFINED XED_IFORMFL_PSUBSW_FIRST_DEFINED XED_IFORMFL_PSUBSW_LAST_DEFINED XED_IFORMFL_PSUBUSB_FIRST_DEFINED XED_IFORMFL_PSUBUSB_LAST_DEFINED XED_IFORMFL_PSUBUSW_FIRST_DEFINED XED_IFORMFL_PSUBUSW_LAST_DEFINED XED_IFORMFL_PSUBW_FIRST_DEFINED XED_IFORMFL_PSUBW_LAST_DEFINED XED_IFORMFL_PSWAPD_FIRST_DEFINED XED_IFORMFL_PSWAPD_LAST_DEFINED XED_IFORMFL_PTEST_FIRST_DEFINED XED_IFORMFL_PTEST_LAST_DEFINED XED_IFORMFL_PTWRITE_FIRST_DEFINED XED_IFORMFL_PTWRITE_LAST_DEFINED XED_IFORMFL_PUNPCKHBW_FIRST_DEFINED XED_IFORMFL_PUNPCKHBW_LAST_DEFINED XED_IFORMFL_PUNPCKHDQ_FIRST_DEFINED XED_IFORMFL_PUNPCKHDQ_LAST_DEFINED XED_IFORMFL_PUNPCKHQDQ_FIRST_DEFINED XED_IFORMFL_PUNPCKHQDQ_LAST_DEFINED XED_IFORMFL_PUNPCKHWD_FIRST_DEFINED XED_IFORMFL_PUNPCKHWD_LAST_DEFINED XED_IFORMFL_PUNPCKLBW_FIRST_DEFINED XED_IFORMFL_PUNPCKLBW_LAST_DEFINED XED_IFORMFL_PUNPCKLDQ_FIRST_DEFINED XED_IFORMFL_PUNPCKLDQ_LAST_DEFINED XED_IFORMFL_PUNPCKLQDQ_FIRST_DEFINED XED_IFORMFL_PUNPCKLQDQ_LAST_DEFINED XED_IFORMFL_PUNPCKLWD_FIRST_DEFINED XED_IFORMFL_PUNPCKLWD_LAST_DEFINED XED_IFORMFL_PUSH2P_FIRST_DEFINED XED_IFORMFL_PUSH2P_LAST_DEFINED XED_IFORMFL_PUSH2_FIRST_DEFINED XED_IFORMFL_PUSH2_LAST_DEFINED XED_IFORMFL_PUSHAD_FIRST_DEFINED XED_IFORMFL_PUSHAD_LAST_DEFINED XED_IFORMFL_PUSHA_FIRST_DEFINED XED_IFORMFL_PUSHA_LAST_DEFINED XED_IFORMFL_PUSHFD_FIRST_DEFINED XED_IFORMFL_PUSHFD_LAST_DEFINED XED_IFORMFL_PUSHFQ_FIRST_DEFINED XED_IFORMFL_PUSHFQ_LAST_DEFINED XED_IFORMFL_PUSHF_FIRST_DEFINED XED_IFORMFL_PUSHF_LAST_DEFINED XED_IFORMFL_PUSHP_FIRST_DEFINED XED_IFORMFL_PUSHP_LAST_DEFINED XED_IFORMFL_PUSH_FIRST_DEFINED XED_IFORMFL_PUSH_LAST_DEFINED XED_IFORMFL_PVALIDATE_FIRST_DEFINED XED_IFORMFL_PVALIDATE_LAST_DEFINED XED_IFORMFL_PXOR_FIRST_DEFINED XED_IFORMFL_PXOR_LAST_DEFINED XED_IFORMFL_RCL_FIRST_DEFINED XED_IFORMFL_RCL_LAST_DEFINED XED_IFORMFL_RCPPS_FIRST_DEFINED XED_IFORMFL_RCPPS_LAST_DEFINED XED_IFORMFL_RCPSS_FIRST_DEFINED XED_IFORMFL_RCPSS_LAST_DEFINED XED_IFORMFL_RCR_FIRST_DEFINED XED_IFORMFL_RCR_LAST_DEFINED XED_IFORMFL_RDFSBASE_FIRST_DEFINED XED_IFORMFL_RDFSBASE_LAST_DEFINED XED_IFORMFL_RDGSBASE_FIRST_DEFINED XED_IFORMFL_RDGSBASE_LAST_DEFINED XED_IFORMFL_RDMSRLIST_FIRST_DEFINED XED_IFORMFL_RDMSRLIST_LAST_DEFINED XED_IFORMFL_RDMSR_FIRST_DEFINED XED_IFORMFL_RDMSR_LAST_DEFINED XED_IFORMFL_RDPID_FIRST_DEFINED XED_IFORMFL_RDPID_LAST_DEFINED XED_IFORMFL_RDPKRU_FIRST_DEFINED XED_IFORMFL_RDPKRU_LAST_DEFINED XED_IFORMFL_RDPMC_FIRST_DEFINED XED_IFORMFL_RDPMC_LAST_DEFINED XED_IFORMFL_RDPRU_FIRST_DEFINED XED_IFORMFL_RDPRU_LAST_DEFINED XED_IFORMFL_RDRAND_FIRST_DEFINED XED_IFORMFL_RDRAND_LAST_DEFINED XED_IFORMFL_RDSEED_FIRST_DEFINED XED_IFORMFL_RDSEED_LAST_DEFINED XED_IFORMFL_RDSSPD_FIRST_DEFINED XED_IFORMFL_RDSSPD_LAST_DEFINED XED_IFORMFL_RDSSPQ_FIRST_DEFINED XED_IFORMFL_RDSSPQ_LAST_DEFINED XED_IFORMFL_RDTSCP_FIRST_DEFINED XED_IFORMFL_RDTSCP_LAST_DEFINED XED_IFORMFL_RDTSC_FIRST_DEFINED XED_IFORMFL_RDTSC_LAST_DEFINED XED_IFORMFL_REPE_CMPSB_FIRST_DEFINED XED_IFORMFL_REPE_CMPSB_LAST_DEFINED XED_IFORMFL_REPE_CMPSD_FIRST_DEFINED XED_IFORMFL_REPE_CMPSD_LAST_DEFINED XED_IFORMFL_REPE_CMPSQ_FIRST_DEFINED XED_IFORMFL_REPE_CMPSQ_LAST_DEFINED XED_IFORMFL_REPE_CMPSW_FIRST_DEFINED XED_IFORMFL_REPE_CMPSW_LAST_DEFINED XED_IFORMFL_REPE_SCASB_FIRST_DEFINED XED_IFORMFL_REPE_SCASB_LAST_DEFINED XED_IFORMFL_REPE_SCASD_FIRST_DEFINED XED_IFORMFL_REPE_SCASD_LAST_DEFINED XED_IFORMFL_REPE_SCASQ_FIRST_DEFINED XED_IFORMFL_REPE_SCASQ_LAST_DEFINED XED_IFORMFL_REPE_SCASW_FIRST_DEFINED XED_IFORMFL_REPE_SCASW_LAST_DEFINED XED_IFORMFL_REPNE_CMPSB_FIRST_DEFINED XED_IFORMFL_REPNE_CMPSB_LAST_DEFINED XED_IFORMFL_REPNE_CMPSD_FIRST_DEFINED XED_IFORMFL_REPNE_CMPSD_LAST_DEFINED XED_IFORMFL_REPNE_CMPSQ_FIRST_DEFINED XED_IFORMFL_REPNE_CMPSQ_LAST_DEFINED XED_IFORMFL_REPNE_CMPSW_FIRST_DEFINED XED_IFORMFL_REPNE_CMPSW_LAST_DEFINED XED_IFORMFL_REPNE_SCASB_FIRST_DEFINED XED_IFORMFL_REPNE_SCASB_LAST_DEFINED XED_IFORMFL_REPNE_SCASD_FIRST_DEFINED XED_IFORMFL_REPNE_SCASD_LAST_DEFINED XED_IFORMFL_REPNE_SCASQ_FIRST_DEFINED XED_IFORMFL_REPNE_SCASQ_LAST_DEFINED XED_IFORMFL_REPNE_SCASW_FIRST_DEFINED XED_IFORMFL_REPNE_SCASW_LAST_DEFINED XED_IFORMFL_REP_INSB_FIRST_DEFINED XED_IFORMFL_REP_INSB_LAST_DEFINED XED_IFORMFL_REP_INSD_FIRST_DEFINED XED_IFORMFL_REP_INSD_LAST_DEFINED XED_IFORMFL_REP_INSW_FIRST_DEFINED XED_IFORMFL_REP_INSW_LAST_DEFINED XED_IFORMFL_REP_LODSB_FIRST_DEFINED XED_IFORMFL_REP_LODSB_LAST_DEFINED XED_IFORMFL_REP_LODSD_FIRST_DEFINED XED_IFORMFL_REP_LODSD_LAST_DEFINED XED_IFORMFL_REP_LODSQ_FIRST_DEFINED XED_IFORMFL_REP_LODSQ_LAST_DEFINED XED_IFORMFL_REP_LODSW_FIRST_DEFINED XED_IFORMFL_REP_LODSW_LAST_DEFINED XED_IFORMFL_REP_MONTMUL_FIRST_DEFINED XED_IFORMFL_REP_MONTMUL_LAST_DEFINED XED_IFORMFL_REP_MOVSB_FIRST_DEFINED XED_IFORMFL_REP_MOVSB_LAST_DEFINED XED_IFORMFL_REP_MOVSD_FIRST_DEFINED XED_IFORMFL_REP_MOVSD_LAST_DEFINED XED_IFORMFL_REP_MOVSQ_FIRST_DEFINED XED_IFORMFL_REP_MOVSQ_LAST_DEFINED XED_IFORMFL_REP_MOVSW_FIRST_DEFINED XED_IFORMFL_REP_MOVSW_LAST_DEFINED XED_IFORMFL_REP_OUTSB_FIRST_DEFINED XED_IFORMFL_REP_OUTSB_LAST_DEFINED XED_IFORMFL_REP_OUTSD_FIRST_DEFINED XED_IFORMFL_REP_OUTSD_LAST_DEFINED XED_IFORMFL_REP_OUTSW_FIRST_DEFINED XED_IFORMFL_REP_OUTSW_LAST_DEFINED XED_IFORMFL_REP_STOSB_FIRST_DEFINED XED_IFORMFL_REP_STOSB_LAST_DEFINED XED_IFORMFL_REP_STOSD_FIRST_DEFINED XED_IFORMFL_REP_STOSD_LAST_DEFINED XED_IFORMFL_REP_STOSQ_FIRST_DEFINED XED_IFORMFL_REP_STOSQ_LAST_DEFINED XED_IFORMFL_REP_STOSW_FIRST_DEFINED XED_IFORMFL_REP_STOSW_LAST_DEFINED XED_IFORMFL_REP_XCRYPTCBC_FIRST_DEFINED XED_IFORMFL_REP_XCRYPTCBC_LAST_DEFINED XED_IFORMFL_REP_XCRYPTCFB_FIRST_DEFINED XED_IFORMFL_REP_XCRYPTCFB_LAST_DEFINED XED_IFORMFL_REP_XCRYPTCTR_FIRST_DEFINED XED_IFORMFL_REP_XCRYPTCTR_LAST_DEFINED XED_IFORMFL_REP_XCRYPTECB_FIRST_DEFINED XED_IFORMFL_REP_XCRYPTECB_LAST_DEFINED XED_IFORMFL_REP_XCRYPTOFB_FIRST_DEFINED XED_IFORMFL_REP_XCRYPTOFB_LAST_DEFINED XED_IFORMFL_REP_XSHA1_FIRST_DEFINED XED_IFORMFL_REP_XSHA1_LAST_DEFINED XED_IFORMFL_REP_XSHA256_FIRST_DEFINED XED_IFORMFL_REP_XSHA256_LAST_DEFINED XED_IFORMFL_REP_XSTORE_FIRST_DEFINED XED_IFORMFL_REP_XSTORE_LAST_DEFINED XED_IFORMFL_RET_FAR_FIRST_DEFINED XED_IFORMFL_RET_FAR_LAST_DEFINED XED_IFORMFL_RET_NEAR_FIRST_DEFINED XED_IFORMFL_RET_NEAR_LAST_DEFINED XED_IFORMFL_RMPADJUST_FIRST_DEFINED XED_IFORMFL_RMPADJUST_LAST_DEFINED XED_IFORMFL_RMPUPDATE_FIRST_DEFINED XED_IFORMFL_RMPUPDATE_LAST_DEFINED XED_IFORMFL_ROL_FIRST_DEFINED XED_IFORMFL_ROL_LAST_DEFINED XED_IFORMFL_RORX_FIRST_DEFINED XED_IFORMFL_RORX_LAST_DEFINED XED_IFORMFL_ROR_FIRST_DEFINED XED_IFORMFL_ROR_LAST_DEFINED XED_IFORMFL_ROUNDPD_FIRST_DEFINED XED_IFORMFL_ROUNDPD_LAST_DEFINED XED_IFORMFL_ROUNDPS_FIRST_DEFINED XED_IFORMFL_ROUNDPS_LAST_DEFINED XED_IFORMFL_ROUNDSD_FIRST_DEFINED XED_IFORMFL_ROUNDSD_LAST_DEFINED XED_IFORMFL_ROUNDSS_FIRST_DEFINED XED_IFORMFL_ROUNDSS_LAST_DEFINED XED_IFORMFL_RSM_FIRST_DEFINED XED_IFORMFL_RSM_LAST_DEFINED XED_IFORMFL_RSQRTPS_FIRST_DEFINED XED_IFORMFL_RSQRTPS_LAST_DEFINED XED_IFORMFL_RSQRTSS_FIRST_DEFINED XED_IFORMFL_RSQRTSS_LAST_DEFINED XED_IFORMFL_RSTORSSP_FIRST_DEFINED XED_IFORMFL_RSTORSSP_LAST_DEFINED XED_IFORMFL_SAHF_FIRST_DEFINED XED_IFORMFL_SAHF_LAST_DEFINED XED_IFORMFL_SALC_FIRST_DEFINED XED_IFORMFL_SALC_LAST_DEFINED XED_IFORMFL_SARX_FIRST_DEFINED XED_IFORMFL_SARX_LAST_DEFINED XED_IFORMFL_SAR_FIRST_DEFINED XED_IFORMFL_SAR_LAST_DEFINED XED_IFORMFL_SAVEPREVSSP_FIRST_DEFINED XED_IFORMFL_SAVEPREVSSP_LAST_DEFINED XED_IFORMFL_SBB_FIRST_DEFINED XED_IFORMFL_SBB_LAST_DEFINED XED_IFORMFL_SBB_LOCK_FIRST_DEFINED XED_IFORMFL_SBB_LOCK_LAST_DEFINED XED_IFORMFL_SCASB_FIRST_DEFINED XED_IFORMFL_SCASB_LAST_DEFINED XED_IFORMFL_SCASD_FIRST_DEFINED XED_IFORMFL_SCASD_LAST_DEFINED XED_IFORMFL_SCASQ_FIRST_DEFINED XED_IFORMFL_SCASQ_LAST_DEFINED XED_IFORMFL_SCASW_FIRST_DEFINED XED_IFORMFL_SCASW_LAST_DEFINED XED_IFORMFL_SEAMCALL_FIRST_DEFINED XED_IFORMFL_SEAMCALL_LAST_DEFINED XED_IFORMFL_SEAMOPS_FIRST_DEFINED XED_IFORMFL_SEAMOPS_LAST_DEFINED XED_IFORMFL_SEAMRET_FIRST_DEFINED XED_IFORMFL_SEAMRET_LAST_DEFINED XED_IFORMFL_SENDUIPI_FIRST_DEFINED XED_IFORMFL_SENDUIPI_LAST_DEFINED XED_IFORMFL_SERIALIZE_FIRST_DEFINED XED_IFORMFL_SERIALIZE_LAST_DEFINED XED_IFORMFL_SETBE_FIRST_DEFINED XED_IFORMFL_SETBE_LAST_DEFINED XED_IFORMFL_SETB_FIRST_DEFINED XED_IFORMFL_SETB_LAST_DEFINED XED_IFORMFL_SETLE_FIRST_DEFINED XED_IFORMFL_SETLE_LAST_DEFINED XED_IFORMFL_SETL_FIRST_DEFINED XED_IFORMFL_SETL_LAST_DEFINED XED_IFORMFL_SETNBE_FIRST_DEFINED XED_IFORMFL_SETNBE_LAST_DEFINED XED_IFORMFL_SETNB_FIRST_DEFINED XED_IFORMFL_SETNB_LAST_DEFINED XED_IFORMFL_SETNLE_FIRST_DEFINED XED_IFORMFL_SETNLE_LAST_DEFINED XED_IFORMFL_SETNL_FIRST_DEFINED XED_IFORMFL_SETNL_LAST_DEFINED XED_IFORMFL_SETNO_FIRST_DEFINED XED_IFORMFL_SETNO_LAST_DEFINED XED_IFORMFL_SETNP_FIRST_DEFINED XED_IFORMFL_SETNP_LAST_DEFINED XED_IFORMFL_SETNS_FIRST_DEFINED XED_IFORMFL_SETNS_LAST_DEFINED XED_IFORMFL_SETNZ_FIRST_DEFINED XED_IFORMFL_SETNZ_LAST_DEFINED XED_IFORMFL_SETO_FIRST_DEFINED XED_IFORMFL_SETO_LAST_DEFINED XED_IFORMFL_SETP_FIRST_DEFINED XED_IFORMFL_SETP_LAST_DEFINED XED_IFORMFL_SETSSBSY_FIRST_DEFINED XED_IFORMFL_SETSSBSY_LAST_DEFINED XED_IFORMFL_SETS_FIRST_DEFINED XED_IFORMFL_SETS_LAST_DEFINED XED_IFORMFL_SETZ_FIRST_DEFINED XED_IFORMFL_SETZ_LAST_DEFINED XED_IFORMFL_SFENCE_FIRST_DEFINED XED_IFORMFL_SFENCE_LAST_DEFINED XED_IFORMFL_SGDT_FIRST_DEFINED XED_IFORMFL_SGDT_LAST_DEFINED XED_IFORMFL_SHA1MSG1_FIRST_DEFINED XED_IFORMFL_SHA1MSG1_LAST_DEFINED XED_IFORMFL_SHA1MSG2_FIRST_DEFINED XED_IFORMFL_SHA1MSG2_LAST_DEFINED XED_IFORMFL_SHA1NEXTE_FIRST_DEFINED XED_IFORMFL_SHA1NEXTE_LAST_DEFINED XED_IFORMFL_SHA1RNDS4_FIRST_DEFINED XED_IFORMFL_SHA1RNDS4_LAST_DEFINED XED_IFORMFL_SHA256MSG1_FIRST_DEFINED XED_IFORMFL_SHA256MSG1_LAST_DEFINED XED_IFORMFL_SHA256MSG2_FIRST_DEFINED XED_IFORMFL_SHA256MSG2_LAST_DEFINED XED_IFORMFL_SHA256RNDS2_FIRST_DEFINED XED_IFORMFL_SHA256RNDS2_LAST_DEFINED XED_IFORMFL_SHLD_FIRST_DEFINED XED_IFORMFL_SHLD_LAST_DEFINED XED_IFORMFL_SHLX_FIRST_DEFINED XED_IFORMFL_SHLX_LAST_DEFINED XED_IFORMFL_SHL_FIRST_DEFINED XED_IFORMFL_SHL_LAST_DEFINED XED_IFORMFL_SHRD_FIRST_DEFINED XED_IFORMFL_SHRD_LAST_DEFINED XED_IFORMFL_SHRX_FIRST_DEFINED XED_IFORMFL_SHRX_LAST_DEFINED XED_IFORMFL_SHR_FIRST_DEFINED XED_IFORMFL_SHR_LAST_DEFINED XED_IFORMFL_SHUFPD_FIRST_DEFINED XED_IFORMFL_SHUFPD_LAST_DEFINED XED_IFORMFL_SHUFPS_FIRST_DEFINED XED_IFORMFL_SHUFPS_LAST_DEFINED XED_IFORMFL_SIDT_FIRST_DEFINED XED_IFORMFL_SIDT_LAST_DEFINED XED_IFORMFL_SKINIT_FIRST_DEFINED XED_IFORMFL_SKINIT_LAST_DEFINED XED_IFORMFL_SLDT_FIRST_DEFINED XED_IFORMFL_SLDT_LAST_DEFINED XED_IFORMFL_SLWPCB_FIRST_DEFINED XED_IFORMFL_SLWPCB_LAST_DEFINED XED_IFORMFL_SMSW_FIRST_DEFINED XED_IFORMFL_SMSW_LAST_DEFINED XED_IFORMFL_SQRTPD_FIRST_DEFINED XED_IFORMFL_SQRTPD_LAST_DEFINED XED_IFORMFL_SQRTPS_FIRST_DEFINED XED_IFORMFL_SQRTPS_LAST_DEFINED XED_IFORMFL_SQRTSD_FIRST_DEFINED XED_IFORMFL_SQRTSD_LAST_DEFINED XED_IFORMFL_SQRTSS_FIRST_DEFINED XED_IFORMFL_SQRTSS_LAST_DEFINED XED_IFORMFL_STAC_FIRST_DEFINED XED_IFORMFL_STAC_LAST_DEFINED XED_IFORMFL_STC_FIRST_DEFINED XED_IFORMFL_STC_LAST_DEFINED XED_IFORMFL_STD_FIRST_DEFINED XED_IFORMFL_STD_LAST_DEFINED XED_IFORMFL_STGI_FIRST_DEFINED XED_IFORMFL_STGI_LAST_DEFINED XED_IFORMFL_STI_FIRST_DEFINED XED_IFORMFL_STI_LAST_DEFINED XED_IFORMFL_STMXCSR_FIRST_DEFINED XED_IFORMFL_STMXCSR_LAST_DEFINED XED_IFORMFL_STOSB_FIRST_DEFINED XED_IFORMFL_STOSB_LAST_DEFINED XED_IFORMFL_STOSD_FIRST_DEFINED XED_IFORMFL_STOSD_LAST_DEFINED XED_IFORMFL_STOSQ_FIRST_DEFINED XED_IFORMFL_STOSQ_LAST_DEFINED XED_IFORMFL_STOSW_FIRST_DEFINED XED_IFORMFL_STOSW_LAST_DEFINED XED_IFORMFL_STR_FIRST_DEFINED XED_IFORMFL_STR_LAST_DEFINED XED_IFORMFL_STTILECFG_FIRST_DEFINED XED_IFORMFL_STTILECFG_LAST_DEFINED XED_IFORMFL_STUI_FIRST_DEFINED XED_IFORMFL_STUI_LAST_DEFINED XED_IFORMFL_SUBPD_FIRST_DEFINED XED_IFORMFL_SUBPD_LAST_DEFINED XED_IFORMFL_SUBPS_FIRST_DEFINED XED_IFORMFL_SUBPS_LAST_DEFINED XED_IFORMFL_SUBSD_FIRST_DEFINED XED_IFORMFL_SUBSD_LAST_DEFINED XED_IFORMFL_SUBSS_FIRST_DEFINED XED_IFORMFL_SUBSS_LAST_DEFINED XED_IFORMFL_SUB_FIRST_DEFINED XED_IFORMFL_SUB_LAST_DEFINED XED_IFORMFL_SUB_LOCK_FIRST_DEFINED XED_IFORMFL_SUB_LOCK_LAST_DEFINED XED_IFORMFL_SWAPGS_FIRST_DEFINED XED_IFORMFL_SWAPGS_LAST_DEFINED XED_IFORMFL_SYSCALL_AMD_FIRST_DEFINED XED_IFORMFL_SYSCALL_AMD_LAST_DEFINED XED_IFORMFL_SYSCALL_FIRST_DEFINED XED_IFORMFL_SYSCALL_LAST_DEFINED XED_IFORMFL_SYSENTER_FIRST_DEFINED XED_IFORMFL_SYSENTER_LAST_DEFINED XED_IFORMFL_SYSEXIT_FIRST_DEFINED XED_IFORMFL_SYSEXIT_LAST_DEFINED XED_IFORMFL_SYSRET64_FIRST_DEFINED XED_IFORMFL_SYSRET64_LAST_DEFINED XED_IFORMFL_SYSRET_AMD_FIRST_DEFINED XED_IFORMFL_SYSRET_AMD_LAST_DEFINED XED_IFORMFL_SYSRET_FIRST_DEFINED XED_IFORMFL_SYSRET_LAST_DEFINED XED_IFORMFL_T1MSKC_FIRST_DEFINED XED_IFORMFL_T1MSKC_LAST_DEFINED XED_IFORMFL_TCMMIMFP16PS_FIRST_DEFINED XED_IFORMFL_TCMMIMFP16PS_LAST_DEFINED XED_IFORMFL_TCMMRLFP16PS_FIRST_DEFINED XED_IFORMFL_TCMMRLFP16PS_LAST_DEFINED XED_IFORMFL_TDCALL_FIRST_DEFINED XED_IFORMFL_TDCALL_LAST_DEFINED XED_IFORMFL_TDPBF16PS_FIRST_DEFINED XED_IFORMFL_TDPBF16PS_LAST_DEFINED XED_IFORMFL_TDPBSSD_FIRST_DEFINED XED_IFORMFL_TDPBSSD_LAST_DEFINED XED_IFORMFL_TDPBSUD_FIRST_DEFINED XED_IFORMFL_TDPBSUD_LAST_DEFINED XED_IFORMFL_TDPBUSD_FIRST_DEFINED XED_IFORMFL_TDPBUSD_LAST_DEFINED XED_IFORMFL_TDPBUUD_FIRST_DEFINED XED_IFORMFL_TDPBUUD_LAST_DEFINED XED_IFORMFL_TDPFP16PS_FIRST_DEFINED XED_IFORMFL_TDPFP16PS_LAST_DEFINED XED_IFORMFL_TESTUI_FIRST_DEFINED XED_IFORMFL_TESTUI_LAST_DEFINED XED_IFORMFL_TEST_FIRST_DEFINED XED_IFORMFL_TEST_LAST_DEFINED XED_IFORMFL_TILELOADDT1_FIRST_DEFINED XED_IFORMFL_TILELOADDT1_LAST_DEFINED XED_IFORMFL_TILELOADD_FIRST_DEFINED XED_IFORMFL_TILELOADD_LAST_DEFINED XED_IFORMFL_TILERELEASE_FIRST_DEFINED XED_IFORMFL_TILERELEASE_LAST_DEFINED XED_IFORMFL_TILESTORED_FIRST_DEFINED XED_IFORMFL_TILESTORED_LAST_DEFINED XED_IFORMFL_TILEZERO_FIRST_DEFINED XED_IFORMFL_TILEZERO_LAST_DEFINED XED_IFORMFL_TLBSYNC_FIRST_DEFINED XED_IFORMFL_TLBSYNC_LAST_DEFINED XED_IFORMFL_TPAUSE_FIRST_DEFINED XED_IFORMFL_TPAUSE_LAST_DEFINED XED_IFORMFL_TZCNT_FIRST_DEFINED XED_IFORMFL_TZCNT_LAST_DEFINED XED_IFORMFL_TZMSK_FIRST_DEFINED XED_IFORMFL_TZMSK_LAST_DEFINED XED_IFORMFL_UCOMISD_FIRST_DEFINED XED_IFORMFL_UCOMISD_LAST_DEFINED XED_IFORMFL_UCOMISS_FIRST_DEFINED XED_IFORMFL_UCOMISS_LAST_DEFINED XED_IFORMFL_UD0_FIRST_DEFINED XED_IFORMFL_UD0_LAST_DEFINED XED_IFORMFL_UD1_FIRST_DEFINED XED_IFORMFL_UD1_LAST_DEFINED XED_IFORMFL_UD2_FIRST_DEFINED XED_IFORMFL_UD2_LAST_DEFINED XED_IFORMFL_UIRET_FIRST_DEFINED XED_IFORMFL_UIRET_LAST_DEFINED XED_IFORMFL_UMONITOR_FIRST_DEFINED XED_IFORMFL_UMONITOR_LAST_DEFINED XED_IFORMFL_UMWAIT_FIRST_DEFINED XED_IFORMFL_UMWAIT_LAST_DEFINED XED_IFORMFL_UNPCKHPD_FIRST_DEFINED XED_IFORMFL_UNPCKHPD_LAST_DEFINED XED_IFORMFL_UNPCKHPS_FIRST_DEFINED XED_IFORMFL_UNPCKHPS_LAST_DEFINED XED_IFORMFL_UNPCKLPD_FIRST_DEFINED XED_IFORMFL_UNPCKLPD_LAST_DEFINED XED_IFORMFL_UNPCKLPS_FIRST_DEFINED XED_IFORMFL_UNPCKLPS_LAST_DEFINED XED_IFORMFL_URDMSR_FIRST_DEFINED XED_IFORMFL_URDMSR_LAST_DEFINED XED_IFORMFL_UWRMSR_FIRST_DEFINED XED_IFORMFL_UWRMSR_LAST_DEFINED XED_IFORMFL_V4FMADDPS_FIRST_DEFINED XED_IFORMFL_V4FMADDPS_LAST_DEFINED XED_IFORMFL_V4FMADDSS_FIRST_DEFINED XED_IFORMFL_V4FMADDSS_LAST_DEFINED XED_IFORMFL_V4FNMADDPS_FIRST_DEFINED XED_IFORMFL_V4FNMADDPS_LAST_DEFINED XED_IFORMFL_V4FNMADDSS_FIRST_DEFINED XED_IFORMFL_V4FNMADDSS_LAST_DEFINED XED_IFORMFL_VADDPD_FIRST_DEFINED XED_IFORMFL_VADDPD_LAST_DEFINED XED_IFORMFL_VADDPH_FIRST_DEFINED XED_IFORMFL_VADDPH_LAST_DEFINED XED_IFORMFL_VADDPS_FIRST_DEFINED XED_IFORMFL_VADDPS_LAST_DEFINED XED_IFORMFL_VADDSD_FIRST_DEFINED XED_IFORMFL_VADDSD_LAST_DEFINED XED_IFORMFL_VADDSH_FIRST_DEFINED XED_IFORMFL_VADDSH_LAST_DEFINED XED_IFORMFL_VADDSS_FIRST_DEFINED XED_IFORMFL_VADDSS_LAST_DEFINED XED_IFORMFL_VADDSUBPD_FIRST_DEFINED XED_IFORMFL_VADDSUBPD_LAST_DEFINED XED_IFORMFL_VADDSUBPS_FIRST_DEFINED XED_IFORMFL_VADDSUBPS_LAST_DEFINED XED_IFORMFL_VAESDECLAST_FIRST_DEFINED XED_IFORMFL_VAESDECLAST_LAST_DEFINED XED_IFORMFL_VAESDEC_FIRST_DEFINED XED_IFORMFL_VAESDEC_LAST_DEFINED XED_IFORMFL_VAESENCLAST_FIRST_DEFINED XED_IFORMFL_VAESENCLAST_LAST_DEFINED XED_IFORMFL_VAESENC_FIRST_DEFINED XED_IFORMFL_VAESENC_LAST_DEFINED XED_IFORMFL_VAESIMC_FIRST_DEFINED XED_IFORMFL_VAESIMC_LAST_DEFINED XED_IFORMFL_VAESKEYGENASSIST_FIRST_DEFINED XED_IFORMFL_VAESKEYGENASSIST_LAST_DEFINED XED_IFORMFL_VALIGND_FIRST_DEFINED XED_IFORMFL_VALIGND_LAST_DEFINED XED_IFORMFL_VALIGNQ_FIRST_DEFINED XED_IFORMFL_VALIGNQ_LAST_DEFINED XED_IFORMFL_VANDNPD_FIRST_DEFINED XED_IFORMFL_VANDNPD_LAST_DEFINED XED_IFORMFL_VANDNPS_FIRST_DEFINED XED_IFORMFL_VANDNPS_LAST_DEFINED XED_IFORMFL_VANDPD_FIRST_DEFINED XED_IFORMFL_VANDPD_LAST_DEFINED XED_IFORMFL_VANDPS_FIRST_DEFINED XED_IFORMFL_VANDPS_LAST_DEFINED XED_IFORMFL_VBCSTNEBF162PS_FIRST_DEFINED XED_IFORMFL_VBCSTNEBF162PS_LAST_DEFINED XED_IFORMFL_VBCSTNESH2PS_FIRST_DEFINED XED_IFORMFL_VBCSTNESH2PS_LAST_DEFINED XED_IFORMFL_VBLENDMPD_FIRST_DEFINED XED_IFORMFL_VBLENDMPD_LAST_DEFINED XED_IFORMFL_VBLENDMPS_FIRST_DEFINED XED_IFORMFL_VBLENDMPS_LAST_DEFINED XED_IFORMFL_VBLENDPD_FIRST_DEFINED XED_IFORMFL_VBLENDPD_LAST_DEFINED XED_IFORMFL_VBLENDPS_FIRST_DEFINED XED_IFORMFL_VBLENDPS_LAST_DEFINED XED_IFORMFL_VBLENDVPD_FIRST_DEFINED XED_IFORMFL_VBLENDVPD_LAST_DEFINED XED_IFORMFL_VBLENDVPS_FIRST_DEFINED XED_IFORMFL_VBLENDVPS_LAST_DEFINED XED_IFORMFL_VBROADCASTF32X2_FIRST_DEFINED XED_IFORMFL_VBROADCASTF32X2_LAST_DEFINED XED_IFORMFL_VBROADCASTF32X4_FIRST_DEFINED XED_IFORMFL_VBROADCASTF32X4_LAST_DEFINED XED_IFORMFL_VBROADCASTF32X8_FIRST_DEFINED XED_IFORMFL_VBROADCASTF32X8_LAST_DEFINED XED_IFORMFL_VBROADCASTF64X2_FIRST_DEFINED XED_IFORMFL_VBROADCASTF64X2_LAST_DEFINED XED_IFORMFL_VBROADCASTF64X4_FIRST_DEFINED XED_IFORMFL_VBROADCASTF64X4_LAST_DEFINED XED_IFORMFL_VBROADCASTF128_FIRST_DEFINED XED_IFORMFL_VBROADCASTF128_LAST_DEFINED XED_IFORMFL_VBROADCASTI32X2_FIRST_DEFINED XED_IFORMFL_VBROADCASTI32X2_LAST_DEFINED XED_IFORMFL_VBROADCASTI32X4_FIRST_DEFINED XED_IFORMFL_VBROADCASTI32X4_LAST_DEFINED XED_IFORMFL_VBROADCASTI32X8_FIRST_DEFINED XED_IFORMFL_VBROADCASTI32X8_LAST_DEFINED XED_IFORMFL_VBROADCASTI64X2_FIRST_DEFINED XED_IFORMFL_VBROADCASTI64X2_LAST_DEFINED XED_IFORMFL_VBROADCASTI64X4_FIRST_DEFINED XED_IFORMFL_VBROADCASTI64X4_LAST_DEFINED XED_IFORMFL_VBROADCASTI128_FIRST_DEFINED XED_IFORMFL_VBROADCASTI128_LAST_DEFINED XED_IFORMFL_VBROADCASTSD_FIRST_DEFINED XED_IFORMFL_VBROADCASTSD_LAST_DEFINED XED_IFORMFL_VBROADCASTSS_FIRST_DEFINED XED_IFORMFL_VBROADCASTSS_LAST_DEFINED XED_IFORMFL_VCMPPD_FIRST_DEFINED XED_IFORMFL_VCMPPD_LAST_DEFINED XED_IFORMFL_VCMPPH_FIRST_DEFINED XED_IFORMFL_VCMPPH_LAST_DEFINED XED_IFORMFL_VCMPPS_FIRST_DEFINED XED_IFORMFL_VCMPPS_LAST_DEFINED XED_IFORMFL_VCMPSD_FIRST_DEFINED XED_IFORMFL_VCMPSD_LAST_DEFINED XED_IFORMFL_VCMPSH_FIRST_DEFINED XED_IFORMFL_VCMPSH_LAST_DEFINED XED_IFORMFL_VCMPSS_FIRST_DEFINED XED_IFORMFL_VCMPSS_LAST_DEFINED XED_IFORMFL_VCOMISD_FIRST_DEFINED XED_IFORMFL_VCOMISD_LAST_DEFINED XED_IFORMFL_VCOMISH_FIRST_DEFINED XED_IFORMFL_VCOMISH_LAST_DEFINED XED_IFORMFL_VCOMISS_FIRST_DEFINED XED_IFORMFL_VCOMISS_LAST_DEFINED XED_IFORMFL_VCOMPRESSPD_FIRST_DEFINED XED_IFORMFL_VCOMPRESSPD_LAST_DEFINED XED_IFORMFL_VCOMPRESSPS_FIRST_DEFINED XED_IFORMFL_VCOMPRESSPS_LAST_DEFINED XED_IFORMFL_VCVTDQ2PD_FIRST_DEFINED XED_IFORMFL_VCVTDQ2PD_LAST_DEFINED XED_IFORMFL_VCVTDQ2PH_FIRST_DEFINED XED_IFORMFL_VCVTDQ2PH_LAST_DEFINED XED_IFORMFL_VCVTDQ2PS_FIRST_DEFINED XED_IFORMFL_VCVTDQ2PS_LAST_DEFINED XED_IFORMFL_VCVTNE2PS2BF16_FIRST_DEFINED XED_IFORMFL_VCVTNE2PS2BF16_LAST_DEFINED XED_IFORMFL_VCVTNEEBF162PS_FIRST_DEFINED XED_IFORMFL_VCVTNEEBF162PS_LAST_DEFINED XED_IFORMFL_VCVTNEEPH2PS_FIRST_DEFINED XED_IFORMFL_VCVTNEEPH2PS_LAST_DEFINED XED_IFORMFL_VCVTNEOBF162PS_FIRST_DEFINED XED_IFORMFL_VCVTNEOBF162PS_LAST_DEFINED XED_IFORMFL_VCVTNEOPH2PS_FIRST_DEFINED XED_IFORMFL_VCVTNEOPH2PS_LAST_DEFINED XED_IFORMFL_VCVTNEPS2BF16_FIRST_DEFINED XED_IFORMFL_VCVTNEPS2BF16_LAST_DEFINED XED_IFORMFL_VCVTPD2DQ_FIRST_DEFINED XED_IFORMFL_VCVTPD2DQ_LAST_DEFINED XED_IFORMFL_VCVTPD2PH_FIRST_DEFINED XED_IFORMFL_VCVTPD2PH_LAST_DEFINED XED_IFORMFL_VCVTPD2PS_FIRST_DEFINED XED_IFORMFL_VCVTPD2PS_LAST_DEFINED XED_IFORMFL_VCVTPD2QQ_FIRST_DEFINED XED_IFORMFL_VCVTPD2QQ_LAST_DEFINED XED_IFORMFL_VCVTPD2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTPD2UDQ_LAST_DEFINED XED_IFORMFL_VCVTPD2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTPD2UQQ_LAST_DEFINED XED_IFORMFL_VCVTPH2DQ_FIRST_DEFINED XED_IFORMFL_VCVTPH2DQ_LAST_DEFINED XED_IFORMFL_VCVTPH2PD_FIRST_DEFINED XED_IFORMFL_VCVTPH2PD_LAST_DEFINED XED_IFORMFL_VCVTPH2PSX_FIRST_DEFINED XED_IFORMFL_VCVTPH2PSX_LAST_DEFINED XED_IFORMFL_VCVTPH2PS_FIRST_DEFINED XED_IFORMFL_VCVTPH2PS_LAST_DEFINED XED_IFORMFL_VCVTPH2QQ_FIRST_DEFINED XED_IFORMFL_VCVTPH2QQ_LAST_DEFINED XED_IFORMFL_VCVTPH2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTPH2UDQ_LAST_DEFINED XED_IFORMFL_VCVTPH2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTPH2UQQ_LAST_DEFINED XED_IFORMFL_VCVTPH2UW_FIRST_DEFINED XED_IFORMFL_VCVTPH2UW_LAST_DEFINED XED_IFORMFL_VCVTPH2W_FIRST_DEFINED XED_IFORMFL_VCVTPH2W_LAST_DEFINED XED_IFORMFL_VCVTPS2DQ_FIRST_DEFINED XED_IFORMFL_VCVTPS2DQ_LAST_DEFINED XED_IFORMFL_VCVTPS2PD_FIRST_DEFINED XED_IFORMFL_VCVTPS2PD_LAST_DEFINED XED_IFORMFL_VCVTPS2PHX_FIRST_DEFINED XED_IFORMFL_VCVTPS2PHX_LAST_DEFINED XED_IFORMFL_VCVTPS2PH_FIRST_DEFINED XED_IFORMFL_VCVTPS2PH_LAST_DEFINED XED_IFORMFL_VCVTPS2QQ_FIRST_DEFINED XED_IFORMFL_VCVTPS2QQ_LAST_DEFINED XED_IFORMFL_VCVTPS2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTPS2UDQ_LAST_DEFINED XED_IFORMFL_VCVTPS2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTPS2UQQ_LAST_DEFINED XED_IFORMFL_VCVTQQ2PD_FIRST_DEFINED XED_IFORMFL_VCVTQQ2PD_LAST_DEFINED XED_IFORMFL_VCVTQQ2PH_FIRST_DEFINED XED_IFORMFL_VCVTQQ2PH_LAST_DEFINED XED_IFORMFL_VCVTQQ2PS_FIRST_DEFINED XED_IFORMFL_VCVTQQ2PS_LAST_DEFINED XED_IFORMFL_VCVTSD2SH_FIRST_DEFINED XED_IFORMFL_VCVTSD2SH_LAST_DEFINED XED_IFORMFL_VCVTSD2SI_FIRST_DEFINED XED_IFORMFL_VCVTSD2SI_LAST_DEFINED XED_IFORMFL_VCVTSD2SS_FIRST_DEFINED XED_IFORMFL_VCVTSD2SS_LAST_DEFINED XED_IFORMFL_VCVTSD2USI_FIRST_DEFINED XED_IFORMFL_VCVTSD2USI_LAST_DEFINED XED_IFORMFL_VCVTSH2SD_FIRST_DEFINED XED_IFORMFL_VCVTSH2SD_LAST_DEFINED XED_IFORMFL_VCVTSH2SI_FIRST_DEFINED XED_IFORMFL_VCVTSH2SI_LAST_DEFINED XED_IFORMFL_VCVTSH2SS_FIRST_DEFINED XED_IFORMFL_VCVTSH2SS_LAST_DEFINED XED_IFORMFL_VCVTSH2USI_FIRST_DEFINED XED_IFORMFL_VCVTSH2USI_LAST_DEFINED XED_IFORMFL_VCVTSI2SD_FIRST_DEFINED XED_IFORMFL_VCVTSI2SD_LAST_DEFINED XED_IFORMFL_VCVTSI2SH_FIRST_DEFINED XED_IFORMFL_VCVTSI2SH_LAST_DEFINED XED_IFORMFL_VCVTSI2SS_FIRST_DEFINED XED_IFORMFL_VCVTSI2SS_LAST_DEFINED XED_IFORMFL_VCVTSS2SD_FIRST_DEFINED XED_IFORMFL_VCVTSS2SD_LAST_DEFINED XED_IFORMFL_VCVTSS2SH_FIRST_DEFINED XED_IFORMFL_VCVTSS2SH_LAST_DEFINED XED_IFORMFL_VCVTSS2SI_FIRST_DEFINED XED_IFORMFL_VCVTSS2SI_LAST_DEFINED XED_IFORMFL_VCVTSS2USI_FIRST_DEFINED XED_IFORMFL_VCVTSS2USI_LAST_DEFINED XED_IFORMFL_VCVTTPD2DQ_FIRST_DEFINED XED_IFORMFL_VCVTTPD2DQ_LAST_DEFINED XED_IFORMFL_VCVTTPD2QQ_FIRST_DEFINED XED_IFORMFL_VCVTTPD2QQ_LAST_DEFINED XED_IFORMFL_VCVTTPD2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTTPD2UDQ_LAST_DEFINED XED_IFORMFL_VCVTTPD2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTTPD2UQQ_LAST_DEFINED XED_IFORMFL_VCVTTPH2DQ_FIRST_DEFINED XED_IFORMFL_VCVTTPH2DQ_LAST_DEFINED XED_IFORMFL_VCVTTPH2QQ_FIRST_DEFINED XED_IFORMFL_VCVTTPH2QQ_LAST_DEFINED XED_IFORMFL_VCVTTPH2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTTPH2UDQ_LAST_DEFINED XED_IFORMFL_VCVTTPH2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTTPH2UQQ_LAST_DEFINED XED_IFORMFL_VCVTTPH2UW_FIRST_DEFINED XED_IFORMFL_VCVTTPH2UW_LAST_DEFINED XED_IFORMFL_VCVTTPH2W_FIRST_DEFINED XED_IFORMFL_VCVTTPH2W_LAST_DEFINED XED_IFORMFL_VCVTTPS2DQ_FIRST_DEFINED XED_IFORMFL_VCVTTPS2DQ_LAST_DEFINED XED_IFORMFL_VCVTTPS2QQ_FIRST_DEFINED XED_IFORMFL_VCVTTPS2QQ_LAST_DEFINED XED_IFORMFL_VCVTTPS2UDQ_FIRST_DEFINED XED_IFORMFL_VCVTTPS2UDQ_LAST_DEFINED XED_IFORMFL_VCVTTPS2UQQ_FIRST_DEFINED XED_IFORMFL_VCVTTPS2UQQ_LAST_DEFINED XED_IFORMFL_VCVTTSD2SI_FIRST_DEFINED XED_IFORMFL_VCVTTSD2SI_LAST_DEFINED XED_IFORMFL_VCVTTSD2USI_FIRST_DEFINED XED_IFORMFL_VCVTTSD2USI_LAST_DEFINED XED_IFORMFL_VCVTTSH2SI_FIRST_DEFINED XED_IFORMFL_VCVTTSH2SI_LAST_DEFINED XED_IFORMFL_VCVTTSH2USI_FIRST_DEFINED XED_IFORMFL_VCVTTSH2USI_LAST_DEFINED XED_IFORMFL_VCVTTSS2SI_FIRST_DEFINED XED_IFORMFL_VCVTTSS2SI_LAST_DEFINED XED_IFORMFL_VCVTTSS2USI_FIRST_DEFINED XED_IFORMFL_VCVTTSS2USI_LAST_DEFINED XED_IFORMFL_VCVTUDQ2PD_FIRST_DEFINED XED_IFORMFL_VCVTUDQ2PD_LAST_DEFINED XED_IFORMFL_VCVTUDQ2PH_FIRST_DEFINED XED_IFORMFL_VCVTUDQ2PH_LAST_DEFINED XED_IFORMFL_VCVTUDQ2PS_FIRST_DEFINED XED_IFORMFL_VCVTUDQ2PS_LAST_DEFINED XED_IFORMFL_VCVTUQQ2PD_FIRST_DEFINED XED_IFORMFL_VCVTUQQ2PD_LAST_DEFINED XED_IFORMFL_VCVTUQQ2PH_FIRST_DEFINED XED_IFORMFL_VCVTUQQ2PH_LAST_DEFINED XED_IFORMFL_VCVTUQQ2PS_FIRST_DEFINED XED_IFORMFL_VCVTUQQ2PS_LAST_DEFINED XED_IFORMFL_VCVTUSI2SD_FIRST_DEFINED XED_IFORMFL_VCVTUSI2SD_LAST_DEFINED XED_IFORMFL_VCVTUSI2SH_FIRST_DEFINED XED_IFORMFL_VCVTUSI2SH_LAST_DEFINED XED_IFORMFL_VCVTUSI2SS_FIRST_DEFINED XED_IFORMFL_VCVTUSI2SS_LAST_DEFINED XED_IFORMFL_VCVTUW2PH_FIRST_DEFINED XED_IFORMFL_VCVTUW2PH_LAST_DEFINED XED_IFORMFL_VCVTW2PH_FIRST_DEFINED XED_IFORMFL_VCVTW2PH_LAST_DEFINED XED_IFORMFL_VDBPSADBW_FIRST_DEFINED XED_IFORMFL_VDBPSADBW_LAST_DEFINED XED_IFORMFL_VDIVPD_FIRST_DEFINED XED_IFORMFL_VDIVPD_LAST_DEFINED XED_IFORMFL_VDIVPH_FIRST_DEFINED XED_IFORMFL_VDIVPH_LAST_DEFINED XED_IFORMFL_VDIVPS_FIRST_DEFINED XED_IFORMFL_VDIVPS_LAST_DEFINED XED_IFORMFL_VDIVSD_FIRST_DEFINED XED_IFORMFL_VDIVSD_LAST_DEFINED XED_IFORMFL_VDIVSH_FIRST_DEFINED XED_IFORMFL_VDIVSH_LAST_DEFINED XED_IFORMFL_VDIVSS_FIRST_DEFINED XED_IFORMFL_VDIVSS_LAST_DEFINED XED_IFORMFL_VDPBF16PS_FIRST_DEFINED XED_IFORMFL_VDPBF16PS_LAST_DEFINED XED_IFORMFL_VDPPD_FIRST_DEFINED XED_IFORMFL_VDPPD_LAST_DEFINED XED_IFORMFL_VDPPS_FIRST_DEFINED XED_IFORMFL_VDPPS_LAST_DEFINED XED_IFORMFL_VERR_FIRST_DEFINED XED_IFORMFL_VERR_LAST_DEFINED XED_IFORMFL_VERW_FIRST_DEFINED XED_IFORMFL_VERW_LAST_DEFINED XED_IFORMFL_VEXP2PD_FIRST_DEFINED XED_IFORMFL_VEXP2PD_LAST_DEFINED XED_IFORMFL_VEXP2PS_FIRST_DEFINED XED_IFORMFL_VEXP2PS_LAST_DEFINED XED_IFORMFL_VEXPANDPD_FIRST_DEFINED XED_IFORMFL_VEXPANDPD_LAST_DEFINED XED_IFORMFL_VEXPANDPS_FIRST_DEFINED XED_IFORMFL_VEXPANDPS_LAST_DEFINED XED_IFORMFL_VEXTRACTF32X4_FIRST_DEFINED XED_IFORMFL_VEXTRACTF32X4_LAST_DEFINED XED_IFORMFL_VEXTRACTF32X8_FIRST_DEFINED XED_IFORMFL_VEXTRACTF32X8_LAST_DEFINED XED_IFORMFL_VEXTRACTF64X2_FIRST_DEFINED XED_IFORMFL_VEXTRACTF64X2_LAST_DEFINED XED_IFORMFL_VEXTRACTF64X4_FIRST_DEFINED XED_IFORMFL_VEXTRACTF64X4_LAST_DEFINED XED_IFORMFL_VEXTRACTF128_FIRST_DEFINED XED_IFORMFL_VEXTRACTF128_LAST_DEFINED XED_IFORMFL_VEXTRACTI32X4_FIRST_DEFINED XED_IFORMFL_VEXTRACTI32X4_LAST_DEFINED XED_IFORMFL_VEXTRACTI32X8_FIRST_DEFINED XED_IFORMFL_VEXTRACTI32X8_LAST_DEFINED XED_IFORMFL_VEXTRACTI64X2_FIRST_DEFINED XED_IFORMFL_VEXTRACTI64X2_LAST_DEFINED XED_IFORMFL_VEXTRACTI64X4_FIRST_DEFINED XED_IFORMFL_VEXTRACTI64X4_LAST_DEFINED XED_IFORMFL_VEXTRACTI128_FIRST_DEFINED XED_IFORMFL_VEXTRACTI128_LAST_DEFINED XED_IFORMFL_VEXTRACTPS_FIRST_DEFINED XED_IFORMFL_VEXTRACTPS_LAST_DEFINED XED_IFORMFL_VFCMADDCPH_FIRST_DEFINED XED_IFORMFL_VFCMADDCPH_LAST_DEFINED XED_IFORMFL_VFCMADDCSH_FIRST_DEFINED XED_IFORMFL_VFCMADDCSH_LAST_DEFINED XED_IFORMFL_VFCMULCPH_FIRST_DEFINED XED_IFORMFL_VFCMULCPH_LAST_DEFINED XED_IFORMFL_VFCMULCSH_FIRST_DEFINED XED_IFORMFL_VFCMULCSH_LAST_DEFINED XED_IFORMFL_VFIXUPIMMPD_FIRST_DEFINED XED_IFORMFL_VFIXUPIMMPD_LAST_DEFINED XED_IFORMFL_VFIXUPIMMPS_FIRST_DEFINED XED_IFORMFL_VFIXUPIMMPS_LAST_DEFINED XED_IFORMFL_VFIXUPIMMSD_FIRST_DEFINED XED_IFORMFL_VFIXUPIMMSD_LAST_DEFINED XED_IFORMFL_VFIXUPIMMSS_FIRST_DEFINED XED_IFORMFL_VFIXUPIMMSS_LAST_DEFINED XED_IFORMFL_VFMADD132PD_FIRST_DEFINED XED_IFORMFL_VFMADD132PD_LAST_DEFINED XED_IFORMFL_VFMADD132PH_FIRST_DEFINED XED_IFORMFL_VFMADD132PH_LAST_DEFINED XED_IFORMFL_VFMADD132PS_FIRST_DEFINED XED_IFORMFL_VFMADD132PS_LAST_DEFINED XED_IFORMFL_VFMADD132SD_FIRST_DEFINED XED_IFORMFL_VFMADD132SD_LAST_DEFINED XED_IFORMFL_VFMADD132SH_FIRST_DEFINED XED_IFORMFL_VFMADD132SH_LAST_DEFINED XED_IFORMFL_VFMADD132SS_FIRST_DEFINED XED_IFORMFL_VFMADD132SS_LAST_DEFINED XED_IFORMFL_VFMADD213PD_FIRST_DEFINED XED_IFORMFL_VFMADD213PD_LAST_DEFINED XED_IFORMFL_VFMADD213PH_FIRST_DEFINED XED_IFORMFL_VFMADD213PH_LAST_DEFINED XED_IFORMFL_VFMADD213PS_FIRST_DEFINED XED_IFORMFL_VFMADD213PS_LAST_DEFINED XED_IFORMFL_VFMADD213SD_FIRST_DEFINED XED_IFORMFL_VFMADD213SD_LAST_DEFINED XED_IFORMFL_VFMADD213SH_FIRST_DEFINED XED_IFORMFL_VFMADD213SH_LAST_DEFINED XED_IFORMFL_VFMADD213SS_FIRST_DEFINED XED_IFORMFL_VFMADD213SS_LAST_DEFINED XED_IFORMFL_VFMADD231PD_FIRST_DEFINED XED_IFORMFL_VFMADD231PD_LAST_DEFINED XED_IFORMFL_VFMADD231PH_FIRST_DEFINED XED_IFORMFL_VFMADD231PH_LAST_DEFINED XED_IFORMFL_VFMADD231PS_FIRST_DEFINED XED_IFORMFL_VFMADD231PS_LAST_DEFINED XED_IFORMFL_VFMADD231SD_FIRST_DEFINED XED_IFORMFL_VFMADD231SD_LAST_DEFINED XED_IFORMFL_VFMADD231SH_FIRST_DEFINED XED_IFORMFL_VFMADD231SH_LAST_DEFINED XED_IFORMFL_VFMADD231SS_FIRST_DEFINED XED_IFORMFL_VFMADD231SS_LAST_DEFINED XED_IFORMFL_VFMADDCPH_FIRST_DEFINED XED_IFORMFL_VFMADDCPH_LAST_DEFINED XED_IFORMFL_VFMADDCSH_FIRST_DEFINED XED_IFORMFL_VFMADDCSH_LAST_DEFINED XED_IFORMFL_VFMADDPD_FIRST_DEFINED XED_IFORMFL_VFMADDPD_LAST_DEFINED XED_IFORMFL_VFMADDPS_FIRST_DEFINED XED_IFORMFL_VFMADDPS_LAST_DEFINED XED_IFORMFL_VFMADDSD_FIRST_DEFINED XED_IFORMFL_VFMADDSD_LAST_DEFINED XED_IFORMFL_VFMADDSS_FIRST_DEFINED XED_IFORMFL_VFMADDSS_LAST_DEFINED XED_IFORMFL_VFMADDSUB132PD_FIRST_DEFINED XED_IFORMFL_VFMADDSUB132PD_LAST_DEFINED XED_IFORMFL_VFMADDSUB132PH_FIRST_DEFINED XED_IFORMFL_VFMADDSUB132PH_LAST_DEFINED XED_IFORMFL_VFMADDSUB132PS_FIRST_DEFINED XED_IFORMFL_VFMADDSUB132PS_LAST_DEFINED XED_IFORMFL_VFMADDSUB213PD_FIRST_DEFINED XED_IFORMFL_VFMADDSUB213PD_LAST_DEFINED XED_IFORMFL_VFMADDSUB213PH_FIRST_DEFINED XED_IFORMFL_VFMADDSUB213PH_LAST_DEFINED XED_IFORMFL_VFMADDSUB213PS_FIRST_DEFINED XED_IFORMFL_VFMADDSUB213PS_LAST_DEFINED XED_IFORMFL_VFMADDSUB231PD_FIRST_DEFINED XED_IFORMFL_VFMADDSUB231PD_LAST_DEFINED XED_IFORMFL_VFMADDSUB231PH_FIRST_DEFINED XED_IFORMFL_VFMADDSUB231PH_LAST_DEFINED XED_IFORMFL_VFMADDSUB231PS_FIRST_DEFINED XED_IFORMFL_VFMADDSUB231PS_LAST_DEFINED XED_IFORMFL_VFMADDSUBPD_FIRST_DEFINED XED_IFORMFL_VFMADDSUBPD_LAST_DEFINED XED_IFORMFL_VFMADDSUBPS_FIRST_DEFINED XED_IFORMFL_VFMADDSUBPS_LAST_DEFINED XED_IFORMFL_VFMSUB132PD_FIRST_DEFINED XED_IFORMFL_VFMSUB132PD_LAST_DEFINED XED_IFORMFL_VFMSUB132PH_FIRST_DEFINED XED_IFORMFL_VFMSUB132PH_LAST_DEFINED XED_IFORMFL_VFMSUB132PS_FIRST_DEFINED XED_IFORMFL_VFMSUB132PS_LAST_DEFINED XED_IFORMFL_VFMSUB132SD_FIRST_DEFINED XED_IFORMFL_VFMSUB132SD_LAST_DEFINED XED_IFORMFL_VFMSUB132SH_FIRST_DEFINED XED_IFORMFL_VFMSUB132SH_LAST_DEFINED XED_IFORMFL_VFMSUB132SS_FIRST_DEFINED XED_IFORMFL_VFMSUB132SS_LAST_DEFINED XED_IFORMFL_VFMSUB213PD_FIRST_DEFINED XED_IFORMFL_VFMSUB213PD_LAST_DEFINED XED_IFORMFL_VFMSUB213PH_FIRST_DEFINED XED_IFORMFL_VFMSUB213PH_LAST_DEFINED XED_IFORMFL_VFMSUB213PS_FIRST_DEFINED XED_IFORMFL_VFMSUB213PS_LAST_DEFINED XED_IFORMFL_VFMSUB213SD_FIRST_DEFINED XED_IFORMFL_VFMSUB213SD_LAST_DEFINED XED_IFORMFL_VFMSUB213SH_FIRST_DEFINED XED_IFORMFL_VFMSUB213SH_LAST_DEFINED XED_IFORMFL_VFMSUB213SS_FIRST_DEFINED XED_IFORMFL_VFMSUB213SS_LAST_DEFINED XED_IFORMFL_VFMSUB231PD_FIRST_DEFINED XED_IFORMFL_VFMSUB231PD_LAST_DEFINED XED_IFORMFL_VFMSUB231PH_FIRST_DEFINED XED_IFORMFL_VFMSUB231PH_LAST_DEFINED XED_IFORMFL_VFMSUB231PS_FIRST_DEFINED XED_IFORMFL_VFMSUB231PS_LAST_DEFINED XED_IFORMFL_VFMSUB231SD_FIRST_DEFINED XED_IFORMFL_VFMSUB231SD_LAST_DEFINED XED_IFORMFL_VFMSUB231SH_FIRST_DEFINED XED_IFORMFL_VFMSUB231SH_LAST_DEFINED XED_IFORMFL_VFMSUB231SS_FIRST_DEFINED XED_IFORMFL_VFMSUB231SS_LAST_DEFINED XED_IFORMFL_VFMSUBADD132PD_FIRST_DEFINED XED_IFORMFL_VFMSUBADD132PD_LAST_DEFINED XED_IFORMFL_VFMSUBADD132PH_FIRST_DEFINED XED_IFORMFL_VFMSUBADD132PH_LAST_DEFINED XED_IFORMFL_VFMSUBADD132PS_FIRST_DEFINED XED_IFORMFL_VFMSUBADD132PS_LAST_DEFINED XED_IFORMFL_VFMSUBADD213PD_FIRST_DEFINED XED_IFORMFL_VFMSUBADD213PD_LAST_DEFINED XED_IFORMFL_VFMSUBADD213PH_FIRST_DEFINED XED_IFORMFL_VFMSUBADD213PH_LAST_DEFINED XED_IFORMFL_VFMSUBADD213PS_FIRST_DEFINED XED_IFORMFL_VFMSUBADD213PS_LAST_DEFINED XED_IFORMFL_VFMSUBADD231PD_FIRST_DEFINED XED_IFORMFL_VFMSUBADD231PD_LAST_DEFINED XED_IFORMFL_VFMSUBADD231PH_FIRST_DEFINED XED_IFORMFL_VFMSUBADD231PH_LAST_DEFINED XED_IFORMFL_VFMSUBADD231PS_FIRST_DEFINED XED_IFORMFL_VFMSUBADD231PS_LAST_DEFINED XED_IFORMFL_VFMSUBADDPD_FIRST_DEFINED XED_IFORMFL_VFMSUBADDPD_LAST_DEFINED XED_IFORMFL_VFMSUBADDPS_FIRST_DEFINED XED_IFORMFL_VFMSUBADDPS_LAST_DEFINED XED_IFORMFL_VFMSUBPD_FIRST_DEFINED XED_IFORMFL_VFMSUBPD_LAST_DEFINED XED_IFORMFL_VFMSUBPS_FIRST_DEFINED XED_IFORMFL_VFMSUBPS_LAST_DEFINED XED_IFORMFL_VFMSUBSD_FIRST_DEFINED XED_IFORMFL_VFMSUBSD_LAST_DEFINED XED_IFORMFL_VFMSUBSS_FIRST_DEFINED XED_IFORMFL_VFMSUBSS_LAST_DEFINED XED_IFORMFL_VFMULCPH_FIRST_DEFINED XED_IFORMFL_VFMULCPH_LAST_DEFINED XED_IFORMFL_VFMULCSH_FIRST_DEFINED XED_IFORMFL_VFMULCSH_LAST_DEFINED XED_IFORMFL_VFNMADD132PD_FIRST_DEFINED XED_IFORMFL_VFNMADD132PD_LAST_DEFINED XED_IFORMFL_VFNMADD132PH_FIRST_DEFINED XED_IFORMFL_VFNMADD132PH_LAST_DEFINED XED_IFORMFL_VFNMADD132PS_FIRST_DEFINED XED_IFORMFL_VFNMADD132PS_LAST_DEFINED XED_IFORMFL_VFNMADD132SD_FIRST_DEFINED XED_IFORMFL_VFNMADD132SD_LAST_DEFINED XED_IFORMFL_VFNMADD132SH_FIRST_DEFINED XED_IFORMFL_VFNMADD132SH_LAST_DEFINED XED_IFORMFL_VFNMADD132SS_FIRST_DEFINED XED_IFORMFL_VFNMADD132SS_LAST_DEFINED XED_IFORMFL_VFNMADD213PD_FIRST_DEFINED XED_IFORMFL_VFNMADD213PD_LAST_DEFINED XED_IFORMFL_VFNMADD213PH_FIRST_DEFINED XED_IFORMFL_VFNMADD213PH_LAST_DEFINED XED_IFORMFL_VFNMADD213PS_FIRST_DEFINED XED_IFORMFL_VFNMADD213PS_LAST_DEFINED XED_IFORMFL_VFNMADD213SD_FIRST_DEFINED XED_IFORMFL_VFNMADD213SD_LAST_DEFINED XED_IFORMFL_VFNMADD213SH_FIRST_DEFINED XED_IFORMFL_VFNMADD213SH_LAST_DEFINED XED_IFORMFL_VFNMADD213SS_FIRST_DEFINED XED_IFORMFL_VFNMADD213SS_LAST_DEFINED XED_IFORMFL_VFNMADD231PD_FIRST_DEFINED XED_IFORMFL_VFNMADD231PD_LAST_DEFINED XED_IFORMFL_VFNMADD231PH_FIRST_DEFINED XED_IFORMFL_VFNMADD231PH_LAST_DEFINED XED_IFORMFL_VFNMADD231PS_FIRST_DEFINED XED_IFORMFL_VFNMADD231PS_LAST_DEFINED XED_IFORMFL_VFNMADD231SD_FIRST_DEFINED XED_IFORMFL_VFNMADD231SD_LAST_DEFINED XED_IFORMFL_VFNMADD231SH_FIRST_DEFINED XED_IFORMFL_VFNMADD231SH_LAST_DEFINED XED_IFORMFL_VFNMADD231SS_FIRST_DEFINED XED_IFORMFL_VFNMADD231SS_LAST_DEFINED XED_IFORMFL_VFNMADDPD_FIRST_DEFINED XED_IFORMFL_VFNMADDPD_LAST_DEFINED XED_IFORMFL_VFNMADDPS_FIRST_DEFINED XED_IFORMFL_VFNMADDPS_LAST_DEFINED XED_IFORMFL_VFNMADDSD_FIRST_DEFINED XED_IFORMFL_VFNMADDSD_LAST_DEFINED XED_IFORMFL_VFNMADDSS_FIRST_DEFINED XED_IFORMFL_VFNMADDSS_LAST_DEFINED XED_IFORMFL_VFNMSUB132PD_FIRST_DEFINED XED_IFORMFL_VFNMSUB132PD_LAST_DEFINED XED_IFORMFL_VFNMSUB132PH_FIRST_DEFINED XED_IFORMFL_VFNMSUB132PH_LAST_DEFINED XED_IFORMFL_VFNMSUB132PS_FIRST_DEFINED XED_IFORMFL_VFNMSUB132PS_LAST_DEFINED XED_IFORMFL_VFNMSUB132SD_FIRST_DEFINED XED_IFORMFL_VFNMSUB132SD_LAST_DEFINED XED_IFORMFL_VFNMSUB132SH_FIRST_DEFINED XED_IFORMFL_VFNMSUB132SH_LAST_DEFINED XED_IFORMFL_VFNMSUB132SS_FIRST_DEFINED XED_IFORMFL_VFNMSUB132SS_LAST_DEFINED XED_IFORMFL_VFNMSUB213PD_FIRST_DEFINED XED_IFORMFL_VFNMSUB213PD_LAST_DEFINED XED_IFORMFL_VFNMSUB213PH_FIRST_DEFINED XED_IFORMFL_VFNMSUB213PH_LAST_DEFINED XED_IFORMFL_VFNMSUB213PS_FIRST_DEFINED XED_IFORMFL_VFNMSUB213PS_LAST_DEFINED XED_IFORMFL_VFNMSUB213SD_FIRST_DEFINED XED_IFORMFL_VFNMSUB213SD_LAST_DEFINED XED_IFORMFL_VFNMSUB213SH_FIRST_DEFINED XED_IFORMFL_VFNMSUB213SH_LAST_DEFINED XED_IFORMFL_VFNMSUB213SS_FIRST_DEFINED XED_IFORMFL_VFNMSUB213SS_LAST_DEFINED XED_IFORMFL_VFNMSUB231PD_FIRST_DEFINED XED_IFORMFL_VFNMSUB231PD_LAST_DEFINED XED_IFORMFL_VFNMSUB231PH_FIRST_DEFINED XED_IFORMFL_VFNMSUB231PH_LAST_DEFINED XED_IFORMFL_VFNMSUB231PS_FIRST_DEFINED XED_IFORMFL_VFNMSUB231PS_LAST_DEFINED XED_IFORMFL_VFNMSUB231SD_FIRST_DEFINED XED_IFORMFL_VFNMSUB231SD_LAST_DEFINED XED_IFORMFL_VFNMSUB231SH_FIRST_DEFINED XED_IFORMFL_VFNMSUB231SH_LAST_DEFINED XED_IFORMFL_VFNMSUB231SS_FIRST_DEFINED XED_IFORMFL_VFNMSUB231SS_LAST_DEFINED XED_IFORMFL_VFNMSUBPD_FIRST_DEFINED XED_IFORMFL_VFNMSUBPD_LAST_DEFINED XED_IFORMFL_VFNMSUBPS_FIRST_DEFINED XED_IFORMFL_VFNMSUBPS_LAST_DEFINED XED_IFORMFL_VFNMSUBSD_FIRST_DEFINED XED_IFORMFL_VFNMSUBSD_LAST_DEFINED XED_IFORMFL_VFNMSUBSS_FIRST_DEFINED XED_IFORMFL_VFNMSUBSS_LAST_DEFINED XED_IFORMFL_VFPCLASSPD_FIRST_DEFINED XED_IFORMFL_VFPCLASSPD_LAST_DEFINED XED_IFORMFL_VFPCLASSPH_FIRST_DEFINED XED_IFORMFL_VFPCLASSPH_LAST_DEFINED XED_IFORMFL_VFPCLASSPS_FIRST_DEFINED XED_IFORMFL_VFPCLASSPS_LAST_DEFINED XED_IFORMFL_VFPCLASSSD_FIRST_DEFINED XED_IFORMFL_VFPCLASSSD_LAST_DEFINED XED_IFORMFL_VFPCLASSSH_FIRST_DEFINED XED_IFORMFL_VFPCLASSSH_LAST_DEFINED XED_IFORMFL_VFPCLASSSS_FIRST_DEFINED XED_IFORMFL_VFPCLASSSS_LAST_DEFINED XED_IFORMFL_VFRCZPD_FIRST_DEFINED XED_IFORMFL_VFRCZPD_LAST_DEFINED XED_IFORMFL_VFRCZPS_FIRST_DEFINED XED_IFORMFL_VFRCZPS_LAST_DEFINED XED_IFORMFL_VFRCZSD_FIRST_DEFINED XED_IFORMFL_VFRCZSD_LAST_DEFINED XED_IFORMFL_VFRCZSS_FIRST_DEFINED XED_IFORMFL_VFRCZSS_LAST_DEFINED XED_IFORMFL_VGATHERDPD_FIRST_DEFINED XED_IFORMFL_VGATHERDPD_LAST_DEFINED XED_IFORMFL_VGATHERDPS_FIRST_DEFINED XED_IFORMFL_VGATHERDPS_LAST_DEFINED XED_IFORMFL_VGATHERPF0DPD_FIRST_DEFINED XED_IFORMFL_VGATHERPF0DPD_LAST_DEFINED XED_IFORMFL_VGATHERPF0DPS_FIRST_DEFINED XED_IFORMFL_VGATHERPF0DPS_LAST_DEFINED XED_IFORMFL_VGATHERPF0QPD_FIRST_DEFINED XED_IFORMFL_VGATHERPF0QPD_LAST_DEFINED XED_IFORMFL_VGATHERPF0QPS_FIRST_DEFINED XED_IFORMFL_VGATHERPF0QPS_LAST_DEFINED XED_IFORMFL_VGATHERPF1DPD_FIRST_DEFINED XED_IFORMFL_VGATHERPF1DPD_LAST_DEFINED XED_IFORMFL_VGATHERPF1DPS_FIRST_DEFINED XED_IFORMFL_VGATHERPF1DPS_LAST_DEFINED XED_IFORMFL_VGATHERPF1QPD_FIRST_DEFINED XED_IFORMFL_VGATHERPF1QPD_LAST_DEFINED XED_IFORMFL_VGATHERPF1QPS_FIRST_DEFINED XED_IFORMFL_VGATHERPF1QPS_LAST_DEFINED XED_IFORMFL_VGATHERQPD_FIRST_DEFINED XED_IFORMFL_VGATHERQPD_LAST_DEFINED XED_IFORMFL_VGATHERQPS_FIRST_DEFINED XED_IFORMFL_VGATHERQPS_LAST_DEFINED XED_IFORMFL_VGETEXPPD_FIRST_DEFINED XED_IFORMFL_VGETEXPPD_LAST_DEFINED XED_IFORMFL_VGETEXPPH_FIRST_DEFINED XED_IFORMFL_VGETEXPPH_LAST_DEFINED XED_IFORMFL_VGETEXPPS_FIRST_DEFINED XED_IFORMFL_VGETEXPPS_LAST_DEFINED XED_IFORMFL_VGETEXPSD_FIRST_DEFINED XED_IFORMFL_VGETEXPSD_LAST_DEFINED XED_IFORMFL_VGETEXPSH_FIRST_DEFINED XED_IFORMFL_VGETEXPSH_LAST_DEFINED XED_IFORMFL_VGETEXPSS_FIRST_DEFINED XED_IFORMFL_VGETEXPSS_LAST_DEFINED XED_IFORMFL_VGETMANTPD_FIRST_DEFINED XED_IFORMFL_VGETMANTPD_LAST_DEFINED XED_IFORMFL_VGETMANTPH_FIRST_DEFINED XED_IFORMFL_VGETMANTPH_LAST_DEFINED XED_IFORMFL_VGETMANTPS_FIRST_DEFINED XED_IFORMFL_VGETMANTPS_LAST_DEFINED XED_IFORMFL_VGETMANTSD_FIRST_DEFINED XED_IFORMFL_VGETMANTSD_LAST_DEFINED XED_IFORMFL_VGETMANTSH_FIRST_DEFINED XED_IFORMFL_VGETMANTSH_LAST_DEFINED XED_IFORMFL_VGETMANTSS_FIRST_DEFINED XED_IFORMFL_VGETMANTSS_LAST_DEFINED XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST_DEFINED XED_IFORMFL_VGF2P8AFFINEINVQB_LAST_DEFINED XED_IFORMFL_VGF2P8AFFINEQB_FIRST_DEFINED XED_IFORMFL_VGF2P8AFFINEQB_LAST_DEFINED XED_IFORMFL_VGF2P8MULB_FIRST_DEFINED XED_IFORMFL_VGF2P8MULB_LAST_DEFINED XED_IFORMFL_VHADDPD_FIRST_DEFINED XED_IFORMFL_VHADDPD_LAST_DEFINED XED_IFORMFL_VHADDPS_FIRST_DEFINED XED_IFORMFL_VHADDPS_LAST_DEFINED XED_IFORMFL_VHSUBPD_FIRST_DEFINED XED_IFORMFL_VHSUBPD_LAST_DEFINED XED_IFORMFL_VHSUBPS_FIRST_DEFINED XED_IFORMFL_VHSUBPS_LAST_DEFINED XED_IFORMFL_VINSERTF32X4_FIRST_DEFINED XED_IFORMFL_VINSERTF32X4_LAST_DEFINED XED_IFORMFL_VINSERTF32X8_FIRST_DEFINED XED_IFORMFL_VINSERTF32X8_LAST_DEFINED XED_IFORMFL_VINSERTF64X2_FIRST_DEFINED XED_IFORMFL_VINSERTF64X2_LAST_DEFINED XED_IFORMFL_VINSERTF64X4_FIRST_DEFINED XED_IFORMFL_VINSERTF64X4_LAST_DEFINED XED_IFORMFL_VINSERTF128_FIRST_DEFINED XED_IFORMFL_VINSERTF128_LAST_DEFINED XED_IFORMFL_VINSERTI32X4_FIRST_DEFINED XED_IFORMFL_VINSERTI32X4_LAST_DEFINED XED_IFORMFL_VINSERTI32X8_FIRST_DEFINED XED_IFORMFL_VINSERTI32X8_LAST_DEFINED XED_IFORMFL_VINSERTI64X2_FIRST_DEFINED XED_IFORMFL_VINSERTI64X2_LAST_DEFINED XED_IFORMFL_VINSERTI64X4_FIRST_DEFINED XED_IFORMFL_VINSERTI64X4_LAST_DEFINED XED_IFORMFL_VINSERTI128_FIRST_DEFINED XED_IFORMFL_VINSERTI128_LAST_DEFINED XED_IFORMFL_VINSERTPS_FIRST_DEFINED XED_IFORMFL_VINSERTPS_LAST_DEFINED XED_IFORMFL_VLDDQU_FIRST_DEFINED XED_IFORMFL_VLDDQU_LAST_DEFINED XED_IFORMFL_VLDMXCSR_FIRST_DEFINED XED_IFORMFL_VLDMXCSR_LAST_DEFINED XED_IFORMFL_VMASKMOVDQU_FIRST_DEFINED XED_IFORMFL_VMASKMOVDQU_LAST_DEFINED XED_IFORMFL_VMASKMOVPD_FIRST_DEFINED XED_IFORMFL_VMASKMOVPD_LAST_DEFINED XED_IFORMFL_VMASKMOVPS_FIRST_DEFINED XED_IFORMFL_VMASKMOVPS_LAST_DEFINED XED_IFORMFL_VMAXPD_FIRST_DEFINED XED_IFORMFL_VMAXPD_LAST_DEFINED XED_IFORMFL_VMAXPH_FIRST_DEFINED XED_IFORMFL_VMAXPH_LAST_DEFINED XED_IFORMFL_VMAXPS_FIRST_DEFINED XED_IFORMFL_VMAXPS_LAST_DEFINED XED_IFORMFL_VMAXSD_FIRST_DEFINED XED_IFORMFL_VMAXSD_LAST_DEFINED XED_IFORMFL_VMAXSH_FIRST_DEFINED XED_IFORMFL_VMAXSH_LAST_DEFINED XED_IFORMFL_VMAXSS_FIRST_DEFINED XED_IFORMFL_VMAXSS_LAST_DEFINED XED_IFORMFL_VMCALL_FIRST_DEFINED XED_IFORMFL_VMCALL_LAST_DEFINED XED_IFORMFL_VMCLEAR_FIRST_DEFINED XED_IFORMFL_VMCLEAR_LAST_DEFINED XED_IFORMFL_VMFUNC_FIRST_DEFINED XED_IFORMFL_VMFUNC_LAST_DEFINED XED_IFORMFL_VMINPD_FIRST_DEFINED XED_IFORMFL_VMINPD_LAST_DEFINED XED_IFORMFL_VMINPH_FIRST_DEFINED XED_IFORMFL_VMINPH_LAST_DEFINED XED_IFORMFL_VMINPS_FIRST_DEFINED XED_IFORMFL_VMINPS_LAST_DEFINED XED_IFORMFL_VMINSD_FIRST_DEFINED XED_IFORMFL_VMINSD_LAST_DEFINED XED_IFORMFL_VMINSH_FIRST_DEFINED XED_IFORMFL_VMINSH_LAST_DEFINED XED_IFORMFL_VMINSS_FIRST_DEFINED XED_IFORMFL_VMINSS_LAST_DEFINED XED_IFORMFL_VMLAUNCH_FIRST_DEFINED XED_IFORMFL_VMLAUNCH_LAST_DEFINED XED_IFORMFL_VMLOAD_FIRST_DEFINED XED_IFORMFL_VMLOAD_LAST_DEFINED XED_IFORMFL_VMMCALL_FIRST_DEFINED XED_IFORMFL_VMMCALL_LAST_DEFINED XED_IFORMFL_VMOVAPD_FIRST_DEFINED XED_IFORMFL_VMOVAPD_LAST_DEFINED XED_IFORMFL_VMOVAPS_FIRST_DEFINED XED_IFORMFL_VMOVAPS_LAST_DEFINED XED_IFORMFL_VMOVDDUP_FIRST_DEFINED XED_IFORMFL_VMOVDDUP_LAST_DEFINED XED_IFORMFL_VMOVDQA32_FIRST_DEFINED XED_IFORMFL_VMOVDQA32_LAST_DEFINED XED_IFORMFL_VMOVDQA64_FIRST_DEFINED XED_IFORMFL_VMOVDQA64_LAST_DEFINED XED_IFORMFL_VMOVDQA_FIRST_DEFINED XED_IFORMFL_VMOVDQA_LAST_DEFINED XED_IFORMFL_VMOVDQU8_FIRST_DEFINED XED_IFORMFL_VMOVDQU8_LAST_DEFINED XED_IFORMFL_VMOVDQU16_FIRST_DEFINED XED_IFORMFL_VMOVDQU16_LAST_DEFINED XED_IFORMFL_VMOVDQU32_FIRST_DEFINED XED_IFORMFL_VMOVDQU32_LAST_DEFINED XED_IFORMFL_VMOVDQU64_FIRST_DEFINED XED_IFORMFL_VMOVDQU64_LAST_DEFINED XED_IFORMFL_VMOVDQU_FIRST_DEFINED XED_IFORMFL_VMOVDQU_LAST_DEFINED XED_IFORMFL_VMOVD_FIRST_DEFINED XED_IFORMFL_VMOVD_LAST_DEFINED XED_IFORMFL_VMOVHLPS_FIRST_DEFINED XED_IFORMFL_VMOVHLPS_LAST_DEFINED XED_IFORMFL_VMOVHPD_FIRST_DEFINED XED_IFORMFL_VMOVHPD_LAST_DEFINED XED_IFORMFL_VMOVHPS_FIRST_DEFINED XED_IFORMFL_VMOVHPS_LAST_DEFINED XED_IFORMFL_VMOVLHPS_FIRST_DEFINED XED_IFORMFL_VMOVLHPS_LAST_DEFINED XED_IFORMFL_VMOVLPD_FIRST_DEFINED XED_IFORMFL_VMOVLPD_LAST_DEFINED XED_IFORMFL_VMOVLPS_FIRST_DEFINED XED_IFORMFL_VMOVLPS_LAST_DEFINED XED_IFORMFL_VMOVMSKPD_FIRST_DEFINED XED_IFORMFL_VMOVMSKPD_LAST_DEFINED XED_IFORMFL_VMOVMSKPS_FIRST_DEFINED XED_IFORMFL_VMOVMSKPS_LAST_DEFINED XED_IFORMFL_VMOVNTDQA_FIRST_DEFINED XED_IFORMFL_VMOVNTDQA_LAST_DEFINED XED_IFORMFL_VMOVNTDQ_FIRST_DEFINED XED_IFORMFL_VMOVNTDQ_LAST_DEFINED XED_IFORMFL_VMOVNTPD_FIRST_DEFINED XED_IFORMFL_VMOVNTPD_LAST_DEFINED XED_IFORMFL_VMOVNTPS_FIRST_DEFINED XED_IFORMFL_VMOVNTPS_LAST_DEFINED XED_IFORMFL_VMOVQ_FIRST_DEFINED XED_IFORMFL_VMOVQ_LAST_DEFINED XED_IFORMFL_VMOVSD_FIRST_DEFINED XED_IFORMFL_VMOVSD_LAST_DEFINED XED_IFORMFL_VMOVSHDUP_FIRST_DEFINED XED_IFORMFL_VMOVSHDUP_LAST_DEFINED XED_IFORMFL_VMOVSH_FIRST_DEFINED XED_IFORMFL_VMOVSH_LAST_DEFINED XED_IFORMFL_VMOVSLDUP_FIRST_DEFINED XED_IFORMFL_VMOVSLDUP_LAST_DEFINED XED_IFORMFL_VMOVSS_FIRST_DEFINED XED_IFORMFL_VMOVSS_LAST_DEFINED XED_IFORMFL_VMOVUPD_FIRST_DEFINED XED_IFORMFL_VMOVUPD_LAST_DEFINED XED_IFORMFL_VMOVUPS_FIRST_DEFINED XED_IFORMFL_VMOVUPS_LAST_DEFINED XED_IFORMFL_VMOVW_FIRST_DEFINED XED_IFORMFL_VMOVW_LAST_DEFINED XED_IFORMFL_VMPSADBW_FIRST_DEFINED XED_IFORMFL_VMPSADBW_LAST_DEFINED XED_IFORMFL_VMPTRLD_FIRST_DEFINED XED_IFORMFL_VMPTRLD_LAST_DEFINED XED_IFORMFL_VMPTRST_FIRST_DEFINED XED_IFORMFL_VMPTRST_LAST_DEFINED XED_IFORMFL_VMREAD_FIRST_DEFINED XED_IFORMFL_VMREAD_LAST_DEFINED XED_IFORMFL_VMRESUME_FIRST_DEFINED XED_IFORMFL_VMRESUME_LAST_DEFINED XED_IFORMFL_VMRUN_FIRST_DEFINED XED_IFORMFL_VMRUN_LAST_DEFINED XED_IFORMFL_VMSAVE_FIRST_DEFINED XED_IFORMFL_VMSAVE_LAST_DEFINED XED_IFORMFL_VMULPD_FIRST_DEFINED XED_IFORMFL_VMULPD_LAST_DEFINED XED_IFORMFL_VMULPH_FIRST_DEFINED XED_IFORMFL_VMULPH_LAST_DEFINED XED_IFORMFL_VMULPS_FIRST_DEFINED XED_IFORMFL_VMULPS_LAST_DEFINED XED_IFORMFL_VMULSD_FIRST_DEFINED XED_IFORMFL_VMULSD_LAST_DEFINED XED_IFORMFL_VMULSH_FIRST_DEFINED XED_IFORMFL_VMULSH_LAST_DEFINED XED_IFORMFL_VMULSS_FIRST_DEFINED XED_IFORMFL_VMULSS_LAST_DEFINED XED_IFORMFL_VMWRITE_FIRST_DEFINED XED_IFORMFL_VMWRITE_LAST_DEFINED XED_IFORMFL_VMXOFF_FIRST_DEFINED XED_IFORMFL_VMXOFF_LAST_DEFINED XED_IFORMFL_VMXON_FIRST_DEFINED XED_IFORMFL_VMXON_LAST_DEFINED XED_IFORMFL_VORPD_FIRST_DEFINED XED_IFORMFL_VORPD_LAST_DEFINED XED_IFORMFL_VORPS_FIRST_DEFINED XED_IFORMFL_VORPS_LAST_DEFINED XED_IFORMFL_VP2INTERSECTD_FIRST_DEFINED XED_IFORMFL_VP2INTERSECTD_LAST_DEFINED XED_IFORMFL_VP2INTERSECTQ_FIRST_DEFINED XED_IFORMFL_VP2INTERSECTQ_LAST_DEFINED XED_IFORMFL_VP4DPWSSDS_FIRST_DEFINED XED_IFORMFL_VP4DPWSSDS_LAST_DEFINED XED_IFORMFL_VP4DPWSSD_FIRST_DEFINED XED_IFORMFL_VP4DPWSSD_LAST_DEFINED XED_IFORMFL_VPABSB_FIRST_DEFINED XED_IFORMFL_VPABSB_LAST_DEFINED XED_IFORMFL_VPABSD_FIRST_DEFINED XED_IFORMFL_VPABSD_LAST_DEFINED XED_IFORMFL_VPABSQ_FIRST_DEFINED XED_IFORMFL_VPABSQ_LAST_DEFINED XED_IFORMFL_VPABSW_FIRST_DEFINED XED_IFORMFL_VPABSW_LAST_DEFINED XED_IFORMFL_VPACKSSDW_FIRST_DEFINED XED_IFORMFL_VPACKSSDW_LAST_DEFINED XED_IFORMFL_VPACKSSWB_FIRST_DEFINED XED_IFORMFL_VPACKSSWB_LAST_DEFINED XED_IFORMFL_VPACKUSDW_FIRST_DEFINED XED_IFORMFL_VPACKUSDW_LAST_DEFINED XED_IFORMFL_VPACKUSWB_FIRST_DEFINED XED_IFORMFL_VPACKUSWB_LAST_DEFINED XED_IFORMFL_VPADDB_FIRST_DEFINED XED_IFORMFL_VPADDB_LAST_DEFINED XED_IFORMFL_VPADDD_FIRST_DEFINED XED_IFORMFL_VPADDD_LAST_DEFINED XED_IFORMFL_VPADDQ_FIRST_DEFINED XED_IFORMFL_VPADDQ_LAST_DEFINED XED_IFORMFL_VPADDSB_FIRST_DEFINED XED_IFORMFL_VPADDSB_LAST_DEFINED XED_IFORMFL_VPADDSW_FIRST_DEFINED XED_IFORMFL_VPADDSW_LAST_DEFINED XED_IFORMFL_VPADDUSB_FIRST_DEFINED XED_IFORMFL_VPADDUSB_LAST_DEFINED XED_IFORMFL_VPADDUSW_FIRST_DEFINED XED_IFORMFL_VPADDUSW_LAST_DEFINED XED_IFORMFL_VPADDW_FIRST_DEFINED XED_IFORMFL_VPADDW_LAST_DEFINED XED_IFORMFL_VPALIGNR_FIRST_DEFINED XED_IFORMFL_VPALIGNR_LAST_DEFINED XED_IFORMFL_VPANDD_FIRST_DEFINED XED_IFORMFL_VPANDD_LAST_DEFINED XED_IFORMFL_VPANDND_FIRST_DEFINED XED_IFORMFL_VPANDND_LAST_DEFINED XED_IFORMFL_VPANDNQ_FIRST_DEFINED XED_IFORMFL_VPANDNQ_LAST_DEFINED XED_IFORMFL_VPANDN_FIRST_DEFINED XED_IFORMFL_VPANDN_LAST_DEFINED XED_IFORMFL_VPANDQ_FIRST_DEFINED XED_IFORMFL_VPANDQ_LAST_DEFINED XED_IFORMFL_VPAND_FIRST_DEFINED XED_IFORMFL_VPAND_LAST_DEFINED XED_IFORMFL_VPAVGB_FIRST_DEFINED XED_IFORMFL_VPAVGB_LAST_DEFINED XED_IFORMFL_VPAVGW_FIRST_DEFINED XED_IFORMFL_VPAVGW_LAST_DEFINED XED_IFORMFL_VPBLENDD_FIRST_DEFINED XED_IFORMFL_VPBLENDD_LAST_DEFINED XED_IFORMFL_VPBLENDMB_FIRST_DEFINED XED_IFORMFL_VPBLENDMB_LAST_DEFINED XED_IFORMFL_VPBLENDMD_FIRST_DEFINED XED_IFORMFL_VPBLENDMD_LAST_DEFINED XED_IFORMFL_VPBLENDMQ_FIRST_DEFINED XED_IFORMFL_VPBLENDMQ_LAST_DEFINED XED_IFORMFL_VPBLENDMW_FIRST_DEFINED XED_IFORMFL_VPBLENDMW_LAST_DEFINED XED_IFORMFL_VPBLENDVB_FIRST_DEFINED XED_IFORMFL_VPBLENDVB_LAST_DEFINED XED_IFORMFL_VPBLENDW_FIRST_DEFINED XED_IFORMFL_VPBLENDW_LAST_DEFINED XED_IFORMFL_VPBROADCASTB_FIRST_DEFINED XED_IFORMFL_VPBROADCASTB_LAST_DEFINED XED_IFORMFL_VPBROADCASTD_FIRST_DEFINED XED_IFORMFL_VPBROADCASTD_LAST_DEFINED XED_IFORMFL_VPBROADCASTMB2Q_FIRST_DEFINED XED_IFORMFL_VPBROADCASTMB2Q_LAST_DEFINED XED_IFORMFL_VPBROADCASTMW2D_FIRST_DEFINED XED_IFORMFL_VPBROADCASTMW2D_LAST_DEFINED XED_IFORMFL_VPBROADCASTQ_FIRST_DEFINED XED_IFORMFL_VPBROADCASTQ_LAST_DEFINED XED_IFORMFL_VPBROADCASTW_FIRST_DEFINED XED_IFORMFL_VPBROADCASTW_LAST_DEFINED XED_IFORMFL_VPCLMULQDQ_FIRST_DEFINED XED_IFORMFL_VPCLMULQDQ_LAST_DEFINED XED_IFORMFL_VPCMOV_FIRST_DEFINED XED_IFORMFL_VPCMOV_LAST_DEFINED XED_IFORMFL_VPCMPB_FIRST_DEFINED XED_IFORMFL_VPCMPB_LAST_DEFINED XED_IFORMFL_VPCMPD_FIRST_DEFINED XED_IFORMFL_VPCMPD_LAST_DEFINED XED_IFORMFL_VPCMPEQB_FIRST_DEFINED XED_IFORMFL_VPCMPEQB_LAST_DEFINED XED_IFORMFL_VPCMPEQD_FIRST_DEFINED XED_IFORMFL_VPCMPEQD_LAST_DEFINED XED_IFORMFL_VPCMPEQQ_FIRST_DEFINED XED_IFORMFL_VPCMPEQQ_LAST_DEFINED XED_IFORMFL_VPCMPEQW_FIRST_DEFINED XED_IFORMFL_VPCMPEQW_LAST_DEFINED XED_IFORMFL_VPCMPESTRI64_FIRST_DEFINED XED_IFORMFL_VPCMPESTRI64_LAST_DEFINED XED_IFORMFL_VPCMPESTRI_FIRST_DEFINED XED_IFORMFL_VPCMPESTRI_LAST_DEFINED XED_IFORMFL_VPCMPESTRM64_FIRST_DEFINED XED_IFORMFL_VPCMPESTRM64_LAST_DEFINED XED_IFORMFL_VPCMPESTRM_FIRST_DEFINED XED_IFORMFL_VPCMPESTRM_LAST_DEFINED XED_IFORMFL_VPCMPGTB_FIRST_DEFINED XED_IFORMFL_VPCMPGTB_LAST_DEFINED XED_IFORMFL_VPCMPGTD_FIRST_DEFINED XED_IFORMFL_VPCMPGTD_LAST_DEFINED XED_IFORMFL_VPCMPGTQ_FIRST_DEFINED XED_IFORMFL_VPCMPGTQ_LAST_DEFINED XED_IFORMFL_VPCMPGTW_FIRST_DEFINED XED_IFORMFL_VPCMPGTW_LAST_DEFINED XED_IFORMFL_VPCMPISTRI64_FIRST_DEFINED XED_IFORMFL_VPCMPISTRI64_LAST_DEFINED XED_IFORMFL_VPCMPISTRI_FIRST_DEFINED XED_IFORMFL_VPCMPISTRI_LAST_DEFINED XED_IFORMFL_VPCMPISTRM_FIRST_DEFINED XED_IFORMFL_VPCMPISTRM_LAST_DEFINED XED_IFORMFL_VPCMPQ_FIRST_DEFINED XED_IFORMFL_VPCMPQ_LAST_DEFINED XED_IFORMFL_VPCMPUB_FIRST_DEFINED XED_IFORMFL_VPCMPUB_LAST_DEFINED XED_IFORMFL_VPCMPUD_FIRST_DEFINED XED_IFORMFL_VPCMPUD_LAST_DEFINED XED_IFORMFL_VPCMPUQ_FIRST_DEFINED XED_IFORMFL_VPCMPUQ_LAST_DEFINED XED_IFORMFL_VPCMPUW_FIRST_DEFINED XED_IFORMFL_VPCMPUW_LAST_DEFINED XED_IFORMFL_VPCMPW_FIRST_DEFINED XED_IFORMFL_VPCMPW_LAST_DEFINED XED_IFORMFL_VPCOMB_FIRST_DEFINED XED_IFORMFL_VPCOMB_LAST_DEFINED XED_IFORMFL_VPCOMD_FIRST_DEFINED XED_IFORMFL_VPCOMD_LAST_DEFINED XED_IFORMFL_VPCOMPRESSB_FIRST_DEFINED XED_IFORMFL_VPCOMPRESSB_LAST_DEFINED XED_IFORMFL_VPCOMPRESSD_FIRST_DEFINED XED_IFORMFL_VPCOMPRESSD_LAST_DEFINED XED_IFORMFL_VPCOMPRESSQ_FIRST_DEFINED XED_IFORMFL_VPCOMPRESSQ_LAST_DEFINED XED_IFORMFL_VPCOMPRESSW_FIRST_DEFINED XED_IFORMFL_VPCOMPRESSW_LAST_DEFINED XED_IFORMFL_VPCOMQ_FIRST_DEFINED XED_IFORMFL_VPCOMQ_LAST_DEFINED XED_IFORMFL_VPCOMUB_FIRST_DEFINED XED_IFORMFL_VPCOMUB_LAST_DEFINED XED_IFORMFL_VPCOMUD_FIRST_DEFINED XED_IFORMFL_VPCOMUD_LAST_DEFINED XED_IFORMFL_VPCOMUQ_FIRST_DEFINED XED_IFORMFL_VPCOMUQ_LAST_DEFINED XED_IFORMFL_VPCOMUW_FIRST_DEFINED XED_IFORMFL_VPCOMUW_LAST_DEFINED XED_IFORMFL_VPCOMW_FIRST_DEFINED XED_IFORMFL_VPCOMW_LAST_DEFINED XED_IFORMFL_VPCONFLICTD_FIRST_DEFINED XED_IFORMFL_VPCONFLICTD_LAST_DEFINED XED_IFORMFL_VPCONFLICTQ_FIRST_DEFINED XED_IFORMFL_VPCONFLICTQ_LAST_DEFINED XED_IFORMFL_VPDPBSSDS_FIRST_DEFINED XED_IFORMFL_VPDPBSSDS_LAST_DEFINED XED_IFORMFL_VPDPBSSD_FIRST_DEFINED XED_IFORMFL_VPDPBSSD_LAST_DEFINED XED_IFORMFL_VPDPBSUDS_FIRST_DEFINED XED_IFORMFL_VPDPBSUDS_LAST_DEFINED XED_IFORMFL_VPDPBSUD_FIRST_DEFINED XED_IFORMFL_VPDPBSUD_LAST_DEFINED XED_IFORMFL_VPDPBUSDS_FIRST_DEFINED XED_IFORMFL_VPDPBUSDS_LAST_DEFINED XED_IFORMFL_VPDPBUSD_FIRST_DEFINED XED_IFORMFL_VPDPBUSD_LAST_DEFINED XED_IFORMFL_VPDPBUUDS_FIRST_DEFINED XED_IFORMFL_VPDPBUUDS_LAST_DEFINED XED_IFORMFL_VPDPBUUD_FIRST_DEFINED XED_IFORMFL_VPDPBUUD_LAST_DEFINED XED_IFORMFL_VPDPWSSDS_FIRST_DEFINED XED_IFORMFL_VPDPWSSDS_LAST_DEFINED XED_IFORMFL_VPDPWSSD_FIRST_DEFINED XED_IFORMFL_VPDPWSSD_LAST_DEFINED XED_IFORMFL_VPDPWSUDS_FIRST_DEFINED XED_IFORMFL_VPDPWSUDS_LAST_DEFINED XED_IFORMFL_VPDPWSUD_FIRST_DEFINED XED_IFORMFL_VPDPWSUD_LAST_DEFINED XED_IFORMFL_VPDPWUSDS_FIRST_DEFINED XED_IFORMFL_VPDPWUSDS_LAST_DEFINED XED_IFORMFL_VPDPWUSD_FIRST_DEFINED XED_IFORMFL_VPDPWUSD_LAST_DEFINED XED_IFORMFL_VPDPWUUDS_FIRST_DEFINED XED_IFORMFL_VPDPWUUDS_LAST_DEFINED XED_IFORMFL_VPDPWUUD_FIRST_DEFINED XED_IFORMFL_VPDPWUUD_LAST_DEFINED XED_IFORMFL_VPERM2F128_FIRST_DEFINED XED_IFORMFL_VPERM2F128_LAST_DEFINED XED_IFORMFL_VPERM2I128_FIRST_DEFINED XED_IFORMFL_VPERM2I128_LAST_DEFINED XED_IFORMFL_VPERMB_FIRST_DEFINED XED_IFORMFL_VPERMB_LAST_DEFINED XED_IFORMFL_VPERMD_FIRST_DEFINED XED_IFORMFL_VPERMD_LAST_DEFINED XED_IFORMFL_VPERMI2B_FIRST_DEFINED XED_IFORMFL_VPERMI2B_LAST_DEFINED XED_IFORMFL_VPERMI2D_FIRST_DEFINED XED_IFORMFL_VPERMI2D_LAST_DEFINED XED_IFORMFL_VPERMI2PD_FIRST_DEFINED XED_IFORMFL_VPERMI2PD_LAST_DEFINED XED_IFORMFL_VPERMI2PS_FIRST_DEFINED XED_IFORMFL_VPERMI2PS_LAST_DEFINED XED_IFORMFL_VPERMI2Q_FIRST_DEFINED XED_IFORMFL_VPERMI2Q_LAST_DEFINED XED_IFORMFL_VPERMI2W_FIRST_DEFINED XED_IFORMFL_VPERMI2W_LAST_DEFINED XED_IFORMFL_VPERMIL2PD_FIRST_DEFINED XED_IFORMFL_VPERMIL2PD_LAST_DEFINED XED_IFORMFL_VPERMIL2PS_FIRST_DEFINED XED_IFORMFL_VPERMIL2PS_LAST_DEFINED XED_IFORMFL_VPERMILPD_FIRST_DEFINED XED_IFORMFL_VPERMILPD_LAST_DEFINED XED_IFORMFL_VPERMILPS_FIRST_DEFINED XED_IFORMFL_VPERMILPS_LAST_DEFINED XED_IFORMFL_VPERMPD_FIRST_DEFINED XED_IFORMFL_VPERMPD_LAST_DEFINED XED_IFORMFL_VPERMPS_FIRST_DEFINED XED_IFORMFL_VPERMPS_LAST_DEFINED XED_IFORMFL_VPERMQ_FIRST_DEFINED XED_IFORMFL_VPERMQ_LAST_DEFINED XED_IFORMFL_VPERMT2B_FIRST_DEFINED XED_IFORMFL_VPERMT2B_LAST_DEFINED XED_IFORMFL_VPERMT2D_FIRST_DEFINED XED_IFORMFL_VPERMT2D_LAST_DEFINED XED_IFORMFL_VPERMT2PD_FIRST_DEFINED XED_IFORMFL_VPERMT2PD_LAST_DEFINED XED_IFORMFL_VPERMT2PS_FIRST_DEFINED XED_IFORMFL_VPERMT2PS_LAST_DEFINED XED_IFORMFL_VPERMT2Q_FIRST_DEFINED XED_IFORMFL_VPERMT2Q_LAST_DEFINED XED_IFORMFL_VPERMT2W_FIRST_DEFINED XED_IFORMFL_VPERMT2W_LAST_DEFINED XED_IFORMFL_VPERMW_FIRST_DEFINED XED_IFORMFL_VPERMW_LAST_DEFINED XED_IFORMFL_VPEXPANDB_FIRST_DEFINED XED_IFORMFL_VPEXPANDB_LAST_DEFINED XED_IFORMFL_VPEXPANDD_FIRST_DEFINED XED_IFORMFL_VPEXPANDD_LAST_DEFINED XED_IFORMFL_VPEXPANDQ_FIRST_DEFINED XED_IFORMFL_VPEXPANDQ_LAST_DEFINED XED_IFORMFL_VPEXPANDW_FIRST_DEFINED XED_IFORMFL_VPEXPANDW_LAST_DEFINED XED_IFORMFL_VPEXTRB_FIRST_DEFINED XED_IFORMFL_VPEXTRB_LAST_DEFINED XED_IFORMFL_VPEXTRD_FIRST_DEFINED XED_IFORMFL_VPEXTRD_LAST_DEFINED XED_IFORMFL_VPEXTRQ_FIRST_DEFINED XED_IFORMFL_VPEXTRQ_LAST_DEFINED XED_IFORMFL_VPEXTRW_C5_FIRST_DEFINED XED_IFORMFL_VPEXTRW_C5_LAST_DEFINED XED_IFORMFL_VPEXTRW_FIRST_DEFINED XED_IFORMFL_VPEXTRW_LAST_DEFINED XED_IFORMFL_VPGATHERDD_FIRST_DEFINED XED_IFORMFL_VPGATHERDD_LAST_DEFINED XED_IFORMFL_VPGATHERDQ_FIRST_DEFINED XED_IFORMFL_VPGATHERDQ_LAST_DEFINED XED_IFORMFL_VPGATHERQD_FIRST_DEFINED XED_IFORMFL_VPGATHERQD_LAST_DEFINED XED_IFORMFL_VPGATHERQQ_FIRST_DEFINED XED_IFORMFL_VPGATHERQQ_LAST_DEFINED XED_IFORMFL_VPHADDBD_FIRST_DEFINED XED_IFORMFL_VPHADDBD_LAST_DEFINED XED_IFORMFL_VPHADDBQ_FIRST_DEFINED XED_IFORMFL_VPHADDBQ_LAST_DEFINED XED_IFORMFL_VPHADDBW_FIRST_DEFINED XED_IFORMFL_VPHADDBW_LAST_DEFINED XED_IFORMFL_VPHADDDQ_FIRST_DEFINED XED_IFORMFL_VPHADDDQ_LAST_DEFINED XED_IFORMFL_VPHADDD_FIRST_DEFINED XED_IFORMFL_VPHADDD_LAST_DEFINED XED_IFORMFL_VPHADDSW_FIRST_DEFINED XED_IFORMFL_VPHADDSW_LAST_DEFINED XED_IFORMFL_VPHADDUBD_FIRST_DEFINED XED_IFORMFL_VPHADDUBD_LAST_DEFINED XED_IFORMFL_VPHADDUBQ_FIRST_DEFINED XED_IFORMFL_VPHADDUBQ_LAST_DEFINED XED_IFORMFL_VPHADDUBW_FIRST_DEFINED XED_IFORMFL_VPHADDUBW_LAST_DEFINED XED_IFORMFL_VPHADDUDQ_FIRST_DEFINED XED_IFORMFL_VPHADDUDQ_LAST_DEFINED XED_IFORMFL_VPHADDUWD_FIRST_DEFINED XED_IFORMFL_VPHADDUWD_LAST_DEFINED XED_IFORMFL_VPHADDUWQ_FIRST_DEFINED XED_IFORMFL_VPHADDUWQ_LAST_DEFINED XED_IFORMFL_VPHADDWD_FIRST_DEFINED XED_IFORMFL_VPHADDWD_LAST_DEFINED XED_IFORMFL_VPHADDWQ_FIRST_DEFINED XED_IFORMFL_VPHADDWQ_LAST_DEFINED XED_IFORMFL_VPHADDW_FIRST_DEFINED XED_IFORMFL_VPHADDW_LAST_DEFINED XED_IFORMFL_VPHMINPOSUW_FIRST_DEFINED XED_IFORMFL_VPHMINPOSUW_LAST_DEFINED XED_IFORMFL_VPHSUBBW_FIRST_DEFINED XED_IFORMFL_VPHSUBBW_LAST_DEFINED XED_IFORMFL_VPHSUBDQ_FIRST_DEFINED XED_IFORMFL_VPHSUBDQ_LAST_DEFINED XED_IFORMFL_VPHSUBD_FIRST_DEFINED XED_IFORMFL_VPHSUBD_LAST_DEFINED XED_IFORMFL_VPHSUBSW_FIRST_DEFINED XED_IFORMFL_VPHSUBSW_LAST_DEFINED XED_IFORMFL_VPHSUBWD_FIRST_DEFINED XED_IFORMFL_VPHSUBWD_LAST_DEFINED XED_IFORMFL_VPHSUBW_FIRST_DEFINED XED_IFORMFL_VPHSUBW_LAST_DEFINED XED_IFORMFL_VPINSRB_FIRST_DEFINED XED_IFORMFL_VPINSRB_LAST_DEFINED XED_IFORMFL_VPINSRD_FIRST_DEFINED XED_IFORMFL_VPINSRD_LAST_DEFINED XED_IFORMFL_VPINSRQ_FIRST_DEFINED XED_IFORMFL_VPINSRQ_LAST_DEFINED XED_IFORMFL_VPINSRW_FIRST_DEFINED XED_IFORMFL_VPINSRW_LAST_DEFINED XED_IFORMFL_VPLZCNTD_FIRST_DEFINED XED_IFORMFL_VPLZCNTD_LAST_DEFINED XED_IFORMFL_VPLZCNTQ_FIRST_DEFINED XED_IFORMFL_VPLZCNTQ_LAST_DEFINED XED_IFORMFL_VPMACSDD_FIRST_DEFINED XED_IFORMFL_VPMACSDD_LAST_DEFINED XED_IFORMFL_VPMACSDQH_FIRST_DEFINED XED_IFORMFL_VPMACSDQH_LAST_DEFINED XED_IFORMFL_VPMACSDQL_FIRST_DEFINED XED_IFORMFL_VPMACSDQL_LAST_DEFINED XED_IFORMFL_VPMACSSDD_FIRST_DEFINED XED_IFORMFL_VPMACSSDD_LAST_DEFINED XED_IFORMFL_VPMACSSDQH_FIRST_DEFINED XED_IFORMFL_VPMACSSDQH_LAST_DEFINED XED_IFORMFL_VPMACSSDQL_FIRST_DEFINED XED_IFORMFL_VPMACSSDQL_LAST_DEFINED XED_IFORMFL_VPMACSSWD_FIRST_DEFINED XED_IFORMFL_VPMACSSWD_LAST_DEFINED XED_IFORMFL_VPMACSSWW_FIRST_DEFINED XED_IFORMFL_VPMACSSWW_LAST_DEFINED XED_IFORMFL_VPMACSWD_FIRST_DEFINED XED_IFORMFL_VPMACSWD_LAST_DEFINED XED_IFORMFL_VPMACSWW_FIRST_DEFINED XED_IFORMFL_VPMACSWW_LAST_DEFINED XED_IFORMFL_VPMADCSSWD_FIRST_DEFINED XED_IFORMFL_VPMADCSSWD_LAST_DEFINED XED_IFORMFL_VPMADCSWD_FIRST_DEFINED XED_IFORMFL_VPMADCSWD_LAST_DEFINED XED_IFORMFL_VPMADD52HUQ_FIRST_DEFINED XED_IFORMFL_VPMADD52HUQ_LAST_DEFINED XED_IFORMFL_VPMADD52LUQ_FIRST_DEFINED XED_IFORMFL_VPMADD52LUQ_LAST_DEFINED XED_IFORMFL_VPMADDUBSW_FIRST_DEFINED XED_IFORMFL_VPMADDUBSW_LAST_DEFINED XED_IFORMFL_VPMADDWD_FIRST_DEFINED XED_IFORMFL_VPMADDWD_LAST_DEFINED XED_IFORMFL_VPMASKMOVD_FIRST_DEFINED XED_IFORMFL_VPMASKMOVD_LAST_DEFINED XED_IFORMFL_VPMASKMOVQ_FIRST_DEFINED XED_IFORMFL_VPMASKMOVQ_LAST_DEFINED XED_IFORMFL_VPMAXSB_FIRST_DEFINED XED_IFORMFL_VPMAXSB_LAST_DEFINED XED_IFORMFL_VPMAXSD_FIRST_DEFINED XED_IFORMFL_VPMAXSD_LAST_DEFINED XED_IFORMFL_VPMAXSQ_FIRST_DEFINED XED_IFORMFL_VPMAXSQ_LAST_DEFINED XED_IFORMFL_VPMAXSW_FIRST_DEFINED XED_IFORMFL_VPMAXSW_LAST_DEFINED XED_IFORMFL_VPMAXUB_FIRST_DEFINED XED_IFORMFL_VPMAXUB_LAST_DEFINED XED_IFORMFL_VPMAXUD_FIRST_DEFINED XED_IFORMFL_VPMAXUD_LAST_DEFINED XED_IFORMFL_VPMAXUQ_FIRST_DEFINED XED_IFORMFL_VPMAXUQ_LAST_DEFINED XED_IFORMFL_VPMAXUW_FIRST_DEFINED XED_IFORMFL_VPMAXUW_LAST_DEFINED XED_IFORMFL_VPMINSB_FIRST_DEFINED XED_IFORMFL_VPMINSB_LAST_DEFINED XED_IFORMFL_VPMINSD_FIRST_DEFINED XED_IFORMFL_VPMINSD_LAST_DEFINED XED_IFORMFL_VPMINSQ_FIRST_DEFINED XED_IFORMFL_VPMINSQ_LAST_DEFINED XED_IFORMFL_VPMINSW_FIRST_DEFINED XED_IFORMFL_VPMINSW_LAST_DEFINED XED_IFORMFL_VPMINUB_FIRST_DEFINED XED_IFORMFL_VPMINUB_LAST_DEFINED XED_IFORMFL_VPMINUD_FIRST_DEFINED XED_IFORMFL_VPMINUD_LAST_DEFINED XED_IFORMFL_VPMINUQ_FIRST_DEFINED XED_IFORMFL_VPMINUQ_LAST_DEFINED XED_IFORMFL_VPMINUW_FIRST_DEFINED XED_IFORMFL_VPMINUW_LAST_DEFINED XED_IFORMFL_VPMOVB2M_FIRST_DEFINED XED_IFORMFL_VPMOVB2M_LAST_DEFINED XED_IFORMFL_VPMOVD2M_FIRST_DEFINED XED_IFORMFL_VPMOVD2M_LAST_DEFINED XED_IFORMFL_VPMOVDB_FIRST_DEFINED XED_IFORMFL_VPMOVDB_LAST_DEFINED XED_IFORMFL_VPMOVDW_FIRST_DEFINED XED_IFORMFL_VPMOVDW_LAST_DEFINED XED_IFORMFL_VPMOVM2B_FIRST_DEFINED XED_IFORMFL_VPMOVM2B_LAST_DEFINED XED_IFORMFL_VPMOVM2D_FIRST_DEFINED XED_IFORMFL_VPMOVM2D_LAST_DEFINED XED_IFORMFL_VPMOVM2Q_FIRST_DEFINED XED_IFORMFL_VPMOVM2Q_LAST_DEFINED XED_IFORMFL_VPMOVM2W_FIRST_DEFINED XED_IFORMFL_VPMOVM2W_LAST_DEFINED XED_IFORMFL_VPMOVMSKB_FIRST_DEFINED XED_IFORMFL_VPMOVMSKB_LAST_DEFINED XED_IFORMFL_VPMOVQ2M_FIRST_DEFINED XED_IFORMFL_VPMOVQ2M_LAST_DEFINED XED_IFORMFL_VPMOVQB_FIRST_DEFINED XED_IFORMFL_VPMOVQB_LAST_DEFINED XED_IFORMFL_VPMOVQD_FIRST_DEFINED XED_IFORMFL_VPMOVQD_LAST_DEFINED XED_IFORMFL_VPMOVQW_FIRST_DEFINED XED_IFORMFL_VPMOVQW_LAST_DEFINED XED_IFORMFL_VPMOVSDB_FIRST_DEFINED XED_IFORMFL_VPMOVSDB_LAST_DEFINED XED_IFORMFL_VPMOVSDW_FIRST_DEFINED XED_IFORMFL_VPMOVSDW_LAST_DEFINED XED_IFORMFL_VPMOVSQB_FIRST_DEFINED XED_IFORMFL_VPMOVSQB_LAST_DEFINED XED_IFORMFL_VPMOVSQD_FIRST_DEFINED XED_IFORMFL_VPMOVSQD_LAST_DEFINED XED_IFORMFL_VPMOVSQW_FIRST_DEFINED XED_IFORMFL_VPMOVSQW_LAST_DEFINED XED_IFORMFL_VPMOVSWB_FIRST_DEFINED XED_IFORMFL_VPMOVSWB_LAST_DEFINED XED_IFORMFL_VPMOVSXBD_FIRST_DEFINED XED_IFORMFL_VPMOVSXBD_LAST_DEFINED XED_IFORMFL_VPMOVSXBQ_FIRST_DEFINED XED_IFORMFL_VPMOVSXBQ_LAST_DEFINED XED_IFORMFL_VPMOVSXBW_FIRST_DEFINED XED_IFORMFL_VPMOVSXBW_LAST_DEFINED XED_IFORMFL_VPMOVSXDQ_FIRST_DEFINED XED_IFORMFL_VPMOVSXDQ_LAST_DEFINED XED_IFORMFL_VPMOVSXWD_FIRST_DEFINED XED_IFORMFL_VPMOVSXWD_LAST_DEFINED XED_IFORMFL_VPMOVSXWQ_FIRST_DEFINED XED_IFORMFL_VPMOVSXWQ_LAST_DEFINED XED_IFORMFL_VPMOVUSDB_FIRST_DEFINED XED_IFORMFL_VPMOVUSDB_LAST_DEFINED XED_IFORMFL_VPMOVUSDW_FIRST_DEFINED XED_IFORMFL_VPMOVUSDW_LAST_DEFINED XED_IFORMFL_VPMOVUSQB_FIRST_DEFINED XED_IFORMFL_VPMOVUSQB_LAST_DEFINED XED_IFORMFL_VPMOVUSQD_FIRST_DEFINED XED_IFORMFL_VPMOVUSQD_LAST_DEFINED XED_IFORMFL_VPMOVUSQW_FIRST_DEFINED XED_IFORMFL_VPMOVUSQW_LAST_DEFINED XED_IFORMFL_VPMOVUSWB_FIRST_DEFINED XED_IFORMFL_VPMOVUSWB_LAST_DEFINED XED_IFORMFL_VPMOVW2M_FIRST_DEFINED XED_IFORMFL_VPMOVW2M_LAST_DEFINED XED_IFORMFL_VPMOVWB_FIRST_DEFINED XED_IFORMFL_VPMOVWB_LAST_DEFINED XED_IFORMFL_VPMOVZXBD_FIRST_DEFINED XED_IFORMFL_VPMOVZXBD_LAST_DEFINED XED_IFORMFL_VPMOVZXBQ_FIRST_DEFINED XED_IFORMFL_VPMOVZXBQ_LAST_DEFINED XED_IFORMFL_VPMOVZXBW_FIRST_DEFINED XED_IFORMFL_VPMOVZXBW_LAST_DEFINED XED_IFORMFL_VPMOVZXDQ_FIRST_DEFINED XED_IFORMFL_VPMOVZXDQ_LAST_DEFINED XED_IFORMFL_VPMOVZXWD_FIRST_DEFINED XED_IFORMFL_VPMOVZXWD_LAST_DEFINED XED_IFORMFL_VPMOVZXWQ_FIRST_DEFINED XED_IFORMFL_VPMOVZXWQ_LAST_DEFINED XED_IFORMFL_VPMULDQ_FIRST_DEFINED XED_IFORMFL_VPMULDQ_LAST_DEFINED XED_IFORMFL_VPMULHRSW_FIRST_DEFINED XED_IFORMFL_VPMULHRSW_LAST_DEFINED XED_IFORMFL_VPMULHUW_FIRST_DEFINED XED_IFORMFL_VPMULHUW_LAST_DEFINED XED_IFORMFL_VPMULHW_FIRST_DEFINED XED_IFORMFL_VPMULHW_LAST_DEFINED XED_IFORMFL_VPMULLD_FIRST_DEFINED XED_IFORMFL_VPMULLD_LAST_DEFINED XED_IFORMFL_VPMULLQ_FIRST_DEFINED XED_IFORMFL_VPMULLQ_LAST_DEFINED XED_IFORMFL_VPMULLW_FIRST_DEFINED XED_IFORMFL_VPMULLW_LAST_DEFINED XED_IFORMFL_VPMULTISHIFTQB_FIRST_DEFINED XED_IFORMFL_VPMULTISHIFTQB_LAST_DEFINED XED_IFORMFL_VPMULUDQ_FIRST_DEFINED XED_IFORMFL_VPMULUDQ_LAST_DEFINED XED_IFORMFL_VPOPCNTB_FIRST_DEFINED XED_IFORMFL_VPOPCNTB_LAST_DEFINED XED_IFORMFL_VPOPCNTD_FIRST_DEFINED XED_IFORMFL_VPOPCNTD_LAST_DEFINED XED_IFORMFL_VPOPCNTQ_FIRST_DEFINED XED_IFORMFL_VPOPCNTQ_LAST_DEFINED XED_IFORMFL_VPOPCNTW_FIRST_DEFINED XED_IFORMFL_VPOPCNTW_LAST_DEFINED XED_IFORMFL_VPORD_FIRST_DEFINED XED_IFORMFL_VPORD_LAST_DEFINED XED_IFORMFL_VPORQ_FIRST_DEFINED XED_IFORMFL_VPORQ_LAST_DEFINED XED_IFORMFL_VPOR_FIRST_DEFINED XED_IFORMFL_VPOR_LAST_DEFINED XED_IFORMFL_VPPERM_FIRST_DEFINED XED_IFORMFL_VPPERM_LAST_DEFINED XED_IFORMFL_VPROLD_FIRST_DEFINED XED_IFORMFL_VPROLD_LAST_DEFINED XED_IFORMFL_VPROLQ_FIRST_DEFINED XED_IFORMFL_VPROLQ_LAST_DEFINED XED_IFORMFL_VPROLVD_FIRST_DEFINED XED_IFORMFL_VPROLVD_LAST_DEFINED XED_IFORMFL_VPROLVQ_FIRST_DEFINED XED_IFORMFL_VPROLVQ_LAST_DEFINED XED_IFORMFL_VPRORD_FIRST_DEFINED XED_IFORMFL_VPRORD_LAST_DEFINED XED_IFORMFL_VPRORQ_FIRST_DEFINED XED_IFORMFL_VPRORQ_LAST_DEFINED XED_IFORMFL_VPRORVD_FIRST_DEFINED XED_IFORMFL_VPRORVD_LAST_DEFINED XED_IFORMFL_VPRORVQ_FIRST_DEFINED XED_IFORMFL_VPRORVQ_LAST_DEFINED XED_IFORMFL_VPROTB_FIRST_DEFINED XED_IFORMFL_VPROTB_LAST_DEFINED XED_IFORMFL_VPROTD_FIRST_DEFINED XED_IFORMFL_VPROTD_LAST_DEFINED XED_IFORMFL_VPROTQ_FIRST_DEFINED XED_IFORMFL_VPROTQ_LAST_DEFINED XED_IFORMFL_VPROTW_FIRST_DEFINED XED_IFORMFL_VPROTW_LAST_DEFINED XED_IFORMFL_VPSADBW_FIRST_DEFINED XED_IFORMFL_VPSADBW_LAST_DEFINED XED_IFORMFL_VPSCATTERDD_FIRST_DEFINED XED_IFORMFL_VPSCATTERDD_LAST_DEFINED XED_IFORMFL_VPSCATTERDQ_FIRST_DEFINED XED_IFORMFL_VPSCATTERDQ_LAST_DEFINED XED_IFORMFL_VPSCATTERQD_FIRST_DEFINED XED_IFORMFL_VPSCATTERQD_LAST_DEFINED XED_IFORMFL_VPSCATTERQQ_FIRST_DEFINED XED_IFORMFL_VPSCATTERQQ_LAST_DEFINED XED_IFORMFL_VPSHAB_FIRST_DEFINED XED_IFORMFL_VPSHAB_LAST_DEFINED XED_IFORMFL_VPSHAD_FIRST_DEFINED XED_IFORMFL_VPSHAD_LAST_DEFINED XED_IFORMFL_VPSHAQ_FIRST_DEFINED XED_IFORMFL_VPSHAQ_LAST_DEFINED XED_IFORMFL_VPSHAW_FIRST_DEFINED XED_IFORMFL_VPSHAW_LAST_DEFINED XED_IFORMFL_VPSHLB_FIRST_DEFINED XED_IFORMFL_VPSHLB_LAST_DEFINED XED_IFORMFL_VPSHLDD_FIRST_DEFINED XED_IFORMFL_VPSHLDD_LAST_DEFINED XED_IFORMFL_VPSHLDQ_FIRST_DEFINED XED_IFORMFL_VPSHLDQ_LAST_DEFINED XED_IFORMFL_VPSHLDVD_FIRST_DEFINED XED_IFORMFL_VPSHLDVD_LAST_DEFINED XED_IFORMFL_VPSHLDVQ_FIRST_DEFINED XED_IFORMFL_VPSHLDVQ_LAST_DEFINED XED_IFORMFL_VPSHLDVW_FIRST_DEFINED XED_IFORMFL_VPSHLDVW_LAST_DEFINED XED_IFORMFL_VPSHLDW_FIRST_DEFINED XED_IFORMFL_VPSHLDW_LAST_DEFINED XED_IFORMFL_VPSHLD_FIRST_DEFINED XED_IFORMFL_VPSHLD_LAST_DEFINED XED_IFORMFL_VPSHLQ_FIRST_DEFINED XED_IFORMFL_VPSHLQ_LAST_DEFINED XED_IFORMFL_VPSHLW_FIRST_DEFINED XED_IFORMFL_VPSHLW_LAST_DEFINED XED_IFORMFL_VPSHRDD_FIRST_DEFINED XED_IFORMFL_VPSHRDD_LAST_DEFINED XED_IFORMFL_VPSHRDQ_FIRST_DEFINED XED_IFORMFL_VPSHRDQ_LAST_DEFINED XED_IFORMFL_VPSHRDVD_FIRST_DEFINED XED_IFORMFL_VPSHRDVD_LAST_DEFINED XED_IFORMFL_VPSHRDVQ_FIRST_DEFINED XED_IFORMFL_VPSHRDVQ_LAST_DEFINED XED_IFORMFL_VPSHRDVW_FIRST_DEFINED XED_IFORMFL_VPSHRDVW_LAST_DEFINED XED_IFORMFL_VPSHRDW_FIRST_DEFINED XED_IFORMFL_VPSHRDW_LAST_DEFINED XED_IFORMFL_VPSHUFBITQMB_FIRST_DEFINED XED_IFORMFL_VPSHUFBITQMB_LAST_DEFINED XED_IFORMFL_VPSHUFB_FIRST_DEFINED XED_IFORMFL_VPSHUFB_LAST_DEFINED XED_IFORMFL_VPSHUFD_FIRST_DEFINED XED_IFORMFL_VPSHUFD_LAST_DEFINED XED_IFORMFL_VPSHUFHW_FIRST_DEFINED XED_IFORMFL_VPSHUFHW_LAST_DEFINED XED_IFORMFL_VPSHUFLW_FIRST_DEFINED XED_IFORMFL_VPSHUFLW_LAST_DEFINED XED_IFORMFL_VPSIGNB_FIRST_DEFINED XED_IFORMFL_VPSIGNB_LAST_DEFINED XED_IFORMFL_VPSIGND_FIRST_DEFINED XED_IFORMFL_VPSIGND_LAST_DEFINED XED_IFORMFL_VPSIGNW_FIRST_DEFINED XED_IFORMFL_VPSIGNW_LAST_DEFINED XED_IFORMFL_VPSLLDQ_FIRST_DEFINED XED_IFORMFL_VPSLLDQ_LAST_DEFINED XED_IFORMFL_VPSLLD_FIRST_DEFINED XED_IFORMFL_VPSLLD_LAST_DEFINED XED_IFORMFL_VPSLLQ_FIRST_DEFINED XED_IFORMFL_VPSLLQ_LAST_DEFINED XED_IFORMFL_VPSLLVD_FIRST_DEFINED XED_IFORMFL_VPSLLVD_LAST_DEFINED XED_IFORMFL_VPSLLVQ_FIRST_DEFINED XED_IFORMFL_VPSLLVQ_LAST_DEFINED XED_IFORMFL_VPSLLVW_FIRST_DEFINED XED_IFORMFL_VPSLLVW_LAST_DEFINED XED_IFORMFL_VPSLLW_FIRST_DEFINED XED_IFORMFL_VPSLLW_LAST_DEFINED XED_IFORMFL_VPSRAD_FIRST_DEFINED XED_IFORMFL_VPSRAD_LAST_DEFINED XED_IFORMFL_VPSRAQ_FIRST_DEFINED XED_IFORMFL_VPSRAQ_LAST_DEFINED XED_IFORMFL_VPSRAVD_FIRST_DEFINED XED_IFORMFL_VPSRAVD_LAST_DEFINED XED_IFORMFL_VPSRAVQ_FIRST_DEFINED XED_IFORMFL_VPSRAVQ_LAST_DEFINED XED_IFORMFL_VPSRAVW_FIRST_DEFINED XED_IFORMFL_VPSRAVW_LAST_DEFINED XED_IFORMFL_VPSRAW_FIRST_DEFINED XED_IFORMFL_VPSRAW_LAST_DEFINED XED_IFORMFL_VPSRLDQ_FIRST_DEFINED XED_IFORMFL_VPSRLDQ_LAST_DEFINED XED_IFORMFL_VPSRLD_FIRST_DEFINED XED_IFORMFL_VPSRLD_LAST_DEFINED XED_IFORMFL_VPSRLQ_FIRST_DEFINED XED_IFORMFL_VPSRLQ_LAST_DEFINED XED_IFORMFL_VPSRLVD_FIRST_DEFINED XED_IFORMFL_VPSRLVD_LAST_DEFINED XED_IFORMFL_VPSRLVQ_FIRST_DEFINED XED_IFORMFL_VPSRLVQ_LAST_DEFINED XED_IFORMFL_VPSRLVW_FIRST_DEFINED XED_IFORMFL_VPSRLVW_LAST_DEFINED XED_IFORMFL_VPSRLW_FIRST_DEFINED XED_IFORMFL_VPSRLW_LAST_DEFINED XED_IFORMFL_VPSUBB_FIRST_DEFINED XED_IFORMFL_VPSUBB_LAST_DEFINED XED_IFORMFL_VPSUBD_FIRST_DEFINED XED_IFORMFL_VPSUBD_LAST_DEFINED XED_IFORMFL_VPSUBQ_FIRST_DEFINED XED_IFORMFL_VPSUBQ_LAST_DEFINED XED_IFORMFL_VPSUBSB_FIRST_DEFINED XED_IFORMFL_VPSUBSB_LAST_DEFINED XED_IFORMFL_VPSUBSW_FIRST_DEFINED XED_IFORMFL_VPSUBSW_LAST_DEFINED XED_IFORMFL_VPSUBUSB_FIRST_DEFINED XED_IFORMFL_VPSUBUSB_LAST_DEFINED XED_IFORMFL_VPSUBUSW_FIRST_DEFINED XED_IFORMFL_VPSUBUSW_LAST_DEFINED XED_IFORMFL_VPSUBW_FIRST_DEFINED XED_IFORMFL_VPSUBW_LAST_DEFINED XED_IFORMFL_VPTERNLOGD_FIRST_DEFINED XED_IFORMFL_VPTERNLOGD_LAST_DEFINED XED_IFORMFL_VPTERNLOGQ_FIRST_DEFINED XED_IFORMFL_VPTERNLOGQ_LAST_DEFINED XED_IFORMFL_VPTESTMB_FIRST_DEFINED XED_IFORMFL_VPTESTMB_LAST_DEFINED XED_IFORMFL_VPTESTMD_FIRST_DEFINED XED_IFORMFL_VPTESTMD_LAST_DEFINED XED_IFORMFL_VPTESTMQ_FIRST_DEFINED XED_IFORMFL_VPTESTMQ_LAST_DEFINED XED_IFORMFL_VPTESTMW_FIRST_DEFINED XED_IFORMFL_VPTESTMW_LAST_DEFINED XED_IFORMFL_VPTESTNMB_FIRST_DEFINED XED_IFORMFL_VPTESTNMB_LAST_DEFINED XED_IFORMFL_VPTESTNMD_FIRST_DEFINED XED_IFORMFL_VPTESTNMD_LAST_DEFINED XED_IFORMFL_VPTESTNMQ_FIRST_DEFINED XED_IFORMFL_VPTESTNMQ_LAST_DEFINED XED_IFORMFL_VPTESTNMW_FIRST_DEFINED XED_IFORMFL_VPTESTNMW_LAST_DEFINED XED_IFORMFL_VPTEST_FIRST_DEFINED XED_IFORMFL_VPTEST_LAST_DEFINED XED_IFORMFL_VPUNPCKHBW_FIRST_DEFINED XED_IFORMFL_VPUNPCKHBW_LAST_DEFINED XED_IFORMFL_VPUNPCKHDQ_FIRST_DEFINED XED_IFORMFL_VPUNPCKHDQ_LAST_DEFINED XED_IFORMFL_VPUNPCKHQDQ_FIRST_DEFINED XED_IFORMFL_VPUNPCKHQDQ_LAST_DEFINED XED_IFORMFL_VPUNPCKHWD_FIRST_DEFINED XED_IFORMFL_VPUNPCKHWD_LAST_DEFINED XED_IFORMFL_VPUNPCKLBW_FIRST_DEFINED XED_IFORMFL_VPUNPCKLBW_LAST_DEFINED XED_IFORMFL_VPUNPCKLDQ_FIRST_DEFINED XED_IFORMFL_VPUNPCKLDQ_LAST_DEFINED XED_IFORMFL_VPUNPCKLQDQ_FIRST_DEFINED XED_IFORMFL_VPUNPCKLQDQ_LAST_DEFINED XED_IFORMFL_VPUNPCKLWD_FIRST_DEFINED XED_IFORMFL_VPUNPCKLWD_LAST_DEFINED XED_IFORMFL_VPXORD_FIRST_DEFINED XED_IFORMFL_VPXORD_LAST_DEFINED XED_IFORMFL_VPXORQ_FIRST_DEFINED XED_IFORMFL_VPXORQ_LAST_DEFINED XED_IFORMFL_VPXOR_FIRST_DEFINED XED_IFORMFL_VPXOR_LAST_DEFINED XED_IFORMFL_VRANGEPD_FIRST_DEFINED XED_IFORMFL_VRANGEPD_LAST_DEFINED XED_IFORMFL_VRANGEPS_FIRST_DEFINED XED_IFORMFL_VRANGEPS_LAST_DEFINED XED_IFORMFL_VRANGESD_FIRST_DEFINED XED_IFORMFL_VRANGESD_LAST_DEFINED XED_IFORMFL_VRANGESS_FIRST_DEFINED XED_IFORMFL_VRANGESS_LAST_DEFINED XED_IFORMFL_VRCP14PD_FIRST_DEFINED XED_IFORMFL_VRCP14PD_LAST_DEFINED XED_IFORMFL_VRCP14PS_FIRST_DEFINED XED_IFORMFL_VRCP14PS_LAST_DEFINED XED_IFORMFL_VRCP14SD_FIRST_DEFINED XED_IFORMFL_VRCP14SD_LAST_DEFINED XED_IFORMFL_VRCP14SS_FIRST_DEFINED XED_IFORMFL_VRCP14SS_LAST_DEFINED XED_IFORMFL_VRCP28PD_FIRST_DEFINED XED_IFORMFL_VRCP28PD_LAST_DEFINED XED_IFORMFL_VRCP28PS_FIRST_DEFINED XED_IFORMFL_VRCP28PS_LAST_DEFINED XED_IFORMFL_VRCP28SD_FIRST_DEFINED XED_IFORMFL_VRCP28SD_LAST_DEFINED XED_IFORMFL_VRCP28SS_FIRST_DEFINED XED_IFORMFL_VRCP28SS_LAST_DEFINED XED_IFORMFL_VRCPPH_FIRST_DEFINED XED_IFORMFL_VRCPPH_LAST_DEFINED XED_IFORMFL_VRCPPS_FIRST_DEFINED XED_IFORMFL_VRCPPS_LAST_DEFINED XED_IFORMFL_VRCPSH_FIRST_DEFINED XED_IFORMFL_VRCPSH_LAST_DEFINED XED_IFORMFL_VRCPSS_FIRST_DEFINED XED_IFORMFL_VRCPSS_LAST_DEFINED XED_IFORMFL_VREDUCEPD_FIRST_DEFINED XED_IFORMFL_VREDUCEPD_LAST_DEFINED XED_IFORMFL_VREDUCEPH_FIRST_DEFINED XED_IFORMFL_VREDUCEPH_LAST_DEFINED XED_IFORMFL_VREDUCEPS_FIRST_DEFINED XED_IFORMFL_VREDUCEPS_LAST_DEFINED XED_IFORMFL_VREDUCESD_FIRST_DEFINED XED_IFORMFL_VREDUCESD_LAST_DEFINED XED_IFORMFL_VREDUCESH_FIRST_DEFINED XED_IFORMFL_VREDUCESH_LAST_DEFINED XED_IFORMFL_VREDUCESS_FIRST_DEFINED XED_IFORMFL_VREDUCESS_LAST_DEFINED XED_IFORMFL_VRNDSCALEPD_FIRST_DEFINED XED_IFORMFL_VRNDSCALEPD_LAST_DEFINED XED_IFORMFL_VRNDSCALEPH_FIRST_DEFINED XED_IFORMFL_VRNDSCALEPH_LAST_DEFINED XED_IFORMFL_VRNDSCALEPS_FIRST_DEFINED XED_IFORMFL_VRNDSCALEPS_LAST_DEFINED XED_IFORMFL_VRNDSCALESD_FIRST_DEFINED XED_IFORMFL_VRNDSCALESD_LAST_DEFINED XED_IFORMFL_VRNDSCALESH_FIRST_DEFINED XED_IFORMFL_VRNDSCALESH_LAST_DEFINED XED_IFORMFL_VRNDSCALESS_FIRST_DEFINED XED_IFORMFL_VRNDSCALESS_LAST_DEFINED XED_IFORMFL_VROUNDPD_FIRST_DEFINED XED_IFORMFL_VROUNDPD_LAST_DEFINED XED_IFORMFL_VROUNDPS_FIRST_DEFINED XED_IFORMFL_VROUNDPS_LAST_DEFINED XED_IFORMFL_VROUNDSD_FIRST_DEFINED XED_IFORMFL_VROUNDSD_LAST_DEFINED XED_IFORMFL_VROUNDSS_FIRST_DEFINED XED_IFORMFL_VROUNDSS_LAST_DEFINED XED_IFORMFL_VRSQRT14PD_FIRST_DEFINED XED_IFORMFL_VRSQRT14PD_LAST_DEFINED XED_IFORMFL_VRSQRT14PS_FIRST_DEFINED XED_IFORMFL_VRSQRT14PS_LAST_DEFINED XED_IFORMFL_VRSQRT14SD_FIRST_DEFINED XED_IFORMFL_VRSQRT14SD_LAST_DEFINED XED_IFORMFL_VRSQRT14SS_FIRST_DEFINED XED_IFORMFL_VRSQRT14SS_LAST_DEFINED XED_IFORMFL_VRSQRT28PD_FIRST_DEFINED XED_IFORMFL_VRSQRT28PD_LAST_DEFINED XED_IFORMFL_VRSQRT28PS_FIRST_DEFINED XED_IFORMFL_VRSQRT28PS_LAST_DEFINED XED_IFORMFL_VRSQRT28SD_FIRST_DEFINED XED_IFORMFL_VRSQRT28SD_LAST_DEFINED XED_IFORMFL_VRSQRT28SS_FIRST_DEFINED XED_IFORMFL_VRSQRT28SS_LAST_DEFINED XED_IFORMFL_VRSQRTPH_FIRST_DEFINED XED_IFORMFL_VRSQRTPH_LAST_DEFINED XED_IFORMFL_VRSQRTPS_FIRST_DEFINED XED_IFORMFL_VRSQRTPS_LAST_DEFINED XED_IFORMFL_VRSQRTSH_FIRST_DEFINED XED_IFORMFL_VRSQRTSH_LAST_DEFINED XED_IFORMFL_VRSQRTSS_FIRST_DEFINED XED_IFORMFL_VRSQRTSS_LAST_DEFINED XED_IFORMFL_VSCALEFPD_FIRST_DEFINED XED_IFORMFL_VSCALEFPD_LAST_DEFINED XED_IFORMFL_VSCALEFPH_FIRST_DEFINED XED_IFORMFL_VSCALEFPH_LAST_DEFINED XED_IFORMFL_VSCALEFPS_FIRST_DEFINED XED_IFORMFL_VSCALEFPS_LAST_DEFINED XED_IFORMFL_VSCALEFSD_FIRST_DEFINED XED_IFORMFL_VSCALEFSD_LAST_DEFINED XED_IFORMFL_VSCALEFSH_FIRST_DEFINED XED_IFORMFL_VSCALEFSH_LAST_DEFINED XED_IFORMFL_VSCALEFSS_FIRST_DEFINED XED_IFORMFL_VSCALEFSS_LAST_DEFINED XED_IFORMFL_VSCATTERDPD_FIRST_DEFINED XED_IFORMFL_VSCATTERDPD_LAST_DEFINED XED_IFORMFL_VSCATTERDPS_FIRST_DEFINED XED_IFORMFL_VSCATTERDPS_LAST_DEFINED XED_IFORMFL_VSCATTERPF0DPD_FIRST_DEFINED XED_IFORMFL_VSCATTERPF0DPD_LAST_DEFINED XED_IFORMFL_VSCATTERPF0DPS_FIRST_DEFINED XED_IFORMFL_VSCATTERPF0DPS_LAST_DEFINED XED_IFORMFL_VSCATTERPF0QPD_FIRST_DEFINED XED_IFORMFL_VSCATTERPF0QPD_LAST_DEFINED XED_IFORMFL_VSCATTERPF0QPS_FIRST_DEFINED XED_IFORMFL_VSCATTERPF0QPS_LAST_DEFINED XED_IFORMFL_VSCATTERPF1DPD_FIRST_DEFINED XED_IFORMFL_VSCATTERPF1DPD_LAST_DEFINED XED_IFORMFL_VSCATTERPF1DPS_FIRST_DEFINED XED_IFORMFL_VSCATTERPF1DPS_LAST_DEFINED XED_IFORMFL_VSCATTERPF1QPD_FIRST_DEFINED XED_IFORMFL_VSCATTERPF1QPD_LAST_DEFINED XED_IFORMFL_VSCATTERPF1QPS_FIRST_DEFINED XED_IFORMFL_VSCATTERPF1QPS_LAST_DEFINED XED_IFORMFL_VSCATTERQPD_FIRST_DEFINED XED_IFORMFL_VSCATTERQPD_LAST_DEFINED XED_IFORMFL_VSCATTERQPS_FIRST_DEFINED XED_IFORMFL_VSCATTERQPS_LAST_DEFINED XED_IFORMFL_VSHA512MSG1_FIRST_DEFINED XED_IFORMFL_VSHA512MSG1_LAST_DEFINED XED_IFORMFL_VSHA512MSG2_FIRST_DEFINED XED_IFORMFL_VSHA512MSG2_LAST_DEFINED XED_IFORMFL_VSHA512RNDS2_FIRST_DEFINED XED_IFORMFL_VSHA512RNDS2_LAST_DEFINED XED_IFORMFL_VSHUFF32X4_FIRST_DEFINED XED_IFORMFL_VSHUFF32X4_LAST_DEFINED XED_IFORMFL_VSHUFF64X2_FIRST_DEFINED XED_IFORMFL_VSHUFF64X2_LAST_DEFINED XED_IFORMFL_VSHUFI32X4_FIRST_DEFINED XED_IFORMFL_VSHUFI32X4_LAST_DEFINED XED_IFORMFL_VSHUFI64X2_FIRST_DEFINED XED_IFORMFL_VSHUFI64X2_LAST_DEFINED XED_IFORMFL_VSHUFPD_FIRST_DEFINED XED_IFORMFL_VSHUFPD_LAST_DEFINED XED_IFORMFL_VSHUFPS_FIRST_DEFINED XED_IFORMFL_VSHUFPS_LAST_DEFINED XED_IFORMFL_VSM3MSG1_FIRST_DEFINED XED_IFORMFL_VSM3MSG1_LAST_DEFINED XED_IFORMFL_VSM3MSG2_FIRST_DEFINED XED_IFORMFL_VSM3MSG2_LAST_DEFINED XED_IFORMFL_VSM3RNDS2_FIRST_DEFINED XED_IFORMFL_VSM3RNDS2_LAST_DEFINED XED_IFORMFL_VSM4KEY4_FIRST_DEFINED XED_IFORMFL_VSM4KEY4_LAST_DEFINED XED_IFORMFL_VSM4RNDS4_FIRST_DEFINED XED_IFORMFL_VSM4RNDS4_LAST_DEFINED XED_IFORMFL_VSQRTPD_FIRST_DEFINED XED_IFORMFL_VSQRTPD_LAST_DEFINED XED_IFORMFL_VSQRTPH_FIRST_DEFINED XED_IFORMFL_VSQRTPH_LAST_DEFINED XED_IFORMFL_VSQRTPS_FIRST_DEFINED XED_IFORMFL_VSQRTPS_LAST_DEFINED XED_IFORMFL_VSQRTSD_FIRST_DEFINED XED_IFORMFL_VSQRTSD_LAST_DEFINED XED_IFORMFL_VSQRTSH_FIRST_DEFINED XED_IFORMFL_VSQRTSH_LAST_DEFINED XED_IFORMFL_VSQRTSS_FIRST_DEFINED XED_IFORMFL_VSQRTSS_LAST_DEFINED XED_IFORMFL_VSTMXCSR_FIRST_DEFINED XED_IFORMFL_VSTMXCSR_LAST_DEFINED XED_IFORMFL_VSUBPD_FIRST_DEFINED XED_IFORMFL_VSUBPD_LAST_DEFINED XED_IFORMFL_VSUBPH_FIRST_DEFINED XED_IFORMFL_VSUBPH_LAST_DEFINED XED_IFORMFL_VSUBPS_FIRST_DEFINED XED_IFORMFL_VSUBPS_LAST_DEFINED XED_IFORMFL_VSUBSD_FIRST_DEFINED XED_IFORMFL_VSUBSD_LAST_DEFINED XED_IFORMFL_VSUBSH_FIRST_DEFINED XED_IFORMFL_VSUBSH_LAST_DEFINED XED_IFORMFL_VSUBSS_FIRST_DEFINED XED_IFORMFL_VSUBSS_LAST_DEFINED XED_IFORMFL_VTESTPD_FIRST_DEFINED XED_IFORMFL_VTESTPD_LAST_DEFINED XED_IFORMFL_VTESTPS_FIRST_DEFINED XED_IFORMFL_VTESTPS_LAST_DEFINED XED_IFORMFL_VUCOMISD_FIRST_DEFINED XED_IFORMFL_VUCOMISD_LAST_DEFINED XED_IFORMFL_VUCOMISH_FIRST_DEFINED XED_IFORMFL_VUCOMISH_LAST_DEFINED XED_IFORMFL_VUCOMISS_FIRST_DEFINED XED_IFORMFL_VUCOMISS_LAST_DEFINED XED_IFORMFL_VUNPCKHPD_FIRST_DEFINED XED_IFORMFL_VUNPCKHPD_LAST_DEFINED XED_IFORMFL_VUNPCKHPS_FIRST_DEFINED XED_IFORMFL_VUNPCKHPS_LAST_DEFINED XED_IFORMFL_VUNPCKLPD_FIRST_DEFINED XED_IFORMFL_VUNPCKLPD_LAST_DEFINED XED_IFORMFL_VUNPCKLPS_FIRST_DEFINED XED_IFORMFL_VUNPCKLPS_LAST_DEFINED XED_IFORMFL_VXORPD_FIRST_DEFINED XED_IFORMFL_VXORPD_LAST_DEFINED XED_IFORMFL_VXORPS_FIRST_DEFINED XED_IFORMFL_VXORPS_LAST_DEFINED XED_IFORMFL_VZEROALL_FIRST_DEFINED XED_IFORMFL_VZEROALL_LAST_DEFINED XED_IFORMFL_VZEROUPPER_FIRST_DEFINED XED_IFORMFL_VZEROUPPER_LAST_DEFINED XED_IFORMFL_WBINVD_FIRST_DEFINED XED_IFORMFL_WBINVD_LAST_DEFINED XED_IFORMFL_WBNOINVD_FIRST_DEFINED XED_IFORMFL_WBNOINVD_LAST_DEFINED XED_IFORMFL_WRFSBASE_FIRST_DEFINED XED_IFORMFL_WRFSBASE_LAST_DEFINED XED_IFORMFL_WRGSBASE_FIRST_DEFINED XED_IFORMFL_WRGSBASE_LAST_DEFINED XED_IFORMFL_WRMSRLIST_FIRST_DEFINED XED_IFORMFL_WRMSRLIST_LAST_DEFINED XED_IFORMFL_WRMSRNS_FIRST_DEFINED XED_IFORMFL_WRMSRNS_LAST_DEFINED XED_IFORMFL_WRMSR_FIRST_DEFINED XED_IFORMFL_WRMSR_LAST_DEFINED XED_IFORMFL_WRPKRU_FIRST_DEFINED XED_IFORMFL_WRPKRU_LAST_DEFINED XED_IFORMFL_WRSSD_FIRST_DEFINED XED_IFORMFL_WRSSD_LAST_DEFINED XED_IFORMFL_WRSSQ_FIRST_DEFINED XED_IFORMFL_WRSSQ_LAST_DEFINED XED_IFORMFL_WRUSSD_FIRST_DEFINED XED_IFORMFL_WRUSSD_LAST_DEFINED XED_IFORMFL_WRUSSQ_FIRST_DEFINED XED_IFORMFL_WRUSSQ_LAST_DEFINED XED_IFORMFL_XABORT_FIRST_DEFINED XED_IFORMFL_XABORT_LAST_DEFINED XED_IFORMFL_XADD_FIRST_DEFINED XED_IFORMFL_XADD_LAST_DEFINED XED_IFORMFL_XADD_LOCK_FIRST_DEFINED XED_IFORMFL_XADD_LOCK_LAST_DEFINED XED_IFORMFL_XBEGIN_FIRST_DEFINED XED_IFORMFL_XBEGIN_LAST_DEFINED XED_IFORMFL_XCHG_FIRST_DEFINED XED_IFORMFL_XCHG_LAST_DEFINED XED_IFORMFL_XEND_FIRST_DEFINED XED_IFORMFL_XEND_LAST_DEFINED XED_IFORMFL_XGETBV_FIRST_DEFINED XED_IFORMFL_XGETBV_LAST_DEFINED XED_IFORMFL_XLAT_FIRST_DEFINED XED_IFORMFL_XLAT_LAST_DEFINED XED_IFORMFL_XORPD_FIRST_DEFINED XED_IFORMFL_XORPD_LAST_DEFINED XED_IFORMFL_XORPS_FIRST_DEFINED XED_IFORMFL_XORPS_LAST_DEFINED XED_IFORMFL_XOR_FIRST_DEFINED XED_IFORMFL_XOR_LAST_DEFINED XED_IFORMFL_XOR_LOCK_FIRST_DEFINED XED_IFORMFL_XOR_LOCK_LAST_DEFINED XED_IFORMFL_XRESLDTRK_FIRST_DEFINED XED_IFORMFL_XRESLDTRK_LAST_DEFINED XED_IFORMFL_XRSTOR64_FIRST_DEFINED XED_IFORMFL_XRSTOR64_LAST_DEFINED XED_IFORMFL_XRSTORS64_FIRST_DEFINED XED_IFORMFL_XRSTORS64_LAST_DEFINED XED_IFORMFL_XRSTORS_FIRST_DEFINED XED_IFORMFL_XRSTORS_LAST_DEFINED XED_IFORMFL_XRSTOR_FIRST_DEFINED XED_IFORMFL_XRSTOR_LAST_DEFINED XED_IFORMFL_XSAVE64_FIRST_DEFINED XED_IFORMFL_XSAVE64_LAST_DEFINED XED_IFORMFL_XSAVEC64_FIRST_DEFINED XED_IFORMFL_XSAVEC64_LAST_DEFINED XED_IFORMFL_XSAVEC_FIRST_DEFINED XED_IFORMFL_XSAVEC_LAST_DEFINED XED_IFORMFL_XSAVEOPT64_FIRST_DEFINED XED_IFORMFL_XSAVEOPT64_LAST_DEFINED XED_IFORMFL_XSAVEOPT_FIRST_DEFINED XED_IFORMFL_XSAVEOPT_LAST_DEFINED XED_IFORMFL_XSAVES64_FIRST_DEFINED XED_IFORMFL_XSAVES64_LAST_DEFINED XED_IFORMFL_XSAVES_FIRST_DEFINED XED_IFORMFL_XSAVES_LAST_DEFINED XED_IFORMFL_XSAVE_FIRST_DEFINED XED_IFORMFL_XSAVE_LAST_DEFINED XED_IFORMFL_XSETBV_FIRST_DEFINED XED_IFORMFL_XSETBV_LAST_DEFINED XED_IFORMFL_XSTORE_FIRST_DEFINED XED_IFORMFL_XSTORE_LAST_DEFINED XED_IFORMFL_XSUSLDTRK_FIRST_DEFINED XED_IFORMFL_XSUSLDTRK_LAST_DEFINED XED_IFORMFL_XTEST_FIRST_DEFINED XED_IFORMFL_XTEST_LAST_DEFINED XED_IFORM_AAA_DEFINED XED_IFORM_AADD_MEM32_GPR32_DEFINED XED_IFORM_AADD_MEM64_GPR64_DEFINED XED_IFORM_AAD_IMMb_DEFINED XED_IFORM_AAM_IMMb_DEFINED XED_IFORM_AAND_MEM32_GPR32_DEFINED XED_IFORM_AAND_MEM64_GPR64_DEFINED XED_IFORM_AAS_DEFINED XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED XED_IFORM_ADCX_GPR32d_MEMd_DEFINED XED_IFORM_ADCX_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_ADCX_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_ADCX_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_ADCX_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED XED_IFORM_ADCX_GPR64q_MEMq_DEFINED XED_IFORM_ADC_AL_IMMb_DEFINED XED_IFORM_ADC_GPR8_GPR8_10_DEFINED XED_IFORM_ADC_GPR8_GPR8_12_DEFINED XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED XED_IFORM_ADC_GPR8_MEMb_DEFINED XED_IFORM_ADC_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_ADC_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ADC_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_ADC_GPRv_GPRv_11_DEFINED XED_IFORM_ADC_GPRv_GPRv_13_DEFINED XED_IFORM_ADC_GPRv_GPRv_APX_DEFINED XED_IFORM_ADC_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_ADC_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_ADC_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_ADC_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_ADC_GPRv_IMM8_APX_DEFINED XED_IFORM_ADC_GPRv_IMMb_DEFINED XED_IFORM_ADC_GPRv_IMMz_APX_DEFINED XED_IFORM_ADC_GPRv_IMMz_DEFINED XED_IFORM_ADC_GPRv_MEMv_APX_DEFINED XED_IFORM_ADC_GPRv_MEMv_DEFINED XED_IFORM_ADC_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_ADC_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_ADC_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED XED_IFORM_ADC_MEMb_GPR8_DEFINED XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED XED_IFORM_ADC_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_ADC_MEMi8_IMM8_APX_DEFINED XED_IFORM_ADC_MEMv_GPRv_APX_DEFINED XED_IFORM_ADC_MEMv_GPRv_DEFINED XED_IFORM_ADC_MEMv_IMM8_APX_DEFINED XED_IFORM_ADC_MEMv_IMMb_DEFINED XED_IFORM_ADC_MEMv_IMMz_APX_DEFINED XED_IFORM_ADC_MEMv_IMMz_DEFINED XED_IFORM_ADC_OrAX_IMMz_DEFINED XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED XED_IFORM_ADDPS_XMMps_MEMps_DEFINED XED_IFORM_ADDPS_XMMps_XMMps_DEFINED XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED XED_IFORM_ADDSS_XMMss_MEMss_DEFINED XED_IFORM_ADDSS_XMMss_XMMss_DEFINED XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED XED_IFORM_ADD_AL_IMMb_DEFINED XED_IFORM_ADD_GPR8_GPR8_00_DEFINED XED_IFORM_ADD_GPR8_GPR8_02_DEFINED XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED XED_IFORM_ADD_GPR8_MEMb_DEFINED XED_IFORM_ADD_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_ADD_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ADD_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_ADD_GPRv_GPRv_01_DEFINED XED_IFORM_ADD_GPRv_GPRv_03_DEFINED XED_IFORM_ADD_GPRv_GPRv_APX_DEFINED XED_IFORM_ADD_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_ADD_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_ADD_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_ADD_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_ADD_GPRv_IMM8_APX_DEFINED XED_IFORM_ADD_GPRv_IMMb_DEFINED XED_IFORM_ADD_GPRv_IMMz_APX_DEFINED XED_IFORM_ADD_GPRv_IMMz_DEFINED XED_IFORM_ADD_GPRv_MEMv_APX_DEFINED XED_IFORM_ADD_GPRv_MEMv_DEFINED XED_IFORM_ADD_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_ADD_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_ADD_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED XED_IFORM_ADD_MEMb_GPR8_DEFINED XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED XED_IFORM_ADD_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_ADD_MEMi8_IMM8_APX_DEFINED XED_IFORM_ADD_MEMv_GPRv_APX_DEFINED XED_IFORM_ADD_MEMv_GPRv_DEFINED XED_IFORM_ADD_MEMv_IMM8_APX_DEFINED XED_IFORM_ADD_MEMv_IMMb_DEFINED XED_IFORM_ADD_MEMv_IMMz_APX_DEFINED XED_IFORM_ADD_MEMv_IMMz_DEFINED XED_IFORM_ADD_OrAX_IMMz_DEFINED XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED XED_IFORM_ADOX_GPR32d_MEMd_DEFINED XED_IFORM_ADOX_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_ADOX_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_ADOX_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_ADOX_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED XED_IFORM_ADOX_GPR64q_MEMq_DEFINED XED_IFORM_AESDEC128KL_XMMu8_MEMu8_APX_DEFINED XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED XED_IFORM_AESDEC256KL_XMMu8_MEMu8_APX_DEFINED XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED XED_IFORM_AESDECWIDE128KL_MEMu8_APX_DEFINED XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED XED_IFORM_AESDECWIDE256KL_MEMu8_APX_DEFINED XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED XED_IFORM_AESENC128KL_XMMu8_MEMu8_APX_DEFINED XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED XED_IFORM_AESENC256KL_XMMu8_MEMu8_APX_DEFINED XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED XED_IFORM_AESENCWIDE128KL_MEMu8_APX_DEFINED XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED XED_IFORM_AESENCWIDE256KL_MEMu8_APX_DEFINED XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd_DEFINED XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq_DEFINED XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED XED_IFORM_AND_AL_IMMb_DEFINED XED_IFORM_AND_GPR8_GPR8_20_DEFINED XED_IFORM_AND_GPR8_GPR8_22_DEFINED XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED XED_IFORM_AND_GPR8_MEMb_DEFINED XED_IFORM_AND_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_AND_GPR8i8_IMM8_APX_DEFINED XED_IFORM_AND_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_AND_GPRv_GPRv_21_DEFINED XED_IFORM_AND_GPRv_GPRv_23_DEFINED XED_IFORM_AND_GPRv_GPRv_APX_DEFINED XED_IFORM_AND_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_AND_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_AND_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_AND_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_AND_GPRv_IMM8_APX_DEFINED XED_IFORM_AND_GPRv_IMMb_DEFINED XED_IFORM_AND_GPRv_IMMz_APX_DEFINED XED_IFORM_AND_GPRv_IMMz_DEFINED XED_IFORM_AND_GPRv_MEMv_APX_DEFINED XED_IFORM_AND_GPRv_MEMv_DEFINED XED_IFORM_AND_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_AND_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_AND_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED XED_IFORM_AND_MEMb_GPR8_DEFINED XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED XED_IFORM_AND_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_AND_MEMi8_IMM8_APX_DEFINED XED_IFORM_AND_MEMv_GPRv_APX_DEFINED XED_IFORM_AND_MEMv_GPRv_DEFINED XED_IFORM_AND_MEMv_IMM8_APX_DEFINED XED_IFORM_AND_MEMv_IMMb_DEFINED XED_IFORM_AND_MEMv_IMMz_APX_DEFINED XED_IFORM_AND_MEMv_IMMz_DEFINED XED_IFORM_AND_OrAX_IMMz_DEFINED XED_IFORM_AOR_MEM32_GPR32_DEFINED XED_IFORM_AOR_MEM64_GPR64_DEFINED XED_IFORM_ARPL_GPR16_GPR16_DEFINED XED_IFORM_ARPL_MEMw_GPR16_DEFINED XED_IFORM_AXOR_MEM32_GPR32_DEFINED XED_IFORM_AXOR_MEM64_GPR64_DEFINED XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX_DEFINED XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX_DEFINED XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d_DEFINED XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q_DEFINED XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd_DEFINED XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd_DEFINED XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd_DEFINED XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd_DEFINED XED_IFORM_BLCFILL_VGPR32d_MEMd_DEFINED XED_IFORM_BLCFILL_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLCFILL_VGPRyy_MEMy_DEFINED XED_IFORM_BLCFILL_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLCIC_VGPR32d_MEMd_DEFINED XED_IFORM_BLCIC_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLCIC_VGPRyy_MEMy_DEFINED XED_IFORM_BLCIC_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLCI_VGPR32d_MEMd_DEFINED XED_IFORM_BLCI_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLCI_VGPRyy_MEMy_DEFINED XED_IFORM_BLCI_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLCMSK_VGPR32d_MEMd_DEFINED XED_IFORM_BLCMSK_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLCMSK_VGPRyy_MEMy_DEFINED XED_IFORM_BLCMSK_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLCS_VGPR32d_MEMd_DEFINED XED_IFORM_BLCS_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLCS_VGPRyy_MEMy_DEFINED XED_IFORM_BLCS_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED XED_IFORM_BLSFILL_VGPR32d_MEMd_DEFINED XED_IFORM_BLSFILL_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLSFILL_VGPRyy_MEMy_DEFINED XED_IFORM_BLSFILL_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLSIC_VGPR32d_MEMd_DEFINED XED_IFORM_BLSIC_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLSIC_VGPRyy_MEMy_DEFINED XED_IFORM_BLSIC_VGPRyy_VGPRyy_DEFINED XED_IFORM_BLSI_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_BLSI_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_BLSI_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_BLSI_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_BLSI_VGPR32d_MEMd_DEFINED XED_IFORM_BLSI_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLSI_VGPR64q_MEMq_DEFINED XED_IFORM_BLSI_VGPR64q_VGPR64q_DEFINED XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_BLSMSK_VGPR32d_MEMd_DEFINED XED_IFORM_BLSMSK_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLSMSK_VGPR64q_MEMq_DEFINED XED_IFORM_BLSMSK_VGPR64q_VGPR64q_DEFINED XED_IFORM_BLSR_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_BLSR_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_BLSR_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_BLSR_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_BLSR_VGPR32d_MEMd_DEFINED XED_IFORM_BLSR_VGPR32d_VGPR32d_DEFINED XED_IFORM_BLSR_VGPR64q_MEMq_DEFINED XED_IFORM_BLSR_VGPR64q_VGPR64q_DEFINED XED_IFORM_BNDCL_BND_AGEN_DEFINED XED_IFORM_BNDCL_BND_GPR32_DEFINED XED_IFORM_BNDCL_BND_GPR64_DEFINED XED_IFORM_BNDCN_BND_AGEN_DEFINED XED_IFORM_BNDCN_BND_GPR32_DEFINED XED_IFORM_BNDCN_BND_GPR64_DEFINED XED_IFORM_BNDCU_BND_AGEN_DEFINED XED_IFORM_BNDCU_BND_GPR32_DEFINED XED_IFORM_BNDCU_BND_GPR64_DEFINED XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED XED_IFORM_BNDMK_BND_AGEN_DEFINED XED_IFORM_BNDMOV_BND_BND_DEFINED XED_IFORM_BNDMOV_BND_MEMdq_DEFINED XED_IFORM_BNDMOV_BND_MEMq_DEFINED XED_IFORM_BNDMOV_MEMdq_BND_DEFINED XED_IFORM_BNDMOV_MEMq_BND_DEFINED XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED XED_IFORM_BOUND_GPRv_MEMa16_DEFINED XED_IFORM_BOUND_GPRv_MEMa32_DEFINED XED_IFORM_BSF_GPRv_GPRv_DEFINED XED_IFORM_BSF_GPRv_MEMv_DEFINED XED_IFORM_BSR_GPRv_GPRv_DEFINED XED_IFORM_BSR_GPRv_MEMv_DEFINED XED_IFORM_BSWAP_GPRv_DEFINED XED_IFORM_BTC_GPRv_GPRv_DEFINED XED_IFORM_BTC_GPRv_IMMb_DEFINED XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED XED_IFORM_BTC_MEMv_GPRv_DEFINED XED_IFORM_BTC_MEMv_IMMb_DEFINED XED_IFORM_BTR_GPRv_GPRv_DEFINED XED_IFORM_BTR_GPRv_IMMb_DEFINED XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED XED_IFORM_BTR_MEMv_GPRv_DEFINED XED_IFORM_BTR_MEMv_IMMb_DEFINED XED_IFORM_BTS_GPRv_GPRv_DEFINED XED_IFORM_BTS_GPRv_IMMb_DEFINED XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED XED_IFORM_BTS_MEMv_GPRv_DEFINED XED_IFORM_BTS_MEMv_IMMb_DEFINED XED_IFORM_BT_GPRv_GPRv_DEFINED XED_IFORM_BT_GPRv_IMMb_DEFINED XED_IFORM_BT_MEMv_GPRv_DEFINED XED_IFORM_BT_MEMv_IMMb_DEFINED XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX_DEFINED XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX_DEFINED XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d_DEFINED XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q_DEFINED XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_CALL_FAR_MEMp2_DEFINED XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED XED_IFORM_CALL_NEAR_GPRv_DEFINED XED_IFORM_CALL_NEAR_MEMv_DEFINED XED_IFORM_CALL_NEAR_RELBRd_DEFINED XED_IFORM_CALL_NEAR_RELBRz_DEFINED XED_IFORM_CBW_DEFINED XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX_DEFINED XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX_DEFINED XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CDQE_DEFINED XED_IFORM_CDQ_DEFINED XED_IFORM_CFCMOVBE_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVBE_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVBE_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVB_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVB_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVB_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVLE_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVLE_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVLE_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVL_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVL_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVL_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNB_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNB_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNB_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNL_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNL_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNL_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNO_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNO_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNO_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNP_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNP_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNP_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNS_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNS_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNS_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVO_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVO_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVO_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVP_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVP_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVP_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVS_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVS_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVS_MEMv_GPRv_APX_DEFINED XED_IFORM_CFCMOVZ_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVZ_GPRv_MEMv_APX_DEFINED XED_IFORM_CFCMOVZ_MEMv_GPRv_APX_DEFINED XED_IFORM_CLAC_DEFINED XED_IFORM_CLC_DEFINED XED_IFORM_CLDEMOTE_MEMu8_DEFINED XED_IFORM_CLD_DEFINED XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED XED_IFORM_CLGI_DEFINED XED_IFORM_CLI_DEFINED XED_IFORM_CLRSSBSY_MEMu64_DEFINED XED_IFORM_CLTS_DEFINED XED_IFORM_CLUI_DEFINED XED_IFORM_CLWB_MEMmprefetch_DEFINED XED_IFORM_CLZERO_DEFINED XED_IFORM_CMC_DEFINED XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED XED_IFORM_CMOVB_GPRv_GPRv_DEFINED XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVB_GPRv_MEMv_DEFINED XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED XED_IFORM_CMOVL_GPRv_GPRv_DEFINED XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVL_GPRv_MEMv_DEFINED XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED XED_IFORM_CMOVO_GPRv_GPRv_DEFINED XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVO_GPRv_MEMv_DEFINED XED_IFORM_CMOVP_GPRv_GPRv_DEFINED XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVP_GPRv_MEMv_DEFINED XED_IFORM_CMOVS_GPRv_GPRv_DEFINED XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVS_GPRv_MEMv_DEFINED XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPSB_DEFINED XED_IFORM_CMPSD_DEFINED XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED XED_IFORM_CMPSQ_DEFINED XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED XED_IFORM_CMPSW_DEFINED XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED XED_IFORM_CMPXCHG8B_MEMq_DEFINED XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED XED_IFORM_CMPXCHG16B_MEMdq_DEFINED XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED XED_IFORM_CMP_AL_IMMb_DEFINED XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED XED_IFORM_CMP_GPR8_GPR8_38_DEFINED XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED XED_IFORM_CMP_GPR8_MEMb_DEFINED XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED XED_IFORM_CMP_GPRv_GPRv_39_DEFINED XED_IFORM_CMP_GPRv_IMMb_DEFINED XED_IFORM_CMP_GPRv_IMMz_DEFINED XED_IFORM_CMP_GPRv_MEMv_DEFINED XED_IFORM_CMP_MEMb_GPR8_DEFINED XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED XED_IFORM_CMP_MEMv_GPRv_DEFINED XED_IFORM_CMP_MEMv_IMMb_DEFINED XED_IFORM_CMP_MEMv_IMMz_DEFINED XED_IFORM_CMP_OrAX_IMMz_DEFINED XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED XED_IFORM_COMISS_XMMss_MEMss_DEFINED XED_IFORM_COMISS_XMMss_XMMss_DEFINED XED_IFORM_CPUID_DEFINED XED_IFORM_CQO_DEFINED XED_IFORM_CRC32_GPRy_GPR8i8_APX_DEFINED XED_IFORM_CRC32_GPRy_GPRv_APX_DEFINED XED_IFORM_CRC32_GPRy_MEMi8_APX_DEFINED XED_IFORM_CRC32_GPRy_MEMv_APX_DEFINED XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED XED_IFORM_CRC32_GPRyy_GPRv_DEFINED XED_IFORM_CRC32_GPRyy_MEMb_DEFINED XED_IFORM_CRC32_GPRyy_MEMv_DEFINED XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX_DEFINED XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX_DEFINED XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX_DEFINED XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX_DEFINED XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX_DEFINED XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED XED_IFORM_CWDE_DEFINED XED_IFORM_CWD_DEFINED XED_IFORM_DAA_DEFINED XED_IFORM_DAS_DEFINED XED_IFORM_DEC_GPR8_DEFINED XED_IFORM_DEC_GPR8i8_APX_DEFINED XED_IFORM_DEC_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_DEC_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_DEC_GPRv_48_DEFINED XED_IFORM_DEC_GPRv_APX_DEFINED XED_IFORM_DEC_GPRv_FFr1_DEFINED XED_IFORM_DEC_GPRv_GPRv_APX_DEFINED XED_IFORM_DEC_GPRv_MEMv_APX_DEFINED XED_IFORM_DEC_LOCK_MEMb_DEFINED XED_IFORM_DEC_LOCK_MEMv_DEFINED XED_IFORM_DEC_MEMb_DEFINED XED_IFORM_DEC_MEMi8_APX_DEFINED XED_IFORM_DEC_MEMv_APX_DEFINED XED_IFORM_DEC_MEMv_DEFINED XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED XED_IFORM_DIVPS_XMMps_MEMps_DEFINED XED_IFORM_DIVPS_XMMps_XMMps_DEFINED XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED XED_IFORM_DIVSS_XMMss_MEMss_DEFINED XED_IFORM_DIVSS_XMMss_XMMss_DEFINED XED_IFORM_DIV_GPR8_DEFINED XED_IFORM_DIV_GPR8i8_APX_DEFINED XED_IFORM_DIV_GPRv_APX_DEFINED XED_IFORM_DIV_GPRv_DEFINED XED_IFORM_DIV_MEMb_DEFINED XED_IFORM_DIV_MEMi8_APX_DEFINED XED_IFORM_DIV_MEMv_APX_DEFINED XED_IFORM_DIV_MEMv_DEFINED XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_EMMS_DEFINED XED_IFORM_ENCLS_DEFINED XED_IFORM_ENCLU_DEFINED XED_IFORM_ENCLV_DEFINED XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_APX_DEFINED XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_APX_DEFINED XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED XED_IFORM_ENDBR32_DEFINED XED_IFORM_ENDBR64_DEFINED XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED XED_IFORM_ENQCMDS_GPRav_MEMu32_APX_DEFINED XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED XED_IFORM_ENQCMD_GPRav_MEMu32_APX_DEFINED XED_IFORM_ENTER_IMMw_IMMb_DEFINED XED_IFORM_ERETS_DEFINED XED_IFORM_ERETU_DEFINED XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED XED_IFORM_F2XM1_DEFINED XED_IFORM_FABS_DEFINED XED_IFORM_FADDP_X87_ST0_DEFINED XED_IFORM_FADD_MEMm64real_DEFINED XED_IFORM_FADD_MEMmem32real_DEFINED XED_IFORM_FADD_ST0_X87_DEFINED XED_IFORM_FADD_X87_ST0_DEFINED XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED XED_IFORM_FCHS_DEFINED XED_IFORM_FCMOVBE_ST0_X87_DEFINED XED_IFORM_FCMOVB_ST0_X87_DEFINED XED_IFORM_FCMOVE_ST0_X87_DEFINED XED_IFORM_FCMOVNBE_ST0_X87_DEFINED XED_IFORM_FCMOVNB_ST0_X87_DEFINED XED_IFORM_FCMOVNE_ST0_X87_DEFINED XED_IFORM_FCMOVNU_ST0_X87_DEFINED XED_IFORM_FCMOVU_ST0_X87_DEFINED XED_IFORM_FCOMIP_ST0_X87_DEFINED XED_IFORM_FCOMI_ST0_X87_DEFINED XED_IFORM_FCOMPP_DEFINED XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED XED_IFORM_FCOMP_ST0_X87_DEFINED XED_IFORM_FCOM_ST0_MEMm64real_DEFINED XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED XED_IFORM_FCOM_ST0_X87_DEFINED XED_IFORM_FCOS_DEFINED XED_IFORM_FDECSTP_DEFINED XED_IFORM_FDISI8087_NOP_DEFINED XED_IFORM_FDIVP_X87_ST0_DEFINED XED_IFORM_FDIVRP_X87_ST0_DEFINED XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED XED_IFORM_FDIVR_ST0_X87_DEFINED XED_IFORM_FDIVR_X87_ST0_DEFINED XED_IFORM_FDIV_ST0_MEMm64real_DEFINED XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED XED_IFORM_FDIV_ST0_X87_DEFINED XED_IFORM_FDIV_X87_ST0_DEFINED XED_IFORM_FEMMS_DEFINED XED_IFORM_FENI8087_NOP_DEFINED XED_IFORM_FFREEP_X87_DEFINED XED_IFORM_FFREE_X87_DEFINED XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED XED_IFORM_FILD_ST0_MEMm64int_DEFINED XED_IFORM_FILD_ST0_MEMmem16int_DEFINED XED_IFORM_FILD_ST0_MEMmem32int_DEFINED XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED XED_IFORM_FINCSTP_DEFINED XED_IFORM_FISTP_MEMm64int_ST0_DEFINED XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED XED_IFORM_FIST_MEMmem16int_ST0_DEFINED XED_IFORM_FIST_MEMmem32int_ST0_DEFINED XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED XED_IFORM_FLD1_DEFINED XED_IFORM_FLDCW_MEMmem16_DEFINED XED_IFORM_FLDENV_MEMmem14_DEFINED XED_IFORM_FLDENV_MEMmem28_DEFINED XED_IFORM_FLDL2E_DEFINED XED_IFORM_FLDL2T_DEFINED XED_IFORM_FLDLG2_DEFINED XED_IFORM_FLDLN2_DEFINED XED_IFORM_FLDPI_DEFINED XED_IFORM_FLDZ_DEFINED XED_IFORM_FLD_ST0_MEMm64real_DEFINED XED_IFORM_FLD_ST0_MEMmem32real_DEFINED XED_IFORM_FLD_ST0_MEMmem80real_DEFINED XED_IFORM_FLD_ST0_X87_DEFINED XED_IFORM_FMULP_X87_ST0_DEFINED XED_IFORM_FMUL_ST0_MEMm64real_DEFINED XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED XED_IFORM_FMUL_ST0_X87_DEFINED XED_IFORM_FMUL_X87_ST0_DEFINED XED_IFORM_FNCLEX_DEFINED XED_IFORM_FNINIT_DEFINED XED_IFORM_FNOP_DEFINED XED_IFORM_FNSAVE_MEMmem94_DEFINED XED_IFORM_FNSAVE_MEMmem108_DEFINED XED_IFORM_FNSTCW_MEMmem16_DEFINED XED_IFORM_FNSTENV_MEMmem14_DEFINED XED_IFORM_FNSTENV_MEMmem28_DEFINED XED_IFORM_FNSTSW_AX_DEFINED XED_IFORM_FNSTSW_MEMmem16_DEFINED XED_IFORM_FPATAN_DEFINED XED_IFORM_FPREM1_DEFINED XED_IFORM_FPREM_DEFINED XED_IFORM_FPTAN_DEFINED XED_IFORM_FRNDINT_DEFINED XED_IFORM_FRSTOR_MEMmem94_DEFINED XED_IFORM_FRSTOR_MEMmem108_DEFINED XED_IFORM_FSCALE_DEFINED XED_IFORM_FSETPM287_NOP_DEFINED XED_IFORM_FSINCOS_DEFINED XED_IFORM_FSIN_DEFINED XED_IFORM_FSQRT_DEFINED XED_IFORM_FSTPNCE_X87_ST0_DEFINED XED_IFORM_FSTP_MEMm64real_ST0_DEFINED XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED XED_IFORM_FSTP_X87_ST0_DEFINED XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED XED_IFORM_FST_MEMm64real_ST0_DEFINED XED_IFORM_FST_MEMmem32real_ST0_DEFINED XED_IFORM_FST_X87_ST0_DEFINED XED_IFORM_FSUBP_X87_ST0_DEFINED XED_IFORM_FSUBRP_X87_ST0_DEFINED XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED XED_IFORM_FSUBR_ST0_X87_DEFINED XED_IFORM_FSUBR_X87_ST0_DEFINED XED_IFORM_FSUB_ST0_MEMm64real_DEFINED XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED XED_IFORM_FSUB_ST0_X87_DEFINED XED_IFORM_FSUB_X87_ST0_DEFINED XED_IFORM_FTST_DEFINED XED_IFORM_FUCOMIP_ST0_X87_DEFINED XED_IFORM_FUCOMI_ST0_X87_DEFINED XED_IFORM_FUCOMPP_DEFINED XED_IFORM_FUCOMP_ST0_X87_DEFINED XED_IFORM_FUCOM_ST0_X87_DEFINED XED_IFORM_FWAIT_DEFINED XED_IFORM_FXAM_DEFINED XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED XED_IFORM_FXCH_ST0_X87_DEFINED XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED XED_IFORM_FXTRACT_DEFINED XED_IFORM_FYL2XP1_DEFINED XED_IFORM_FYL2X_DEFINED XED_IFORM_GETSEC_DEFINED XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED XED_IFORM_HADDPS_XMMps_MEMps_DEFINED XED_IFORM_HADDPS_XMMps_XMMps_DEFINED XED_IFORM_HLT_DEFINED XED_IFORM_HRESET_IMM8_DEFINED XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED XED_IFORM_IDIV_GPR8_DEFINED XED_IFORM_IDIV_GPR8i8_APX_DEFINED XED_IFORM_IDIV_GPRv_APX_DEFINED XED_IFORM_IDIV_GPRv_DEFINED XED_IFORM_IDIV_MEMb_DEFINED XED_IFORM_IDIV_MEMi8_APX_DEFINED XED_IFORM_IDIV_MEMv_APX_DEFINED XED_IFORM_IDIV_MEMv_DEFINED XED_IFORM_IMUL_GPR8_DEFINED XED_IFORM_IMUL_GPR8i8_APX_DEFINED XED_IFORM_IMUL_GPRv_APX_DEFINED XED_IFORM_IMUL_GPRv_DEFINED XED_IFORM_IMUL_GPRv_GPRv_APX_DEFINED XED_IFORM_IMUL_GPRv_GPRv_DEFINED XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_IMUL_GPRv_MEMv_APX_DEFINED XED_IFORM_IMUL_GPRv_MEMv_DEFINED XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED XED_IFORM_IMUL_MEMb_DEFINED XED_IFORM_IMUL_MEMi8_APX_DEFINED XED_IFORM_IMUL_MEMv_APX_DEFINED XED_IFORM_IMUL_MEMv_DEFINED XED_IFORM_INCSSPD_GPR32u8_DEFINED XED_IFORM_INCSSPQ_GPR64u8_DEFINED XED_IFORM_INC_GPR8_DEFINED XED_IFORM_INC_GPR8i8_APX_DEFINED XED_IFORM_INC_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_INC_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_INC_GPRv_40_DEFINED XED_IFORM_INC_GPRv_APX_DEFINED XED_IFORM_INC_GPRv_FFr0_DEFINED XED_IFORM_INC_GPRv_GPRv_APX_DEFINED XED_IFORM_INC_GPRv_MEMv_APX_DEFINED XED_IFORM_INC_LOCK_MEMb_DEFINED XED_IFORM_INC_LOCK_MEMv_DEFINED XED_IFORM_INC_MEMb_DEFINED XED_IFORM_INC_MEMi8_APX_DEFINED XED_IFORM_INC_MEMv_APX_DEFINED XED_IFORM_INC_MEMv_DEFINED XED_IFORM_INSB_DEFINED XED_IFORM_INSD_DEFINED XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED XED_IFORM_INSW_DEFINED XED_IFORM_INT1_DEFINED XED_IFORM_INT3_DEFINED XED_IFORM_INTO_DEFINED XED_IFORM_INT_IMMb_DEFINED XED_IFORM_INVALID_DEFINED XED_IFORM_INVD_DEFINED XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED XED_IFORM_INVEPT_GPR64i64_MEMi128_APX_DEFINED XED_IFORM_INVLPGA_ArAX_ECX_DEFINED XED_IFORM_INVLPGB_EAX_EDX_ECX_DEFINED XED_IFORM_INVLPGB_RAX_EDX_ECX_DEFINED XED_IFORM_INVLPG_MEMb_DEFINED XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED XED_IFORM_INVPCID_GPR64i64_MEMi128_APX_DEFINED XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED XED_IFORM_INVVPID_GPR64i64_MEMi128_APX_DEFINED XED_IFORM_IN_AL_DX_DEFINED XED_IFORM_IN_AL_IMMb_DEFINED XED_IFORM_IN_OeAX_DX_DEFINED XED_IFORM_IN_OeAX_IMMb_DEFINED XED_IFORM_IRETD_DEFINED XED_IFORM_IRETQ_DEFINED XED_IFORM_IRET_DEFINED XED_IFORM_JBE_RELBRb_DEFINED XED_IFORM_JBE_RELBRd_DEFINED XED_IFORM_JBE_RELBRz_DEFINED XED_IFORM_JB_RELBRb_DEFINED XED_IFORM_JB_RELBRd_DEFINED XED_IFORM_JB_RELBRz_DEFINED XED_IFORM_JCXZ_RELBRb_DEFINED XED_IFORM_JECXZ_RELBRb_DEFINED XED_IFORM_JLE_RELBRb_DEFINED XED_IFORM_JLE_RELBRd_DEFINED XED_IFORM_JLE_RELBRz_DEFINED XED_IFORM_JL_RELBRb_DEFINED XED_IFORM_JL_RELBRd_DEFINED XED_IFORM_JL_RELBRz_DEFINED XED_IFORM_JMPABS_ABSBRu64_APX_DEFINED XED_IFORM_JMP_FAR_MEMp2_DEFINED XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED XED_IFORM_JMP_GPRv_DEFINED XED_IFORM_JMP_MEMv_DEFINED XED_IFORM_JMP_RELBRb_DEFINED XED_IFORM_JMP_RELBRd_DEFINED XED_IFORM_JMP_RELBRz_DEFINED XED_IFORM_JNBE_RELBRb_DEFINED XED_IFORM_JNBE_RELBRd_DEFINED XED_IFORM_JNBE_RELBRz_DEFINED XED_IFORM_JNB_RELBRb_DEFINED XED_IFORM_JNB_RELBRd_DEFINED XED_IFORM_JNB_RELBRz_DEFINED XED_IFORM_JNLE_RELBRb_DEFINED XED_IFORM_JNLE_RELBRd_DEFINED XED_IFORM_JNLE_RELBRz_DEFINED XED_IFORM_JNL_RELBRb_DEFINED XED_IFORM_JNL_RELBRd_DEFINED XED_IFORM_JNL_RELBRz_DEFINED XED_IFORM_JNO_RELBRb_DEFINED XED_IFORM_JNO_RELBRd_DEFINED XED_IFORM_JNO_RELBRz_DEFINED XED_IFORM_JNP_RELBRb_DEFINED XED_IFORM_JNP_RELBRd_DEFINED XED_IFORM_JNP_RELBRz_DEFINED XED_IFORM_JNS_RELBRb_DEFINED XED_IFORM_JNS_RELBRd_DEFINED XED_IFORM_JNS_RELBRz_DEFINED XED_IFORM_JNZ_RELBRb_DEFINED XED_IFORM_JNZ_RELBRd_DEFINED XED_IFORM_JNZ_RELBRz_DEFINED XED_IFORM_JO_RELBRb_DEFINED XED_IFORM_JO_RELBRd_DEFINED XED_IFORM_JO_RELBRz_DEFINED XED_IFORM_JP_RELBRb_DEFINED XED_IFORM_JP_RELBRd_DEFINED XED_IFORM_JP_RELBRz_DEFINED XED_IFORM_JRCXZ_RELBRb_DEFINED XED_IFORM_JS_RELBRb_DEFINED XED_IFORM_JS_RELBRd_DEFINED XED_IFORM_JS_RELBRz_DEFINED XED_IFORM_JZ_RELBRb_DEFINED XED_IFORM_JZ_RELBRd_DEFINED XED_IFORM_JZ_RELBRz_DEFINED XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX_DEFINED XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX_DEFINED XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_KMOVB_MASKmskw_MASKu8_APX_DEFINED XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED XED_IFORM_KMOVB_MASKmskw_MEMu8_APX_DEFINED XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_KMOVB_MEMu8_MASKmskw_APX_DEFINED XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX_DEFINED XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX_DEFINED XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_KMOVD_MASKmskw_MASKu32_APX_DEFINED XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED XED_IFORM_KMOVD_MASKmskw_MEMu32_APX_DEFINED XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_KMOVD_MEMu32_MASKmskw_APX_DEFINED XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX_DEFINED XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX_DEFINED XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX_DEFINED XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX_DEFINED XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX_DEFINED XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX_DEFINED XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX_DEFINED XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_KMOVW_MASKmskw_MASKu16_APX_DEFINED XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED XED_IFORM_KMOVW_MASKmskw_MEMu16_APX_DEFINED XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_KMOVW_MEMu16_MASKmskw_APX_DEFINED XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED XED_IFORM_LAHF_DEFINED XED_IFORM_LAR_GPRv_GPRv_DEFINED XED_IFORM_LAR_GPRv_MEMw_DEFINED XED_IFORM_LAST_DEFINED XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED XED_IFORM_LDMXCSR_MEMd_DEFINED XED_IFORM_LDS_GPRz_MEMp_DEFINED XED_IFORM_LDTILECFG_MEM_APX_DEFINED XED_IFORM_LDTILECFG_MEM_DEFINED XED_IFORM_LEAVE_DEFINED XED_IFORM_LEA_GPRv_AGEN_DEFINED XED_IFORM_LES_GPRz_MEMp_DEFINED XED_IFORM_LFENCE_DEFINED XED_IFORM_LFS_GPRv_MEMp2_DEFINED XED_IFORM_LGDT_MEMs64_DEFINED XED_IFORM_LGDT_MEMs_DEFINED XED_IFORM_LGS_GPRv_MEMp2_DEFINED XED_IFORM_LIDT_MEMs64_DEFINED XED_IFORM_LIDT_MEMs_DEFINED XED_IFORM_LKGS_GPR16u16_DEFINED XED_IFORM_LKGS_MEMu16_DEFINED XED_IFORM_LLDT_GPR16_DEFINED XED_IFORM_LLDT_MEMw_DEFINED XED_IFORM_LLWPCB_VGPRyy_DEFINED XED_IFORM_LMSW_GPR16_DEFINED XED_IFORM_LMSW_MEMw_DEFINED XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED XED_IFORM_LODSB_DEFINED XED_IFORM_LODSD_DEFINED XED_IFORM_LODSQ_DEFINED XED_IFORM_LODSW_DEFINED XED_IFORM_LOOPE_RELBRb_DEFINED XED_IFORM_LOOPNE_RELBRb_DEFINED XED_IFORM_LOOP_RELBRb_DEFINED XED_IFORM_LSL_GPRv_GPRz_DEFINED XED_IFORM_LSL_GPRv_MEMw_DEFINED XED_IFORM_LSS_GPRv_MEMp2_DEFINED XED_IFORM_LTR_GPR16_DEFINED XED_IFORM_LTR_MEMw_DEFINED XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd_DEFINED XED_IFORM_LWPINS_VGPRyy_VGPR32d_IMMd_DEFINED XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd_DEFINED XED_IFORM_LWPVAL_VGPRyy_VGPR32d_IMMd_DEFINED XED_IFORM_LZCNT_GPRv_GPRv_APX_DEFINED XED_IFORM_LZCNT_GPRv_GPRv_DEFINED XED_IFORM_LZCNT_GPRv_MEMv_APX_DEFINED XED_IFORM_LZCNT_GPRv_MEMv_DEFINED XED_IFORM_MASKMOVDQU_XMMxub_XMMxub_DEFINED XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED XED_IFORM_MAXPS_XMMps_MEMps_DEFINED XED_IFORM_MAXPS_XMMps_XMMps_DEFINED XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED XED_IFORM_MAXSS_XMMss_MEMss_DEFINED XED_IFORM_MAXSS_XMMss_XMMss_DEFINED XED_IFORM_MCOMMIT_DEFINED XED_IFORM_MFENCE_DEFINED XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED XED_IFORM_MINPS_XMMps_MEMps_DEFINED XED_IFORM_MINPS_XMMps_XMMps_DEFINED XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED XED_IFORM_MINSS_XMMss_MEMss_DEFINED XED_IFORM_MINSS_XMMss_XMMss_DEFINED XED_IFORM_MONITORX_DEFINED XED_IFORM_MONITOR_DEFINED XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED XED_IFORM_MOVBE_GPRv_GPRv_APX_DEFINED XED_IFORM_MOVBE_GPRv_MEMv_APX_DEFINED XED_IFORM_MOVBE_GPRv_MEMv_DEFINED XED_IFORM_MOVBE_MEMv_GPRv_APX_DEFINED XED_IFORM_MOVBE_MEMv_GPRv_DEFINED XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX_DEFINED XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX_DEFINED XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED XED_IFORM_MOVD_GPR32_MMXd_DEFINED XED_IFORM_MOVD_GPR32_XMMd_DEFINED XED_IFORM_MOVD_MEMd_MMXd_DEFINED XED_IFORM_MOVD_MEMd_XMMd_DEFINED XED_IFORM_MOVD_MMXq_GPR32_DEFINED XED_IFORM_MOVD_MMXq_MEMd_DEFINED XED_IFORM_MOVD_XMMdq_GPR32_DEFINED XED_IFORM_MOVD_XMMdq_MEMd_DEFINED XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED XED_IFORM_MOVQ_GPR64_MMXq_DEFINED XED_IFORM_MOVQ_GPR64_XMMq_DEFINED XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED XED_IFORM_MOVQ_MMXq_GPR64_DEFINED XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED XED_IFORM_MOVSB_DEFINED XED_IFORM_MOVSD_DEFINED XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED XED_IFORM_MOVSQ_DEFINED XED_IFORM_MOVSS_MEMss_XMMss_DEFINED XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED XED_IFORM_MOVSW_DEFINED XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED XED_IFORM_MOVSXD_GPRv_MEMz_DEFINED XED_IFORM_MOVSX_GPRv_GPR8_DEFINED XED_IFORM_MOVSX_GPRv_GPR16_DEFINED XED_IFORM_MOVSX_GPRv_MEMb_DEFINED XED_IFORM_MOVSX_GPRv_MEMw_DEFINED XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED XED_IFORM_MOVZX_GPRv_GPR8_DEFINED XED_IFORM_MOVZX_GPRv_GPR16_DEFINED XED_IFORM_MOVZX_GPRv_MEMb_DEFINED XED_IFORM_MOVZX_GPRv_MEMw_DEFINED XED_IFORM_MOV_AL_MEMb_DEFINED XED_IFORM_MOV_CR_CR_GPR32_DEFINED XED_IFORM_MOV_CR_CR_GPR64_DEFINED XED_IFORM_MOV_CR_GPR32_CR_DEFINED XED_IFORM_MOV_CR_GPR64_CR_DEFINED XED_IFORM_MOV_DR_DR_GPR32_DEFINED XED_IFORM_MOV_DR_DR_GPR64_DEFINED XED_IFORM_MOV_DR_GPR32_DR_DEFINED XED_IFORM_MOV_DR_GPR64_DR_DEFINED XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED XED_IFORM_MOV_GPR8_GPR8_88_DEFINED XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED XED_IFORM_MOV_GPR8_MEMb_DEFINED XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED XED_IFORM_MOV_GPRv_GPRv_89_DEFINED XED_IFORM_MOV_GPRv_IMMv_DEFINED XED_IFORM_MOV_GPRv_IMMz_DEFINED XED_IFORM_MOV_GPRv_MEMv_DEFINED XED_IFORM_MOV_GPRv_SEG_DEFINED XED_IFORM_MOV_MEMb_AL_DEFINED XED_IFORM_MOV_MEMb_GPR8_DEFINED XED_IFORM_MOV_MEMb_IMMb_DEFINED XED_IFORM_MOV_MEMv_GPRv_DEFINED XED_IFORM_MOV_MEMv_IMMz_DEFINED XED_IFORM_MOV_MEMv_OrAX_DEFINED XED_IFORM_MOV_MEMw_SEG_DEFINED XED_IFORM_MOV_OrAX_MEMv_DEFINED XED_IFORM_MOV_SEG_GPR16_DEFINED XED_IFORM_MOV_SEG_MEMw_DEFINED XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED XED_IFORM_MULPS_XMMps_MEMps_DEFINED XED_IFORM_MULPS_XMMps_XMMps_DEFINED XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED XED_IFORM_MULSS_XMMss_MEMss_DEFINED XED_IFORM_MULSS_XMMss_XMMss_DEFINED XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd_DEFINED XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq_DEFINED XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_MUL_GPR8_DEFINED XED_IFORM_MUL_GPR8i8_APX_DEFINED XED_IFORM_MUL_GPRv_APX_DEFINED XED_IFORM_MUL_GPRv_DEFINED XED_IFORM_MUL_MEMb_DEFINED XED_IFORM_MUL_MEMi8_APX_DEFINED XED_IFORM_MUL_MEMv_APX_DEFINED XED_IFORM_MUL_MEMv_DEFINED XED_IFORM_MWAITX_DEFINED XED_IFORM_MWAIT_DEFINED XED_IFORM_NEG_GPR8_DEFINED XED_IFORM_NEG_GPR8i8_APX_DEFINED XED_IFORM_NEG_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_NEG_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_NEG_GPRv_APX_DEFINED XED_IFORM_NEG_GPRv_DEFINED XED_IFORM_NEG_GPRv_GPRv_APX_DEFINED XED_IFORM_NEG_GPRv_MEMv_APX_DEFINED XED_IFORM_NEG_LOCK_MEMb_DEFINED XED_IFORM_NEG_LOCK_MEMv_DEFINED XED_IFORM_NEG_MEMb_DEFINED XED_IFORM_NEG_MEMi8_APX_DEFINED XED_IFORM_NEG_MEMv_APX_DEFINED XED_IFORM_NEG_MEMv_DEFINED XED_IFORM_NOP_90_DEFINED XED_IFORM_NOP_GPRv_0F1F_DEFINED XED_IFORM_NOP_GPRv_0F18r0_DEFINED XED_IFORM_NOP_GPRv_0F18r1_DEFINED XED_IFORM_NOP_GPRv_0F18r2_DEFINED XED_IFORM_NOP_GPRv_0F18r3_DEFINED XED_IFORM_NOP_GPRv_0F18r4_DEFINED XED_IFORM_NOP_GPRv_0F18r5_DEFINED XED_IFORM_NOP_GPRv_0F18r6_DEFINED XED_IFORM_NOP_GPRv_0F18r7_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED XED_IFORM_NOP_MEMv_0F1F_DEFINED XED_IFORM_NOP_MEMv_0F18r4_DEFINED XED_IFORM_NOP_MEMv_0F18r5_DEFINED XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED XED_IFORM_NOT_GPR8_DEFINED XED_IFORM_NOT_GPR8i8_APX_DEFINED XED_IFORM_NOT_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_NOT_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_NOT_GPRv_APX_DEFINED XED_IFORM_NOT_GPRv_DEFINED XED_IFORM_NOT_GPRv_GPRv_APX_DEFINED XED_IFORM_NOT_GPRv_MEMv_APX_DEFINED XED_IFORM_NOT_LOCK_MEMb_DEFINED XED_IFORM_NOT_LOCK_MEMv_DEFINED XED_IFORM_NOT_MEMb_DEFINED XED_IFORM_NOT_MEMi8_APX_DEFINED XED_IFORM_NOT_MEMv_APX_DEFINED XED_IFORM_NOT_MEMv_DEFINED XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED XED_IFORM_OR_AL_IMMb_DEFINED XED_IFORM_OR_GPR8_GPR8_0A_DEFINED XED_IFORM_OR_GPR8_GPR8_08_DEFINED XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED XED_IFORM_OR_GPR8_MEMb_DEFINED XED_IFORM_OR_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_OR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_OR_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_OR_GPRv_GPRv_0B_DEFINED XED_IFORM_OR_GPRv_GPRv_09_DEFINED XED_IFORM_OR_GPRv_GPRv_APX_DEFINED XED_IFORM_OR_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_OR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_OR_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_OR_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_OR_GPRv_IMM8_APX_DEFINED XED_IFORM_OR_GPRv_IMMb_DEFINED XED_IFORM_OR_GPRv_IMMz_APX_DEFINED XED_IFORM_OR_GPRv_IMMz_DEFINED XED_IFORM_OR_GPRv_MEMv_APX_DEFINED XED_IFORM_OR_GPRv_MEMv_DEFINED XED_IFORM_OR_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_OR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_OR_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED XED_IFORM_OR_MEMb_GPR8_DEFINED XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED XED_IFORM_OR_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_OR_MEMi8_IMM8_APX_DEFINED XED_IFORM_OR_MEMv_GPRv_APX_DEFINED XED_IFORM_OR_MEMv_GPRv_DEFINED XED_IFORM_OR_MEMv_IMM8_APX_DEFINED XED_IFORM_OR_MEMv_IMMb_DEFINED XED_IFORM_OR_MEMv_IMMz_APX_DEFINED XED_IFORM_OR_MEMv_IMMz_DEFINED XED_IFORM_OR_OrAX_IMMz_DEFINED XED_IFORM_OUTSB_DEFINED XED_IFORM_OUTSD_DEFINED XED_IFORM_OUTSW_DEFINED XED_IFORM_OUT_DX_AL_DEFINED XED_IFORM_OUT_DX_OeAX_DEFINED XED_IFORM_OUT_IMMb_AL_DEFINED XED_IFORM_OUT_IMMb_OeAX_DEFINED XED_IFORM_PABSB_MMXq_MEMq_DEFINED XED_IFORM_PABSB_MMXq_MMXq_DEFINED XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED XED_IFORM_PABSD_MMXq_MEMq_DEFINED XED_IFORM_PABSD_MMXq_MMXq_DEFINED XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED XED_IFORM_PABSW_MMXq_MEMq_DEFINED XED_IFORM_PABSW_MMXq_MMXq_DEFINED XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED XED_IFORM_PADDB_MMXq_MEMq_DEFINED XED_IFORM_PADDB_MMXq_MMXq_DEFINED XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED XED_IFORM_PADDD_MMXq_MEMq_DEFINED XED_IFORM_PADDD_MMXq_MMXq_DEFINED XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED XED_IFORM_PADDQ_MMXq_MEMq_DEFINED XED_IFORM_PADDQ_MMXq_MMXq_DEFINED XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED XED_IFORM_PADDSB_MMXq_MEMq_DEFINED XED_IFORM_PADDSB_MMXq_MMXq_DEFINED XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED XED_IFORM_PADDSW_MMXq_MEMq_DEFINED XED_IFORM_PADDSW_MMXq_MMXq_DEFINED XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED XED_IFORM_PADDW_MMXq_MEMq_DEFINED XED_IFORM_PADDW_MMXq_MMXq_DEFINED XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PANDN_MMXq_MEMq_DEFINED XED_IFORM_PANDN_MMXq_MMXq_DEFINED XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED XED_IFORM_PAND_MMXq_MEMq_DEFINED XED_IFORM_PAND_MMXq_MMXq_DEFINED XED_IFORM_PAND_XMMdq_MEMdq_DEFINED XED_IFORM_PAND_XMMdq_XMMdq_DEFINED XED_IFORM_PAUSE_DEFINED XED_IFORM_PAVGB_MMXq_MEMq_DEFINED XED_IFORM_PAVGB_MMXq_MMXq_DEFINED XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED XED_IFORM_PAVGW_MMXq_MEMq_DEFINED XED_IFORM_PAVGW_MMXq_MMXq_DEFINED XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PBNDKB_DEFINED XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PCONFIG64_DEFINED XED_IFORM_PCONFIG_DEFINED XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd_DEFINED XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq_DEFINED XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX_DEFINED XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX_DEFINED XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd_DEFINED XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq_DEFINED XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_PF2ID_MMXq_MEMq_DEFINED XED_IFORM_PF2ID_MMXq_MMXq_DEFINED XED_IFORM_PF2IW_MMXq_MEMq_DEFINED XED_IFORM_PF2IW_MMXq_MMXq_DEFINED XED_IFORM_PFACC_MMXq_MEMq_DEFINED XED_IFORM_PFACC_MMXq_MMXq_DEFINED XED_IFORM_PFADD_MMXq_MEMq_DEFINED XED_IFORM_PFADD_MMXq_MMXq_DEFINED XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED XED_IFORM_PFMAX_MMXq_MEMq_DEFINED XED_IFORM_PFMAX_MMXq_MMXq_DEFINED XED_IFORM_PFMIN_MMXq_MEMq_DEFINED XED_IFORM_PFMIN_MMXq_MMXq_DEFINED XED_IFORM_PFMUL_MMXq_MEMq_DEFINED XED_IFORM_PFMUL_MMXq_MMXq_DEFINED XED_IFORM_PFNACC_MMXq_MEMq_DEFINED XED_IFORM_PFNACC_MMXq_MMXq_DEFINED XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED XED_IFORM_PFRCP_MMXq_MEMq_DEFINED XED_IFORM_PFRCP_MMXq_MMXq_DEFINED XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED XED_IFORM_PFSUB_MMXq_MEMq_DEFINED XED_IFORM_PFSUB_MMXq_MMXq_DEFINED XED_IFORM_PHADDD_MMXq_MEMq_DEFINED XED_IFORM_PHADDD_MMXq_MMXq_DEFINED XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED XED_IFORM_PHADDW_MMXq_MEMq_DEFINED XED_IFORM_PHADDW_MMXq_MMXq_DEFINED XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED XED_IFORM_PI2FD_MMXq_MEMq_DEFINED XED_IFORM_PI2FD_MMXq_MMXq_DEFINED XED_IFORM_PI2FW_MMXq_MEMq_DEFINED XED_IFORM_PI2FW_MMXq_MMXq_DEFINED XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED XED_IFORM_PMINSW_MMXq_MEMq_DEFINED XED_IFORM_PMINSW_MMXq_MMXq_DEFINED XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED XED_IFORM_PMINUB_MMXq_MEMq_DEFINED XED_IFORM_PMINUB_MMXq_MMXq_DEFINED XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED XED_IFORM_PMULHW_MMXq_MEMq_DEFINED XED_IFORM_PMULHW_MMXq_MMXq_DEFINED XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED XED_IFORM_PMULLW_MMXq_MEMq_DEFINED XED_IFORM_PMULLW_MMXq_MMXq_DEFINED XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED XED_IFORM_POP2P_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_POP2_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_POPAD_DEFINED XED_IFORM_POPA_DEFINED XED_IFORM_POPCNT_GPRv_GPRv_APX_DEFINED XED_IFORM_POPCNT_GPRv_GPRv_DEFINED XED_IFORM_POPCNT_GPRv_MEMv_APX_DEFINED XED_IFORM_POPCNT_GPRv_MEMv_DEFINED XED_IFORM_POPFD_DEFINED XED_IFORM_POPFQ_DEFINED XED_IFORM_POPF_DEFINED XED_IFORM_POPP_GPRv_DEFINED XED_IFORM_POP_DS_DEFINED XED_IFORM_POP_ES_DEFINED XED_IFORM_POP_FS_DEFINED XED_IFORM_POP_GPRv_8F_DEFINED XED_IFORM_POP_GPRv_58_DEFINED XED_IFORM_POP_GS_DEFINED XED_IFORM_POP_MEMv_DEFINED XED_IFORM_POP_SS_DEFINED XED_IFORM_POR_MMXq_MEMq_DEFINED XED_IFORM_POR_MMXq_MMXq_DEFINED XED_IFORM_POR_XMMdq_MEMdq_DEFINED XED_IFORM_POR_XMMdq_XMMdq_DEFINED XED_IFORM_PREFETCHIT0_MEMu8_DEFINED XED_IFORM_PREFETCHIT1_MEMu8_DEFINED XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED XED_IFORM_PREFETCHWT1_MEMu8_DEFINED XED_IFORM_PREFETCHW_0F0Dr1_DEFINED XED_IFORM_PREFETCHW_0F0Dr3_DEFINED XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED XED_IFORM_PSADBW_MMXq_MEMq_DEFINED XED_IFORM_PSADBW_MMXq_MMXq_DEFINED XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED XED_IFORM_PSIGND_MMXq_MEMq_DEFINED XED_IFORM_PSIGND_MMXq_MMXq_DEFINED XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED XED_IFORM_PSLLD_MMXq_IMMb_DEFINED XED_IFORM_PSLLD_MMXq_MEMq_DEFINED XED_IFORM_PSLLD_MMXq_MMXq_DEFINED XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED XED_IFORM_PSLLW_MMXq_IMMb_DEFINED XED_IFORM_PSLLW_MMXq_MEMq_DEFINED XED_IFORM_PSLLW_MMXq_MMXq_DEFINED XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED XED_IFORM_PSMASH_RAX_DEFINED XED_IFORM_PSRAD_MMXq_IMMb_DEFINED XED_IFORM_PSRAD_MMXq_MEMq_DEFINED XED_IFORM_PSRAD_MMXq_MMXq_DEFINED XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED XED_IFORM_PSRAW_MMXq_IMMb_DEFINED XED_IFORM_PSRAW_MMXq_MEMq_DEFINED XED_IFORM_PSRAW_MMXq_MMXq_DEFINED XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED XED_IFORM_PSRLD_MMXq_IMMb_DEFINED XED_IFORM_PSRLD_MMXq_MEMq_DEFINED XED_IFORM_PSRLD_MMXq_MMXq_DEFINED XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED XED_IFORM_PSRLW_MMXq_IMMb_DEFINED XED_IFORM_PSRLW_MMXq_MEMq_DEFINED XED_IFORM_PSRLW_MMXq_MMXq_DEFINED XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBB_MMXq_MEMq_DEFINED XED_IFORM_PSUBB_MMXq_MMXq_DEFINED XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBD_MMXq_MEMq_DEFINED XED_IFORM_PSUBD_MMXq_MMXq_DEFINED XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED XED_IFORM_PSUBW_MMXq_MEMq_DEFINED XED_IFORM_PSUBW_MMXq_MMXq_DEFINED XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED XED_IFORM_PTWRITE_GPRy_DEFINED XED_IFORM_PTWRITE_MEMy_DEFINED XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX_DEFINED XED_IFORM_PUSHAD_DEFINED XED_IFORM_PUSHA_DEFINED XED_IFORM_PUSHFD_DEFINED XED_IFORM_PUSHFQ_DEFINED XED_IFORM_PUSHF_DEFINED XED_IFORM_PUSHP_GPRv_DEFINED XED_IFORM_PUSH_CS_DEFINED XED_IFORM_PUSH_DS_DEFINED XED_IFORM_PUSH_ES_DEFINED XED_IFORM_PUSH_FS_DEFINED XED_IFORM_PUSH_GPRv_50_DEFINED XED_IFORM_PUSH_GPRv_FFr6_DEFINED XED_IFORM_PUSH_GS_DEFINED XED_IFORM_PUSH_IMMb_DEFINED XED_IFORM_PUSH_IMMz_DEFINED XED_IFORM_PUSH_MEMv_DEFINED XED_IFORM_PUSH_SS_DEFINED XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED XED_IFORM_PXOR_MMXq_MEMq_DEFINED XED_IFORM_PXOR_MMXq_MMXq_DEFINED XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED XED_IFORM_RCL_GPR8_CL_DEFINED XED_IFORM_RCL_GPR8_IMMb_DEFINED XED_IFORM_RCL_GPR8_ONE_DEFINED XED_IFORM_RCL_GPR8i8_CL_APX_DEFINED XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_RCL_GPR8i8_IMM8_APX_DEFINED XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_RCL_GPR8i8_ONE_APX_DEFINED XED_IFORM_RCL_GPRv_CL_APX_DEFINED XED_IFORM_RCL_GPRv_CL_DEFINED XED_IFORM_RCL_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_RCL_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_RCL_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_RCL_GPRv_IMM8_APX_DEFINED XED_IFORM_RCL_GPRv_IMMb_DEFINED XED_IFORM_RCL_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_RCL_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_RCL_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_RCL_GPRv_ONE_APX_DEFINED XED_IFORM_RCL_GPRv_ONE_DEFINED XED_IFORM_RCL_MEMb_CL_DEFINED XED_IFORM_RCL_MEMb_IMMb_DEFINED XED_IFORM_RCL_MEMb_ONE_DEFINED XED_IFORM_RCL_MEMi8_CL_APX_DEFINED XED_IFORM_RCL_MEMi8_IMM8_APX_DEFINED XED_IFORM_RCL_MEMi8_ONE_APX_DEFINED XED_IFORM_RCL_MEMv_CL_APX_DEFINED XED_IFORM_RCL_MEMv_CL_DEFINED XED_IFORM_RCL_MEMv_IMM8_APX_DEFINED XED_IFORM_RCL_MEMv_IMMb_DEFINED XED_IFORM_RCL_MEMv_ONE_APX_DEFINED XED_IFORM_RCL_MEMv_ONE_DEFINED XED_IFORM_RCPPS_XMMps_MEMps_DEFINED XED_IFORM_RCPPS_XMMps_XMMps_DEFINED XED_IFORM_RCPSS_XMMss_MEMss_DEFINED XED_IFORM_RCPSS_XMMss_XMMss_DEFINED XED_IFORM_RCR_GPR8_CL_DEFINED XED_IFORM_RCR_GPR8_IMMb_DEFINED XED_IFORM_RCR_GPR8_ONE_DEFINED XED_IFORM_RCR_GPR8i8_CL_APX_DEFINED XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_RCR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_RCR_GPR8i8_ONE_APX_DEFINED XED_IFORM_RCR_GPRv_CL_APX_DEFINED XED_IFORM_RCR_GPRv_CL_DEFINED XED_IFORM_RCR_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_RCR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_RCR_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_RCR_GPRv_IMM8_APX_DEFINED XED_IFORM_RCR_GPRv_IMMb_DEFINED XED_IFORM_RCR_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_RCR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_RCR_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_RCR_GPRv_ONE_APX_DEFINED XED_IFORM_RCR_GPRv_ONE_DEFINED XED_IFORM_RCR_MEMb_CL_DEFINED XED_IFORM_RCR_MEMb_IMMb_DEFINED XED_IFORM_RCR_MEMb_ONE_DEFINED XED_IFORM_RCR_MEMi8_CL_APX_DEFINED XED_IFORM_RCR_MEMi8_IMM8_APX_DEFINED XED_IFORM_RCR_MEMi8_ONE_APX_DEFINED XED_IFORM_RCR_MEMv_CL_APX_DEFINED XED_IFORM_RCR_MEMv_CL_DEFINED XED_IFORM_RCR_MEMv_IMM8_APX_DEFINED XED_IFORM_RCR_MEMv_IMMb_DEFINED XED_IFORM_RCR_MEMv_ONE_APX_DEFINED XED_IFORM_RCR_MEMv_ONE_DEFINED XED_IFORM_RDFSBASE_GPRy_DEFINED XED_IFORM_RDGSBASE_GPRy_DEFINED XED_IFORM_RDMSRLIST_DEFINED XED_IFORM_RDMSR_DEFINED XED_IFORM_RDPID_GPR32u32_DEFINED XED_IFORM_RDPID_GPR64u64_DEFINED XED_IFORM_RDPKRU_DEFINED XED_IFORM_RDPMC_DEFINED XED_IFORM_RDPRU_DEFINED XED_IFORM_RDRAND_GPRv_DEFINED XED_IFORM_RDSEED_GPRv_DEFINED XED_IFORM_RDSSPD_GPR32u32_DEFINED XED_IFORM_RDSSPQ_GPR64u64_DEFINED XED_IFORM_RDTSCP_DEFINED XED_IFORM_RDTSC_DEFINED XED_IFORM_REPE_CMPSB_DEFINED XED_IFORM_REPE_CMPSD_DEFINED XED_IFORM_REPE_CMPSQ_DEFINED XED_IFORM_REPE_CMPSW_DEFINED XED_IFORM_REPE_SCASB_DEFINED XED_IFORM_REPE_SCASD_DEFINED XED_IFORM_REPE_SCASQ_DEFINED XED_IFORM_REPE_SCASW_DEFINED XED_IFORM_REPNE_CMPSB_DEFINED XED_IFORM_REPNE_CMPSD_DEFINED XED_IFORM_REPNE_CMPSQ_DEFINED XED_IFORM_REPNE_CMPSW_DEFINED XED_IFORM_REPNE_SCASB_DEFINED XED_IFORM_REPNE_SCASD_DEFINED XED_IFORM_REPNE_SCASQ_DEFINED XED_IFORM_REPNE_SCASW_DEFINED XED_IFORM_REP_INSB_DEFINED XED_IFORM_REP_INSD_DEFINED XED_IFORM_REP_INSW_DEFINED XED_IFORM_REP_LODSB_DEFINED XED_IFORM_REP_LODSD_DEFINED XED_IFORM_REP_LODSQ_DEFINED XED_IFORM_REP_LODSW_DEFINED XED_IFORM_REP_MONTMUL_DEFINED XED_IFORM_REP_MOVSB_DEFINED XED_IFORM_REP_MOVSD_DEFINED XED_IFORM_REP_MOVSQ_DEFINED XED_IFORM_REP_MOVSW_DEFINED XED_IFORM_REP_OUTSB_DEFINED XED_IFORM_REP_OUTSD_DEFINED XED_IFORM_REP_OUTSW_DEFINED XED_IFORM_REP_STOSB_DEFINED XED_IFORM_REP_STOSD_DEFINED XED_IFORM_REP_STOSQ_DEFINED XED_IFORM_REP_STOSW_DEFINED XED_IFORM_REP_XCRYPTCBC_DEFINED XED_IFORM_REP_XCRYPTCFB_DEFINED XED_IFORM_REP_XCRYPTCTR_DEFINED XED_IFORM_REP_XCRYPTECB_DEFINED XED_IFORM_REP_XCRYPTOFB_DEFINED XED_IFORM_REP_XSHA1_DEFINED XED_IFORM_REP_XSHA256_DEFINED XED_IFORM_REP_XSTORE_DEFINED XED_IFORM_RET_FAR_DEFINED XED_IFORM_RET_FAR_IMMw_DEFINED XED_IFORM_RET_NEAR_DEFINED XED_IFORM_RET_NEAR_IMMw_DEFINED XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED XED_IFORM_ROL_GPR8_CL_DEFINED XED_IFORM_ROL_GPR8_IMMb_DEFINED XED_IFORM_ROL_GPR8_ONE_DEFINED XED_IFORM_ROL_GPR8i8_CL_APX_DEFINED XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_ROL_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_ROL_GPR8i8_ONE_APX_DEFINED XED_IFORM_ROL_GPRv_CL_APX_DEFINED XED_IFORM_ROL_GPRv_CL_DEFINED XED_IFORM_ROL_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_ROL_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_ROL_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_ROL_GPRv_IMM8_APX_DEFINED XED_IFORM_ROL_GPRv_IMMb_DEFINED XED_IFORM_ROL_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_ROL_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_ROL_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_ROL_GPRv_ONE_APX_DEFINED XED_IFORM_ROL_GPRv_ONE_DEFINED XED_IFORM_ROL_MEMb_CL_DEFINED XED_IFORM_ROL_MEMb_IMMb_DEFINED XED_IFORM_ROL_MEMb_ONE_DEFINED XED_IFORM_ROL_MEMi8_CL_APX_DEFINED XED_IFORM_ROL_MEMi8_IMM8_APX_DEFINED XED_IFORM_ROL_MEMi8_ONE_APX_DEFINED XED_IFORM_ROL_MEMv_CL_APX_DEFINED XED_IFORM_ROL_MEMv_CL_DEFINED XED_IFORM_ROL_MEMv_IMM8_APX_DEFINED XED_IFORM_ROL_MEMv_IMMb_DEFINED XED_IFORM_ROL_MEMv_ONE_APX_DEFINED XED_IFORM_ROL_MEMv_ONE_DEFINED XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX_DEFINED XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX_DEFINED XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX_DEFINED XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX_DEFINED XED_IFORM_RORX_VGPR32d_MEMd_IMMb_DEFINED XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb_DEFINED XED_IFORM_RORX_VGPR64q_MEMq_IMMb_DEFINED XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb_DEFINED XED_IFORM_ROR_GPR8_CL_DEFINED XED_IFORM_ROR_GPR8_IMMb_DEFINED XED_IFORM_ROR_GPR8_ONE_DEFINED XED_IFORM_ROR_GPR8i8_CL_APX_DEFINED XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_ROR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_ROR_GPR8i8_ONE_APX_DEFINED XED_IFORM_ROR_GPRv_CL_APX_DEFINED XED_IFORM_ROR_GPRv_CL_DEFINED XED_IFORM_ROR_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_ROR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_ROR_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_ROR_GPRv_IMM8_APX_DEFINED XED_IFORM_ROR_GPRv_IMMb_DEFINED XED_IFORM_ROR_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_ROR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_ROR_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_ROR_GPRv_ONE_APX_DEFINED XED_IFORM_ROR_GPRv_ONE_DEFINED XED_IFORM_ROR_MEMb_CL_DEFINED XED_IFORM_ROR_MEMb_IMMb_DEFINED XED_IFORM_ROR_MEMb_ONE_DEFINED XED_IFORM_ROR_MEMi8_CL_APX_DEFINED XED_IFORM_ROR_MEMi8_IMM8_APX_DEFINED XED_IFORM_ROR_MEMi8_ONE_APX_DEFINED XED_IFORM_ROR_MEMv_CL_APX_DEFINED XED_IFORM_ROR_MEMv_CL_DEFINED XED_IFORM_ROR_MEMv_IMM8_APX_DEFINED XED_IFORM_ROR_MEMv_IMMb_DEFINED XED_IFORM_ROR_MEMv_ONE_APX_DEFINED XED_IFORM_ROR_MEMv_ONE_DEFINED XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED XED_IFORM_RSM_DEFINED XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED XED_IFORM_RSTORSSP_MEMu64_DEFINED XED_IFORM_SAHF_DEFINED XED_IFORM_SALC_DEFINED XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d_DEFINED XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q_DEFINED XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_SAR_GPR8_CL_DEFINED XED_IFORM_SAR_GPR8_IMMb_DEFINED XED_IFORM_SAR_GPR8_ONE_DEFINED XED_IFORM_SAR_GPR8i8_CL_APX_DEFINED XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_SAR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_SAR_GPR8i8_ONE_APX_DEFINED XED_IFORM_SAR_GPRv_CL_APX_DEFINED XED_IFORM_SAR_GPRv_CL_DEFINED XED_IFORM_SAR_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SAR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SAR_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_SAR_GPRv_IMM8_APX_DEFINED XED_IFORM_SAR_GPRv_IMMb_DEFINED XED_IFORM_SAR_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_SAR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_SAR_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_SAR_GPRv_ONE_APX_DEFINED XED_IFORM_SAR_GPRv_ONE_DEFINED XED_IFORM_SAR_MEMb_CL_DEFINED XED_IFORM_SAR_MEMb_IMMb_DEFINED XED_IFORM_SAR_MEMb_ONE_DEFINED XED_IFORM_SAR_MEMi8_CL_APX_DEFINED XED_IFORM_SAR_MEMi8_IMM8_APX_DEFINED XED_IFORM_SAR_MEMi8_ONE_APX_DEFINED XED_IFORM_SAR_MEMv_CL_APX_DEFINED XED_IFORM_SAR_MEMv_CL_DEFINED XED_IFORM_SAR_MEMv_IMM8_APX_DEFINED XED_IFORM_SAR_MEMv_IMMb_DEFINED XED_IFORM_SAR_MEMv_ONE_APX_DEFINED XED_IFORM_SAR_MEMv_ONE_DEFINED XED_IFORM_SAVEPREVSSP_DEFINED XED_IFORM_SBB_AL_IMMb_DEFINED XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED XED_IFORM_SBB_GPR8_GPR8_18_DEFINED XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED XED_IFORM_SBB_GPR8_MEMb_DEFINED XED_IFORM_SBB_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_SBB_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SBB_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED XED_IFORM_SBB_GPRv_GPRv_19_DEFINED XED_IFORM_SBB_GPRv_GPRv_APX_DEFINED XED_IFORM_SBB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_SBB_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SBB_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_SBB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_SBB_GPRv_IMM8_APX_DEFINED XED_IFORM_SBB_GPRv_IMMb_DEFINED XED_IFORM_SBB_GPRv_IMMz_APX_DEFINED XED_IFORM_SBB_GPRv_IMMz_DEFINED XED_IFORM_SBB_GPRv_MEMv_APX_DEFINED XED_IFORM_SBB_GPRv_MEMv_DEFINED XED_IFORM_SBB_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_SBB_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_SBB_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED XED_IFORM_SBB_MEMb_GPR8_DEFINED XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED XED_IFORM_SBB_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_SBB_MEMi8_IMM8_APX_DEFINED XED_IFORM_SBB_MEMv_GPRv_APX_DEFINED XED_IFORM_SBB_MEMv_GPRv_DEFINED XED_IFORM_SBB_MEMv_IMM8_APX_DEFINED XED_IFORM_SBB_MEMv_IMMb_DEFINED XED_IFORM_SBB_MEMv_IMMz_APX_DEFINED XED_IFORM_SBB_MEMv_IMMz_DEFINED XED_IFORM_SBB_OrAX_IMMz_DEFINED XED_IFORM_SCASB_DEFINED XED_IFORM_SCASD_DEFINED XED_IFORM_SCASQ_DEFINED XED_IFORM_SCASW_DEFINED XED_IFORM_SEAMCALL_DEFINED XED_IFORM_SEAMOPS_DEFINED XED_IFORM_SEAMRET_DEFINED XED_IFORM_SENDUIPI_GPR64u32_DEFINED XED_IFORM_SERIALIZE_DEFINED XED_IFORM_SETBE_GPR8_DEFINED XED_IFORM_SETBE_GPR8i8_APX_DEFINED XED_IFORM_SETBE_MEMb_DEFINED XED_IFORM_SETBE_MEMi8_APX_DEFINED XED_IFORM_SETB_GPR8_DEFINED XED_IFORM_SETB_GPR8i8_APX_DEFINED XED_IFORM_SETB_MEMb_DEFINED XED_IFORM_SETB_MEMi8_APX_DEFINED XED_IFORM_SETLE_GPR8_DEFINED XED_IFORM_SETLE_GPR8i8_APX_DEFINED XED_IFORM_SETLE_MEMb_DEFINED XED_IFORM_SETLE_MEMi8_APX_DEFINED XED_IFORM_SETL_GPR8_DEFINED XED_IFORM_SETL_GPR8i8_APX_DEFINED XED_IFORM_SETL_MEMb_DEFINED XED_IFORM_SETL_MEMi8_APX_DEFINED XED_IFORM_SETNBE_GPR8_DEFINED XED_IFORM_SETNBE_GPR8i8_APX_DEFINED XED_IFORM_SETNBE_MEMb_DEFINED XED_IFORM_SETNBE_MEMi8_APX_DEFINED XED_IFORM_SETNB_GPR8_DEFINED XED_IFORM_SETNB_GPR8i8_APX_DEFINED XED_IFORM_SETNB_MEMb_DEFINED XED_IFORM_SETNB_MEMi8_APX_DEFINED XED_IFORM_SETNLE_GPR8_DEFINED XED_IFORM_SETNLE_GPR8i8_APX_DEFINED XED_IFORM_SETNLE_MEMb_DEFINED XED_IFORM_SETNLE_MEMi8_APX_DEFINED XED_IFORM_SETNL_GPR8_DEFINED XED_IFORM_SETNL_GPR8i8_APX_DEFINED XED_IFORM_SETNL_MEMb_DEFINED XED_IFORM_SETNL_MEMi8_APX_DEFINED XED_IFORM_SETNO_GPR8_DEFINED XED_IFORM_SETNO_GPR8i8_APX_DEFINED XED_IFORM_SETNO_MEMb_DEFINED XED_IFORM_SETNO_MEMi8_APX_DEFINED XED_IFORM_SETNP_GPR8_DEFINED XED_IFORM_SETNP_GPR8i8_APX_DEFINED XED_IFORM_SETNP_MEMb_DEFINED XED_IFORM_SETNP_MEMi8_APX_DEFINED XED_IFORM_SETNS_GPR8_DEFINED XED_IFORM_SETNS_GPR8i8_APX_DEFINED XED_IFORM_SETNS_MEMb_DEFINED XED_IFORM_SETNS_MEMi8_APX_DEFINED XED_IFORM_SETNZ_GPR8_DEFINED XED_IFORM_SETNZ_GPR8i8_APX_DEFINED XED_IFORM_SETNZ_MEMb_DEFINED XED_IFORM_SETNZ_MEMi8_APX_DEFINED XED_IFORM_SETO_GPR8_DEFINED XED_IFORM_SETO_GPR8i8_APX_DEFINED XED_IFORM_SETO_MEMb_DEFINED XED_IFORM_SETO_MEMi8_APX_DEFINED XED_IFORM_SETP_GPR8_DEFINED XED_IFORM_SETP_GPR8i8_APX_DEFINED XED_IFORM_SETP_MEMb_DEFINED XED_IFORM_SETP_MEMi8_APX_DEFINED XED_IFORM_SETSSBSY_DEFINED XED_IFORM_SETS_GPR8_DEFINED XED_IFORM_SETS_GPR8i8_APX_DEFINED XED_IFORM_SETS_MEMb_DEFINED XED_IFORM_SETS_MEMi8_APX_DEFINED XED_IFORM_SETZ_GPR8_DEFINED XED_IFORM_SETZ_GPR8i8_APX_DEFINED XED_IFORM_SETZ_MEMb_DEFINED XED_IFORM_SETZ_MEMi8_APX_DEFINED XED_IFORM_SFENCE_DEFINED XED_IFORM_SGDT_MEMs64_DEFINED XED_IFORM_SGDT_MEMs_DEFINED XED_IFORM_SHA1MSG1_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA1MSG1_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHA1MSG2_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA1MSG2_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_APX_DEFINED XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_APX_DEFINED XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED XED_IFORM_SHA256MSG1_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA256MSG1_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHA256MSG2_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA256MSG2_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_APX_DEFINED XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_APX_DEFINED XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED XED_IFORM_SHLD_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX_DEFINED XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHLD_MEMv_GPRv_CL_APX_DEFINED XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d_DEFINED XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q_DEFINED XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED XED_IFORM_SHL_GPR8i8_CL_APX_DEFINED XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_SHL_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_SHL_GPR8i8_ONE_APX_DEFINED XED_IFORM_SHL_GPRv_CL_APX_DEFINED XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED XED_IFORM_SHL_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHL_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHL_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_SHL_GPRv_IMM8_APX_DEFINED XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED XED_IFORM_SHL_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_SHL_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_SHL_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_SHL_GPRv_ONE_APX_DEFINED XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED XED_IFORM_SHL_MEMi8_CL_APX_DEFINED XED_IFORM_SHL_MEMi8_IMM8_APX_DEFINED XED_IFORM_SHL_MEMi8_ONE_APX_DEFINED XED_IFORM_SHL_MEMv_CL_APX_DEFINED XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED XED_IFORM_SHL_MEMv_IMM8_APX_DEFINED XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED XED_IFORM_SHL_MEMv_ONE_APX_DEFINED XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED XED_IFORM_SHRD_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX_DEFINED XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHRD_MEMv_GPRv_CL_APX_DEFINED XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d_DEFINED XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d_DEFINED XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q_DEFINED XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q_DEFINED XED_IFORM_SHR_GPR8_CL_DEFINED XED_IFORM_SHR_GPR8_IMMb_DEFINED XED_IFORM_SHR_GPR8_ONE_DEFINED XED_IFORM_SHR_GPR8i8_CL_APX_DEFINED XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX_DEFINED XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX_DEFINED XED_IFORM_SHR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX_DEFINED XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX_DEFINED XED_IFORM_SHR_GPR8i8_ONE_APX_DEFINED XED_IFORM_SHR_GPRv_CL_APX_DEFINED XED_IFORM_SHR_GPRv_CL_DEFINED XED_IFORM_SHR_GPRv_GPRv_CL_APX_DEFINED XED_IFORM_SHR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SHR_GPRv_GPRv_ONE_APX_DEFINED XED_IFORM_SHR_GPRv_IMM8_APX_DEFINED XED_IFORM_SHR_GPRv_IMMb_DEFINED XED_IFORM_SHR_GPRv_MEMv_CL_APX_DEFINED XED_IFORM_SHR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_SHR_GPRv_MEMv_ONE_APX_DEFINED XED_IFORM_SHR_GPRv_ONE_APX_DEFINED XED_IFORM_SHR_GPRv_ONE_DEFINED XED_IFORM_SHR_MEMb_CL_DEFINED XED_IFORM_SHR_MEMb_IMMb_DEFINED XED_IFORM_SHR_MEMb_ONE_DEFINED XED_IFORM_SHR_MEMi8_CL_APX_DEFINED XED_IFORM_SHR_MEMi8_IMM8_APX_DEFINED XED_IFORM_SHR_MEMi8_ONE_APX_DEFINED XED_IFORM_SHR_MEMv_CL_APX_DEFINED XED_IFORM_SHR_MEMv_CL_DEFINED XED_IFORM_SHR_MEMv_IMM8_APX_DEFINED XED_IFORM_SHR_MEMv_IMMb_DEFINED XED_IFORM_SHR_MEMv_ONE_APX_DEFINED XED_IFORM_SHR_MEMv_ONE_DEFINED XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED XED_IFORM_SIDT_MEMs64_DEFINED XED_IFORM_SIDT_MEMs_DEFINED XED_IFORM_SKINIT_EAX_DEFINED XED_IFORM_SLDT_GPRv_DEFINED XED_IFORM_SLDT_MEMw_DEFINED XED_IFORM_SLWPCB_VGPRyy_DEFINED XED_IFORM_SMSW_GPRv_DEFINED XED_IFORM_SMSW_MEMw_DEFINED XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED XED_IFORM_STAC_DEFINED XED_IFORM_STC_DEFINED XED_IFORM_STD_DEFINED XED_IFORM_STGI_DEFINED XED_IFORM_STI_DEFINED XED_IFORM_STMXCSR_MEMd_DEFINED XED_IFORM_STOSB_DEFINED XED_IFORM_STOSD_DEFINED XED_IFORM_STOSQ_DEFINED XED_IFORM_STOSW_DEFINED XED_IFORM_STR_GPRv_DEFINED XED_IFORM_STR_MEMw_DEFINED XED_IFORM_STTILECFG_MEM_APX_DEFINED XED_IFORM_STTILECFG_MEM_DEFINED XED_IFORM_STUI_DEFINED XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED XED_IFORM_SUBPS_XMMps_MEMps_DEFINED XED_IFORM_SUBPS_XMMps_XMMps_DEFINED XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED XED_IFORM_SUBSS_XMMss_MEMss_DEFINED XED_IFORM_SUBSS_XMMss_XMMss_DEFINED XED_IFORM_SUB_AL_IMMb_DEFINED XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED XED_IFORM_SUB_GPR8_GPR8_28_DEFINED XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED XED_IFORM_SUB_GPR8_MEMb_DEFINED XED_IFORM_SUB_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_SUB_GPR8i8_IMM8_APX_DEFINED XED_IFORM_SUB_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED XED_IFORM_SUB_GPRv_GPRv_29_DEFINED XED_IFORM_SUB_GPRv_GPRv_APX_DEFINED XED_IFORM_SUB_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_SUB_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_SUB_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_SUB_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_SUB_GPRv_IMM8_APX_DEFINED XED_IFORM_SUB_GPRv_IMMb_DEFINED XED_IFORM_SUB_GPRv_IMMz_APX_DEFINED XED_IFORM_SUB_GPRv_IMMz_DEFINED XED_IFORM_SUB_GPRv_MEMv_APX_DEFINED XED_IFORM_SUB_GPRv_MEMv_DEFINED XED_IFORM_SUB_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_SUB_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_SUB_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED XED_IFORM_SUB_MEMb_GPR8_DEFINED XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED XED_IFORM_SUB_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_SUB_MEMi8_IMM8_APX_DEFINED XED_IFORM_SUB_MEMv_GPRv_APX_DEFINED XED_IFORM_SUB_MEMv_GPRv_DEFINED XED_IFORM_SUB_MEMv_IMM8_APX_DEFINED XED_IFORM_SUB_MEMv_IMMb_DEFINED XED_IFORM_SUB_MEMv_IMMz_APX_DEFINED XED_IFORM_SUB_MEMv_IMMz_DEFINED XED_IFORM_SUB_OrAX_IMMz_DEFINED XED_IFORM_SWAPGS_DEFINED XED_IFORM_SYSCALL_AMD_DEFINED XED_IFORM_SYSCALL_DEFINED XED_IFORM_SYSENTER_DEFINED XED_IFORM_SYSEXIT_DEFINED XED_IFORM_SYSRET64_DEFINED XED_IFORM_SYSRET_AMD_DEFINED XED_IFORM_SYSRET_DEFINED XED_IFORM_T1MSKC_VGPR32d_MEMd_DEFINED XED_IFORM_T1MSKC_VGPR32d_VGPR32d_DEFINED XED_IFORM_T1MSKC_VGPRyy_MEMy_DEFINED XED_IFORM_T1MSKC_VGPRyy_VGPRyy_DEFINED XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED XED_IFORM_TDCALL_DEFINED XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16_DEFINED XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8_DEFINED XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8_DEFINED XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8_DEFINED XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8_DEFINED XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED XED_IFORM_TESTUI_DEFINED XED_IFORM_TEST_AL_IMMb_DEFINED XED_IFORM_TEST_GPR8_GPR8_DEFINED XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED XED_IFORM_TEST_GPRv_GPRv_DEFINED XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED XED_IFORM_TEST_MEMb_GPR8_DEFINED XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED XED_IFORM_TEST_MEMv_GPRv_DEFINED XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED XED_IFORM_TEST_OrAX_IMMz_DEFINED XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX_DEFINED XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED XED_IFORM_TILELOADD_TMMu32_MEMu32_APX_DEFINED XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED XED_IFORM_TILERELEASE_DEFINED XED_IFORM_TILESTORED_MEMu32_TMMu32_APX_DEFINED XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED XED_IFORM_TILEZERO_TMMu32_DEFINED XED_IFORM_TLBSYNC_DEFINED XED_IFORM_TPAUSE_GPR32u32_DEFINED XED_IFORM_TZCNT_GPRv_GPRv_APX_DEFINED XED_IFORM_TZCNT_GPRv_GPRv_DEFINED XED_IFORM_TZCNT_GPRv_MEMv_APX_DEFINED XED_IFORM_TZCNT_GPRv_MEMv_DEFINED XED_IFORM_TZMSK_VGPR32d_MEMd_DEFINED XED_IFORM_TZMSK_VGPR32d_VGPR32d_DEFINED XED_IFORM_TZMSK_VGPRyy_MEMy_DEFINED XED_IFORM_TZMSK_VGPRyy_VGPRyy_DEFINED XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED XED_IFORM_UD0_DEFINED XED_IFORM_UD0_GPR32_GPR32_DEFINED XED_IFORM_UD0_GPR32_MEMd_DEFINED XED_IFORM_UD1_GPR32_GPR32_DEFINED XED_IFORM_UD1_GPR32_MEMd_DEFINED XED_IFORM_UD2_DEFINED XED_IFORM_UIRET_DEFINED XED_IFORM_UMONITOR_GPRa_DEFINED XED_IFORM_UMWAIT_GPR32_DEFINED XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED XED_IFORM_URDMSR_GPR64u64_GPR64u64_DEFINED XED_IFORM_URDMSR_GPR64u64_IMM32_DEFINED XED_IFORM_UWRMSR_GPR64u64_GPR64u64_DEFINED XED_IFORM_UWRMSR_IMM32_GPR64u64_DEFINED XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16_DEFINED XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16_DEFINED XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16_DEFINED XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16_DEFINED XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VERR_GPR16_DEFINED XED_IFORM_VERR_MEMw_DEFINED XED_IFORM_VERW_GPR16_DEFINED XED_IFORM_VERW_MEMw_DEFINED XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED XED_IFORM_VLDMXCSR_MEMd_DEFINED XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub_DEFINED XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMCALL_DEFINED XED_IFORM_VMCLEAR_MEMq_DEFINED XED_IFORM_VMFUNC_DEFINED XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMLAUNCH_DEFINED XED_IFORM_VMLOAD_ArAX_DEFINED XED_IFORM_VMMCALL_DEFINED XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED XED_IFORM_VMOVD_MEMd_XMMd_DEFINED XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VMPTRLD_MEMq_DEFINED XED_IFORM_VMPTRST_MEMq_DEFINED XED_IFORM_VMREAD_GPR32_GPR32_DEFINED XED_IFORM_VMREAD_GPR64_GPR64_DEFINED XED_IFORM_VMREAD_MEMd_GPR32_DEFINED XED_IFORM_VMREAD_MEMq_GPR64_DEFINED XED_IFORM_VMRESUME_DEFINED XED_IFORM_VMRUN_ArAX_DEFINED XED_IFORM_VMSAVE_DEFINED XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED XED_IFORM_VMXOFF_DEFINED XED_IFORM_VMXON_MEMq_DEFINED XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8_DEFINED XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8_DEFINED XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8_DEFINED XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8_DEFINED XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8_DEFINED XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8_DEFINED XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8_DEFINED XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8_DEFINED XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8_DEFINED XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8_DEFINED XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8_DEFINED XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8_DEFINED XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8_DEFINED XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8_DEFINED XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8_DEFINED XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8_DEFINED XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8_DEFINED XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8_DEFINED XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8_DEFINED XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8_DEFINED XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8_DEFINED XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8_DEFINED XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8_DEFINED XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8_DEFINED XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16_DEFINED XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16_DEFINED XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16_DEFINED XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16_DEFINED XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16_DEFINED XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16_DEFINED XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16_DEFINED XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16_DEFINED XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16_DEFINED XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16_DEFINED XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16_DEFINED XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16_DEFINED XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16_DEFINED XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16_DEFINED XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16_DEFINED XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16_DEFINED XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16_DEFINED XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16_DEFINED XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16_DEFINED XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16_DEFINED XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16_DEFINED XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16_DEFINED XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16_DEFINED XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16_DEFINED XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64_DEFINED XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64_DEFINED XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64_DEFINED XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64_DEFINED XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64_DEFINED XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64_DEFINED XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64_DEFINED XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64_DEFINED XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED XED_IFORM_VSHA512MSG1_YMMu64_XMMu64_DEFINED XED_IFORM_VSHA512MSG2_YMMu64_YMMu64_DEFINED XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64_DEFINED XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32_DEFINED XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32_DEFINED XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32_DEFINED XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32_DEFINED XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8_DEFINED XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8_DEFINED XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_DEFINED XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_DEFINED XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_DEFINED XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_DEFINED XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_DEFINED XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_DEFINED XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_DEFINED XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_DEFINED XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VSTMXCSR_MEMd_DEFINED XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED XED_IFORM_VZEROALL_DEFINED XED_IFORM_VZEROUPPER_DEFINED XED_IFORM_WBINVD_DEFINED XED_IFORM_WBNOINVD_DEFINED XED_IFORM_WRFSBASE_GPRy_DEFINED XED_IFORM_WRGSBASE_GPRy_DEFINED XED_IFORM_WRMSRLIST_DEFINED XED_IFORM_WRMSRNS_DEFINED XED_IFORM_WRMSR_DEFINED XED_IFORM_WRPKRU_DEFINED XED_IFORM_WRSSD_MEMu32_GPR32u32_APX_DEFINED XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX_DEFINED XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX_DEFINED XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX_DEFINED XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED XED_IFORM_XABORT_IMMb_DEFINED XED_IFORM_XADD_GPR8_GPR8_DEFINED XED_IFORM_XADD_GPRv_GPRv_DEFINED XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED XED_IFORM_XADD_MEMb_GPR8_DEFINED XED_IFORM_XADD_MEMv_GPRv_DEFINED XED_IFORM_XBEGIN_RELBRz_DEFINED XED_IFORM_XCHG_GPR8_GPR8_DEFINED XED_IFORM_XCHG_GPRv_GPRv_DEFINED XED_IFORM_XCHG_GPRv_OrAX_DEFINED XED_IFORM_XCHG_MEMb_GPR8_DEFINED XED_IFORM_XCHG_MEMv_GPRv_DEFINED XED_IFORM_XEND_DEFINED XED_IFORM_XGETBV_DEFINED XED_IFORM_XLAT_DEFINED XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED XED_IFORM_XOR_AL_IMMb_DEFINED XED_IFORM_XOR_GPR8_GPR8_30_DEFINED XED_IFORM_XOR_GPR8_GPR8_32_DEFINED XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED XED_IFORM_XOR_GPR8_MEMb_DEFINED XED_IFORM_XOR_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX_DEFINED XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_XOR_GPR8i8_IMM8_APX_DEFINED XED_IFORM_XOR_GPR8i8_MEMi8_APX_DEFINED XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX_DEFINED XED_IFORM_XOR_GPRv_GPRv_31_DEFINED XED_IFORM_XOR_GPRv_GPRv_33_DEFINED XED_IFORM_XOR_GPRv_GPRv_APX_DEFINED XED_IFORM_XOR_GPRv_GPRv_GPRv_APX_DEFINED XED_IFORM_XOR_GPRv_GPRv_IMM8_APX_DEFINED XED_IFORM_XOR_GPRv_GPRv_IMMz_APX_DEFINED XED_IFORM_XOR_GPRv_GPRv_MEMv_APX_DEFINED XED_IFORM_XOR_GPRv_IMM8_APX_DEFINED XED_IFORM_XOR_GPRv_IMMb_DEFINED XED_IFORM_XOR_GPRv_IMMz_APX_DEFINED XED_IFORM_XOR_GPRv_IMMz_DEFINED XED_IFORM_XOR_GPRv_MEMv_APX_DEFINED XED_IFORM_XOR_GPRv_MEMv_DEFINED XED_IFORM_XOR_GPRv_MEMv_GPRv_APX_DEFINED XED_IFORM_XOR_GPRv_MEMv_IMM8_APX_DEFINED XED_IFORM_XOR_GPRv_MEMv_IMMz_APX_DEFINED XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED XED_IFORM_XOR_MEMb_GPR8_DEFINED XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED XED_IFORM_XOR_MEMi8_GPR8i8_APX_DEFINED XED_IFORM_XOR_MEMi8_IMM8_APX_DEFINED XED_IFORM_XOR_MEMv_GPRv_APX_DEFINED XED_IFORM_XOR_MEMv_GPRv_DEFINED XED_IFORM_XOR_MEMv_IMM8_APX_DEFINED XED_IFORM_XOR_MEMv_IMMb_DEFINED XED_IFORM_XOR_MEMv_IMMz_APX_DEFINED XED_IFORM_XOR_MEMv_IMMz_DEFINED XED_IFORM_XOR_OrAX_IMMz_DEFINED XED_IFORM_XRESLDTRK_DEFINED XED_IFORM_XRSTOR64_MEMmxsave_DEFINED XED_IFORM_XRSTORS64_MEMmxsave_DEFINED XED_IFORM_XRSTORS_MEMmxsave_DEFINED XED_IFORM_XRSTOR_MEMmxsave_DEFINED XED_IFORM_XSAVE64_MEMmxsave_DEFINED XED_IFORM_XSAVEC64_MEMmxsave_DEFINED XED_IFORM_XSAVEC_MEMmxsave_DEFINED XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED XED_IFORM_XSAVES64_MEMmxsave_DEFINED XED_IFORM_XSAVES_MEMmxsave_DEFINED XED_IFORM_XSAVE_MEMmxsave_DEFINED XED_IFORM_XSETBV_DEFINED XED_IFORM_XSTORE_DEFINED XED_IFORM_XSUSLDTRK_DEFINED XED_IFORM_XTEST_DEFINED XED_INFO2_VERBOSE XED_INFO_VERBOSE XED_ISA_SET_3DNOW_DEFINED XED_ISA_SET_ADOX_ADCX_DEFINED XED_ISA_SET_AES_DEFINED XED_ISA_SET_AMD_DEFINED XED_ISA_SET_AMD_INVLPGB_DEFINED XED_ISA_SET_AMX_BF16_DEFINED XED_ISA_SET_AMX_COMPLEX_DEFINED XED_ISA_SET_AMX_FP16_DEFINED XED_ISA_SET_AMX_INT8_DEFINED XED_ISA_SET_AMX_TILE_DEFINED XED_ISA_SET_APX_F_AMX_DEFINED XED_ISA_SET_APX_F_DEFINED XED_ISA_SET_APX_F_KOPB_DEFINED XED_ISA_SET_APX_F_KOPD_DEFINED XED_ISA_SET_APX_F_KOPQ_DEFINED XED_ISA_SET_APX_F_KOPW_DEFINED XED_ISA_SET_AVX2GATHER_DEFINED XED_ISA_SET_AVX2_DEFINED XED_ISA_SET_AVX512BW_128N_DEFINED XED_ISA_SET_AVX512BW_128_DEFINED XED_ISA_SET_AVX512BW_256_DEFINED XED_ISA_SET_AVX512BW_512_DEFINED XED_ISA_SET_AVX512BW_KOPD_DEFINED XED_ISA_SET_AVX512BW_KOPQ_DEFINED XED_ISA_SET_AVX512CD_128_DEFINED XED_ISA_SET_AVX512CD_256_DEFINED XED_ISA_SET_AVX512CD_512_DEFINED XED_ISA_SET_AVX512DQ_128N_DEFINED XED_ISA_SET_AVX512DQ_128_DEFINED XED_ISA_SET_AVX512DQ_256_DEFINED XED_ISA_SET_AVX512DQ_512_DEFINED XED_ISA_SET_AVX512DQ_KOPB_DEFINED XED_ISA_SET_AVX512DQ_KOPW_DEFINED XED_ISA_SET_AVX512DQ_SCALAR_DEFINED XED_ISA_SET_AVX512ER_512_DEFINED XED_ISA_SET_AVX512ER_SCALAR_DEFINED XED_ISA_SET_AVX512F_128N_DEFINED XED_ISA_SET_AVX512F_128_DEFINED XED_ISA_SET_AVX512F_256_DEFINED XED_ISA_SET_AVX512F_512_DEFINED XED_ISA_SET_AVX512F_KOPW_DEFINED XED_ISA_SET_AVX512F_SCALAR_DEFINED XED_ISA_SET_AVX512PF_512_DEFINED XED_ISA_SET_AVX512_4FMAPS_512_DEFINED XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED XED_ISA_SET_AVX512_4VNNIW_512_DEFINED XED_ISA_SET_AVX512_BF16_128_DEFINED XED_ISA_SET_AVX512_BF16_256_DEFINED XED_ISA_SET_AVX512_BF16_512_DEFINED XED_ISA_SET_AVX512_BITALG_128_DEFINED XED_ISA_SET_AVX512_BITALG_256_DEFINED XED_ISA_SET_AVX512_BITALG_512_DEFINED XED_ISA_SET_AVX512_FP16_128N_DEFINED XED_ISA_SET_AVX512_FP16_128_DEFINED XED_ISA_SET_AVX512_FP16_256_DEFINED XED_ISA_SET_AVX512_FP16_512_DEFINED XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED XED_ISA_SET_AVX512_GFNI_128_DEFINED XED_ISA_SET_AVX512_GFNI_256_DEFINED XED_ISA_SET_AVX512_GFNI_512_DEFINED XED_ISA_SET_AVX512_IFMA_128_DEFINED XED_ISA_SET_AVX512_IFMA_256_DEFINED XED_ISA_SET_AVX512_IFMA_512_DEFINED XED_ISA_SET_AVX512_VAES_128_DEFINED XED_ISA_SET_AVX512_VAES_256_DEFINED XED_ISA_SET_AVX512_VAES_512_DEFINED XED_ISA_SET_AVX512_VBMI2_128_DEFINED XED_ISA_SET_AVX512_VBMI2_256_DEFINED XED_ISA_SET_AVX512_VBMI2_512_DEFINED XED_ISA_SET_AVX512_VBMI_128_DEFINED XED_ISA_SET_AVX512_VBMI_256_DEFINED XED_ISA_SET_AVX512_VBMI_512_DEFINED XED_ISA_SET_AVX512_VNNI_128_DEFINED XED_ISA_SET_AVX512_VNNI_256_DEFINED XED_ISA_SET_AVX512_VNNI_512_DEFINED XED_ISA_SET_AVX512_VP2INTERSECT_128_DEFINED XED_ISA_SET_AVX512_VP2INTERSECT_256_DEFINED XED_ISA_SET_AVX512_VP2INTERSECT_512_DEFINED XED_ISA_SET_AVX512_VPCLMULQDQ_128_DEFINED XED_ISA_SET_AVX512_VPCLMULQDQ_256_DEFINED XED_ISA_SET_AVX512_VPCLMULQDQ_512_DEFINED XED_ISA_SET_AVX512_VPOPCNTDQ_128_DEFINED XED_ISA_SET_AVX512_VPOPCNTDQ_256_DEFINED XED_ISA_SET_AVX512_VPOPCNTDQ_512_DEFINED XED_ISA_SET_AVXAES_DEFINED XED_ISA_SET_AVX_DEFINED XED_ISA_SET_AVX_GFNI_DEFINED XED_ISA_SET_AVX_IFMA_DEFINED XED_ISA_SET_AVX_NE_CONVERT_DEFINED XED_ISA_SET_AVX_VNNI_DEFINED XED_ISA_SET_AVX_VNNI_INT8_DEFINED XED_ISA_SET_AVX_VNNI_INT16_DEFINED XED_ISA_SET_BMI1_DEFINED XED_ISA_SET_BMI2_DEFINED XED_ISA_SET_CET_DEFINED XED_ISA_SET_CLDEMOTE_DEFINED XED_ISA_SET_CLFLUSHOPT_DEFINED XED_ISA_SET_CLFSH_DEFINED XED_ISA_SET_CLWB_DEFINED XED_ISA_SET_CLZERO_DEFINED XED_ISA_SET_CMOV_DEFINED XED_ISA_SET_CMPCCXADD_DEFINED XED_ISA_SET_CMPXCHG16B_DEFINED XED_ISA_SET_ENQCMD_DEFINED XED_ISA_SET_F16C_DEFINED XED_ISA_SET_FAT_NOP_DEFINED XED_ISA_SET_FCMOV_DEFINED XED_ISA_SET_FCOMI_DEFINED XED_ISA_SET_FMA4_DEFINED XED_ISA_SET_FMA_DEFINED XED_ISA_SET_FRED_DEFINED XED_ISA_SET_FXSAVE64_DEFINED XED_ISA_SET_FXSAVE_DEFINED XED_ISA_SET_GFNI_DEFINED XED_ISA_SET_HRESET_DEFINED XED_ISA_SET_I86_DEFINED XED_ISA_SET_I186_DEFINED XED_ISA_SET_I286PROTECTED_DEFINED XED_ISA_SET_I286REAL_DEFINED XED_ISA_SET_I386_DEFINED XED_ISA_SET_I486REAL_DEFINED XED_ISA_SET_I486_DEFINED XED_ISA_SET_ICACHE_PREFETCH_DEFINED XED_ISA_SET_INVALID_DEFINED XED_ISA_SET_INVPCID_DEFINED XED_ISA_SET_KEYLOCKER_DEFINED XED_ISA_SET_KEYLOCKER_WIDE_DEFINED XED_ISA_SET_LAHF_DEFINED XED_ISA_SET_LAST_DEFINED XED_ISA_SET_LKGS_DEFINED XED_ISA_SET_LONGMODE_DEFINED XED_ISA_SET_LWP_DEFINED XED_ISA_SET_LZCNT_DEFINED XED_ISA_SET_MCOMMIT_DEFINED XED_ISA_SET_MONITORX_DEFINED XED_ISA_SET_MONITOR_DEFINED XED_ISA_SET_MOVBE_DEFINED XED_ISA_SET_MOVDIR_DEFINED XED_ISA_SET_MPX_DEFINED XED_ISA_SET_MSRLIST_DEFINED XED_ISA_SET_PAUSE_DEFINED XED_ISA_SET_PBNDKB_DEFINED XED_ISA_SET_PCLMULQDQ_DEFINED XED_ISA_SET_PCONFIG_DEFINED XED_ISA_SET_PENTIUMMMX_DEFINED XED_ISA_SET_PENTIUMREAL_DEFINED XED_ISA_SET_PKU_DEFINED XED_ISA_SET_POPCNT_DEFINED XED_ISA_SET_PPRO_DEFINED XED_ISA_SET_PPRO_UD0_LONG_DEFINED XED_ISA_SET_PPRO_UD0_SHORT_DEFINED XED_ISA_SET_PREFETCHWT1_DEFINED XED_ISA_SET_PREFETCHW_DEFINED XED_ISA_SET_PREFETCH_NOP_DEFINED XED_ISA_SET_PTWRITE_DEFINED XED_ISA_SET_RAO_INT_DEFINED XED_ISA_SET_RDPID_DEFINED XED_ISA_SET_RDPMC_DEFINED XED_ISA_SET_RDPRU_DEFINED XED_ISA_SET_RDRAND_DEFINED XED_ISA_SET_RDSEED_DEFINED XED_ISA_SET_RDTSCP_DEFINED XED_ISA_SET_RDWRFSGS_DEFINED XED_ISA_SET_RTM_DEFINED XED_ISA_SET_SERIALIZE_DEFINED XED_ISA_SET_SGX_DEFINED XED_ISA_SET_SGX_ENCLV_DEFINED XED_ISA_SET_SHA512_DEFINED XED_ISA_SET_SHA_DEFINED XED_ISA_SET_SM3_DEFINED XED_ISA_SET_SM4_DEFINED XED_ISA_SET_SMAP_DEFINED XED_ISA_SET_SMX_DEFINED XED_ISA_SET_SNP_DEFINED XED_ISA_SET_SSE2MMX_DEFINED XED_ISA_SET_SSE2_DEFINED XED_ISA_SET_SSE3X87_DEFINED XED_ISA_SET_SSE3_DEFINED XED_ISA_SET_SSE4A_DEFINED XED_ISA_SET_SSE4_DEFINED XED_ISA_SET_SSE42_DEFINED XED_ISA_SET_SSEMXCSR_DEFINED XED_ISA_SET_SSE_DEFINED XED_ISA_SET_SSE_PREFETCH_DEFINED XED_ISA_SET_SSSE3MMX_DEFINED XED_ISA_SET_SSSE3_DEFINED XED_ISA_SET_SVM_DEFINED XED_ISA_SET_TBM_DEFINED XED_ISA_SET_TDX_DEFINED XED_ISA_SET_TSX_LDTRK_DEFINED XED_ISA_SET_UINTR_DEFINED XED_ISA_SET_USER_MSR_DEFINED XED_ISA_SET_VAES_DEFINED XED_ISA_SET_VIA_PADLOCK_AES_DEFINED XED_ISA_SET_VIA_PADLOCK_MONTMUL_DEFINED XED_ISA_SET_VIA_PADLOCK_RNG_DEFINED XED_ISA_SET_VIA_PADLOCK_SHA_DEFINED XED_ISA_SET_VMFUNC_DEFINED XED_ISA_SET_VPCLMULQDQ_DEFINED XED_ISA_SET_VTX_DEFINED XED_ISA_SET_WAITPKG_DEFINED XED_ISA_SET_WBNOINVD_DEFINED XED_ISA_SET_WRMSRNS_DEFINED XED_ISA_SET_X87_DEFINED XED_ISA_SET_XOP_DEFINED XED_ISA_SET_XSAVEC_DEFINED XED_ISA_SET_XSAVEOPT_DEFINED XED_ISA_SET_XSAVES_DEFINED XED_ISA_SET_XSAVE_DEFINED XED_MACHINE_MODE_INVALID_DEFINED XED_MACHINE_MODE_LAST_DEFINED XED_MACHINE_MODE_LEGACY_16_DEFINED XED_MACHINE_MODE_LEGACY_32_DEFINED XED_MACHINE_MODE_LONG_64_DEFINED XED_MACHINE_MODE_LONG_COMPAT_16_DEFINED XED_MACHINE_MODE_LONG_COMPAT_32_DEFINED XED_MACHINE_MODE_REAL_16_DEFINED XED_MACHINE_MODE_REAL_32_DEFINED XED_MAX_ATTRIBUTE_COUNT XED_MAX_CONVERT_PATTERNS XED_MAX_CPUID_GROUPS_PER_ISA_SET XED_MAX_CPUID_RECS_PER_GROUP XED_MAX_DECORATIONS_PER_OPERAND XED_MAX_DISPLACEMENT_BYTES XED_MAX_GLOBAL_FLAG_ACTIONS XED_MAX_IFORMS_PER_ICLASS XED_MAX_IMMEDIATE_BYTES XED_MAX_INSTRUCTION_BYTES XED_MAX_INST_TABLE_NODES XED_MAX_MAP_EVEX XED_MAX_MAP_VEX XED_MAX_OPERAND_SEQUENCES XED_MAX_OPERAND_TABLE_NODES XED_MAX_REQUIRED_ATTRIBUTES XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES XED_MORE_VERBOSE XED_NONTERMINAL_AR8_DEFINED XED_NONTERMINAL_AR9_DEFINED XED_NONTERMINAL_AR10_DEFINED XED_NONTERMINAL_AR11_DEFINED XED_NONTERMINAL_AR12_DEFINED XED_NONTERMINAL_AR13_DEFINED XED_NONTERMINAL_AR14_DEFINED XED_NONTERMINAL_AR15_DEFINED XED_NONTERMINAL_AR16_DEFINED XED_NONTERMINAL_AR17_DEFINED XED_NONTERMINAL_AR18_DEFINED XED_NONTERMINAL_AR19_DEFINED XED_NONTERMINAL_AR20_DEFINED XED_NONTERMINAL_AR21_DEFINED XED_NONTERMINAL_AR22_DEFINED XED_NONTERMINAL_AR23_DEFINED XED_NONTERMINAL_AR24_DEFINED XED_NONTERMINAL_AR25_DEFINED XED_NONTERMINAL_AR26_DEFINED XED_NONTERMINAL_AR27_DEFINED XED_NONTERMINAL_AR28_DEFINED XED_NONTERMINAL_AR29_DEFINED XED_NONTERMINAL_AR30_DEFINED XED_NONTERMINAL_AR31_DEFINED XED_NONTERMINAL_ARAX_DEFINED XED_NONTERMINAL_ARBP_DEFINED XED_NONTERMINAL_ARBX_DEFINED XED_NONTERMINAL_ARCX_DEFINED XED_NONTERMINAL_ARDI_DEFINED XED_NONTERMINAL_ARDX_DEFINED XED_NONTERMINAL_ARSI_DEFINED XED_NONTERMINAL_ARSP_DEFINED XED_NONTERMINAL_ASZ_NONTERM_DEFINED XED_NONTERMINAL_AVX512_ROUND_DEFINED XED_NONTERMINAL_AVX_INSTRUCTIONS_DEFINED XED_NONTERMINAL_AVX_SPLITTER_DEFINED XED_NONTERMINAL_A_GPR_B_DEFINED XED_NONTERMINAL_A_GPR_R_DEFINED XED_NONTERMINAL_BND_B_CHECK_DEFINED XED_NONTERMINAL_BND_B_DEFINED XED_NONTERMINAL_BND_R_CHECK_DEFINED XED_NONTERMINAL_BND_R_DEFINED XED_NONTERMINAL_BRANCH_HINT_DEFINED XED_NONTERMINAL_BRDISP8_DEFINED XED_NONTERMINAL_BRDISP32_DEFINED XED_NONTERMINAL_BRDISP64_DEFINED XED_NONTERMINAL_BRDISPZ_DEFINED XED_NONTERMINAL_CET_NO_TRACK_DEFINED XED_NONTERMINAL_CR_B_DEFINED XED_NONTERMINAL_CR_R_DEFINED XED_NONTERMINAL_CR_WIDTH_DEFINED XED_NONTERMINAL_DF64_DEFINED XED_NONTERMINAL_DFV_DEFINED XED_NONTERMINAL_DR_R_DEFINED XED_NONTERMINAL_ESIZE_1_BITS_DEFINED XED_NONTERMINAL_ESIZE_2_BITS_DEFINED XED_NONTERMINAL_ESIZE_4_BITS_DEFINED XED_NONTERMINAL_ESIZE_8_BITS_DEFINED XED_NONTERMINAL_ESIZE_16_BITS_DEFINED XED_NONTERMINAL_ESIZE_32_BITS_DEFINED XED_NONTERMINAL_ESIZE_64_BITS_DEFINED XED_NONTERMINAL_ESIZE_128_BITS_DEFINED XED_NONTERMINAL_EVAPX_DEFINED XED_NONTERMINAL_EVAPX_SCC_DEFINED XED_NONTERMINAL_EVEXR4_ONE_DEFINED XED_NONTERMINAL_EVEX_INSTRUCTIONS_DEFINED XED_NONTERMINAL_EVEX_SPLITTER_DEFINED XED_NONTERMINAL_FINAL_DSEG1_DEFINED XED_NONTERMINAL_FINAL_DSEG1_MODE64_DEFINED XED_NONTERMINAL_FINAL_DSEG1_NOT64_DEFINED XED_NONTERMINAL_FINAL_DSEG_DEFINED XED_NONTERMINAL_FINAL_DSEG_MODE64_DEFINED XED_NONTERMINAL_FINAL_DSEG_NOT64_DEFINED XED_NONTERMINAL_FINAL_ESEG1_DEFINED XED_NONTERMINAL_FINAL_ESEG_DEFINED XED_NONTERMINAL_FINAL_SSEG0_DEFINED XED_NONTERMINAL_FINAL_SSEG1_DEFINED XED_NONTERMINAL_FINAL_SSEG_DEFINED XED_NONTERMINAL_FINAL_SSEG_MODE64_DEFINED XED_NONTERMINAL_FINAL_SSEG_NOT64_DEFINED XED_NONTERMINAL_FIX_ROUND_LEN128_DEFINED XED_NONTERMINAL_FIX_ROUND_LEN512_DEFINED XED_NONTERMINAL_FORCE64_DEFINED XED_NONTERMINAL_GPR8_B_DEFINED XED_NONTERMINAL_GPR8_R_DEFINED XED_NONTERMINAL_GPR8_SB_DEFINED XED_NONTERMINAL_GPR16_B_DEFINED XED_NONTERMINAL_GPR16_R_DEFINED XED_NONTERMINAL_GPR16_SB_DEFINED XED_NONTERMINAL_GPR32_B_DEFINED XED_NONTERMINAL_GPR32_R_DEFINED XED_NONTERMINAL_GPR32_SB_DEFINED XED_NONTERMINAL_GPR32_X_DEFINED XED_NONTERMINAL_GPR64_B_DEFINED XED_NONTERMINAL_GPR64_B_NORSP_DEFINED XED_NONTERMINAL_GPR64_R_DEFINED XED_NONTERMINAL_GPR64_SB_DEFINED XED_NONTERMINAL_GPR64_X_DEFINED XED_NONTERMINAL_GPRV_B_DEFINED XED_NONTERMINAL_GPRV_R_DEFINED XED_NONTERMINAL_GPRV_SB_DEFINED XED_NONTERMINAL_GPRY_B_DEFINED XED_NONTERMINAL_GPRY_R_DEFINED XED_NONTERMINAL_GPRZ_B_DEFINED XED_NONTERMINAL_GPRZ_R_DEFINED XED_NONTERMINAL_IGNORE66_DEFINED XED_NONTERMINAL_IMMUNE66_DEFINED XED_NONTERMINAL_IMMUNE66_LOOP64_DEFINED XED_NONTERMINAL_IMMUNE_REXW_DEFINED XED_NONTERMINAL_INSTRUCTIONS_DEFINED XED_NONTERMINAL_INVALID_DEFINED XED_NONTERMINAL_ISA_DEFINED XED_NONTERMINAL_LAST_DEFINED XED_NONTERMINAL_MASK1_DEFINED XED_NONTERMINAL_MASKNOT0_DEFINED XED_NONTERMINAL_MASK_B_DEFINED XED_NONTERMINAL_MASK_N32_DEFINED XED_NONTERMINAL_MASK_N64_DEFINED XED_NONTERMINAL_MASK_N_DEFINED XED_NONTERMINAL_MASK_R_DEFINED XED_NONTERMINAL_MEMDISP8_DEFINED XED_NONTERMINAL_MEMDISP16_DEFINED XED_NONTERMINAL_MEMDISP32_DEFINED XED_NONTERMINAL_MEMDISPV_DEFINED XED_NONTERMINAL_MEMDISP_DEFINED XED_NONTERMINAL_MMX_B_DEFINED XED_NONTERMINAL_MMX_R_DEFINED XED_NONTERMINAL_MODRM16_DEFINED XED_NONTERMINAL_MODRM32_DEFINED XED_NONTERMINAL_MODRM64ALT32_DEFINED XED_NONTERMINAL_MODRM_DEFINED XED_NONTERMINAL_NELEM_EIGHTHMEM_DEFINED XED_NONTERMINAL_NELEM_FULLMEM_DEFINED XED_NONTERMINAL_NELEM_FULL_DEFINED XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED XED_NONTERMINAL_NELEM_GPR_READER_DEFINED XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED XED_NONTERMINAL_NELEM_GSCAT_DEFINED XED_NONTERMINAL_NELEM_HALFMEM_DEFINED XED_NONTERMINAL_NELEM_HALF_DEFINED XED_NONTERMINAL_NELEM_MEM128_DEFINED XED_NONTERMINAL_NELEM_MOVDDUP_DEFINED XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED XED_NONTERMINAL_NELEM_QUARTER_DEFINED XED_NONTERMINAL_NELEM_SCALAR_DEFINED XED_NONTERMINAL_NELEM_TUPLE1_4X_DEFINED XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED XED_NONTERMINAL_NELEM_TUPLE1_DEFINED XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED XED_NONTERMINAL_NELEM_TUPLE2_DEFINED XED_NONTERMINAL_NELEM_TUPLE4_DEFINED XED_NONTERMINAL_NELEM_TUPLE8_DEFINED XED_NONTERMINAL_OEAX_DEFINED XED_NONTERMINAL_ONE_DEFINED XED_NONTERMINAL_ORAX_DEFINED XED_NONTERMINAL_ORBP_DEFINED XED_NONTERMINAL_ORBX_DEFINED XED_NONTERMINAL_ORCX_DEFINED XED_NONTERMINAL_ORDX_DEFINED XED_NONTERMINAL_ORSP_DEFINED XED_NONTERMINAL_OSZ_NONTERM_DEFINED XED_NONTERMINAL_OVERRIDE_SEG0_DEFINED XED_NONTERMINAL_OVERRIDE_SEG1_DEFINED XED_NONTERMINAL_PREFIXES_DEFINED XED_NONTERMINAL_REFINING66_DEFINED XED_NONTERMINAL_REMOVE_SEGMENT_DEFINED XED_NONTERMINAL_RFLAGS_DEFINED XED_NONTERMINAL_RIPA_DEFINED XED_NONTERMINAL_RIP_DEFINED XED_NONTERMINAL_SAE_DEFINED XED_NONTERMINAL_SEG_DEFINED XED_NONTERMINAL_SEG_MOV_DEFINED XED_NONTERMINAL_SE_IMM8_DEFINED XED_NONTERMINAL_SIB_BASE0_DEFINED XED_NONTERMINAL_SIB_DEFINED XED_NONTERMINAL_SIMM8_DEFINED XED_NONTERMINAL_SIMMZ_DEFINED XED_NONTERMINAL_SRBP_DEFINED XED_NONTERMINAL_SRSP_DEFINED XED_NONTERMINAL_TMM_B_DEFINED XED_NONTERMINAL_TMM_N_DEFINED XED_NONTERMINAL_TMM_R3_DEFINED XED_NONTERMINAL_TMM_R_DEFINED XED_NONTERMINAL_UIMM8_1_DEFINED XED_NONTERMINAL_UIMM8_DEFINED XED_NONTERMINAL_UIMM16_DEFINED XED_NONTERMINAL_UIMM32_DEFINED XED_NONTERMINAL_UIMMV_DEFINED XED_NONTERMINAL_UISA_VMODRM_XMM_DEFINED XED_NONTERMINAL_UISA_VMODRM_YMM_DEFINED XED_NONTERMINAL_UISA_VMODRM_ZMM_DEFINED XED_NONTERMINAL_UISA_VSIB_BASE_DEFINED XED_NONTERMINAL_UISA_VSIB_INDEX_XMM_DEFINED XED_NONTERMINAL_UISA_VSIB_INDEX_YMM_DEFINED XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM_DEFINED XED_NONTERMINAL_UISA_VSIB_XMM_DEFINED XED_NONTERMINAL_UISA_VSIB_YMM_DEFINED XED_NONTERMINAL_UISA_VSIB_ZMM_DEFINED XED_NONTERMINAL_VGPR8_N3_64_DEFINED XED_NONTERMINAL_VGPR8_N3_DEFINED XED_NONTERMINAL_VGPR16_N3_64_DEFINED XED_NONTERMINAL_VGPR16_N3_DEFINED XED_NONTERMINAL_VGPR32_B_32_DEFINED XED_NONTERMINAL_VGPR32_B_64_DEFINED XED_NONTERMINAL_VGPR32_B_DEFINED XED_NONTERMINAL_VGPR32_N3_64_DEFINED XED_NONTERMINAL_VGPR32_N3_DEFINED XED_NONTERMINAL_VGPR32_N_32_DEFINED XED_NONTERMINAL_VGPR32_N_64_DEFINED XED_NONTERMINAL_VGPR32_N_DEFINED XED_NONTERMINAL_VGPR32_R_32_DEFINED XED_NONTERMINAL_VGPR32_R_64_DEFINED XED_NONTERMINAL_VGPR32_R_DEFINED XED_NONTERMINAL_VGPR64_B_DEFINED XED_NONTERMINAL_VGPR64_N3_64_DEFINED XED_NONTERMINAL_VGPR64_N3_DEFINED XED_NONTERMINAL_VGPR64_N3_NORSP_DEFINED XED_NONTERMINAL_VGPR64_N_DEFINED XED_NONTERMINAL_VGPR64_R_DEFINED XED_NONTERMINAL_VGPRV_N3_DEFINED XED_NONTERMINAL_VGPRY_B_DEFINED XED_NONTERMINAL_VGPRY_N_DEFINED XED_NONTERMINAL_VGPRY_R_DEFINED XED_NONTERMINAL_VMODRM_XMM_DEFINED XED_NONTERMINAL_VMODRM_YMM_DEFINED XED_NONTERMINAL_VSIB_BASE_DEFINED XED_NONTERMINAL_VSIB_INDEX_XMM_DEFINED XED_NONTERMINAL_VSIB_INDEX_YMM_DEFINED XED_NONTERMINAL_VSIB_XMM_DEFINED XED_NONTERMINAL_VSIB_YMM_DEFINED XED_NONTERMINAL_X87_DEFINED XED_NONTERMINAL_XMM_B3_32_DEFINED XED_NONTERMINAL_XMM_B3_64_DEFINED XED_NONTERMINAL_XMM_B3_DEFINED XED_NONTERMINAL_XMM_B_32_DEFINED XED_NONTERMINAL_XMM_B_64_DEFINED XED_NONTERMINAL_XMM_B_DEFINED XED_NONTERMINAL_XMM_L_B3_64_DEFINED XED_NONTERMINAL_XMM_L_B3_DEFINED XED_NONTERMINAL_XMM_L_R3_64_DEFINED XED_NONTERMINAL_XMM_L_R3_DEFINED XED_NONTERMINAL_XMM_N3_32_DEFINED XED_NONTERMINAL_XMM_N3_64_DEFINED XED_NONTERMINAL_XMM_N3_DEFINED XED_NONTERMINAL_XMM_N_32_DEFINED XED_NONTERMINAL_XMM_N_64_DEFINED XED_NONTERMINAL_XMM_N_DEFINED XED_NONTERMINAL_XMM_R3_32_DEFINED XED_NONTERMINAL_XMM_R3_64_DEFINED XED_NONTERMINAL_XMM_R3_DEFINED XED_NONTERMINAL_XMM_R_32_DEFINED XED_NONTERMINAL_XMM_R_64_DEFINED XED_NONTERMINAL_XMM_R_DEFINED XED_NONTERMINAL_XMM_SE32_DEFINED XED_NONTERMINAL_XMM_SE64_DEFINED XED_NONTERMINAL_XMM_SE_DEFINED XED_NONTERMINAL_XOP_INSTRUCTIONS_DEFINED XED_NONTERMINAL_YMM_B3_32_DEFINED XED_NONTERMINAL_YMM_B3_64_DEFINED XED_NONTERMINAL_YMM_B3_DEFINED XED_NONTERMINAL_YMM_B_32_DEFINED XED_NONTERMINAL_YMM_B_64_DEFINED XED_NONTERMINAL_YMM_B_DEFINED XED_NONTERMINAL_YMM_N3_32_DEFINED XED_NONTERMINAL_YMM_N3_64_DEFINED XED_NONTERMINAL_YMM_N3_DEFINED XED_NONTERMINAL_YMM_N_32_DEFINED XED_NONTERMINAL_YMM_N_64_DEFINED XED_NONTERMINAL_YMM_N_DEFINED XED_NONTERMINAL_YMM_R3_32_DEFINED XED_NONTERMINAL_YMM_R3_64_DEFINED XED_NONTERMINAL_YMM_R3_DEFINED XED_NONTERMINAL_YMM_R_32_DEFINED XED_NONTERMINAL_YMM_R_64_DEFINED XED_NONTERMINAL_YMM_R_DEFINED XED_NONTERMINAL_YMM_SE32_DEFINED XED_NONTERMINAL_YMM_SE64_DEFINED XED_NONTERMINAL_YMM_SE_DEFINED XED_NONTERMINAL_ZMM_B3_32_DEFINED XED_NONTERMINAL_ZMM_B3_64_DEFINED XED_NONTERMINAL_ZMM_B3_DEFINED XED_NONTERMINAL_ZMM_N3_32_DEFINED XED_NONTERMINAL_ZMM_N3_64_DEFINED XED_NONTERMINAL_ZMM_N3_DEFINED XED_NONTERMINAL_ZMM_R3_32_DEFINED XED_NONTERMINAL_ZMM_R3_64_DEFINED XED_NONTERMINAL_ZMM_R3_DEFINED XED_OPERAND_ABSBR_DEFINED XED_OPERAND_ACTION_CRW_DEFINED XED_OPERAND_ACTION_CR_DEFINED XED_OPERAND_ACTION_CW_DEFINED XED_OPERAND_ACTION_INVALID_DEFINED XED_OPERAND_ACTION_LAST_DEFINED XED_OPERAND_ACTION_RCW_DEFINED XED_OPERAND_ACTION_RW_DEFINED XED_OPERAND_ACTION_R_DEFINED XED_OPERAND_ACTION_W_DEFINED XED_OPERAND_AGEN_DEFINED XED_OPERAND_AMD3DNOW_DEFINED XED_OPERAND_ASZ_DEFINED XED_OPERAND_BASE0_DEFINED XED_OPERAND_BASE1_DEFINED XED_OPERAND_BCAST_DEFINED XED_OPERAND_BCRC_DEFINED XED_OPERAND_BRDISP_WIDTH_DEFINED XED_OPERAND_CET_DEFINED XED_OPERAND_CHIP_DEFINED XED_OPERAND_CLDEMOTE_DEFINED XED_OPERAND_CONVERT_BCASTSTR_DEFINED XED_OPERAND_CONVERT_INVALID_DEFINED XED_OPERAND_CONVERT_LAST_DEFINED XED_OPERAND_CONVERT_ROUNDC_DEFINED XED_OPERAND_CONVERT_SAESTR_DEFINED XED_OPERAND_CONVERT_ZEROSTR_DEFINED XED_OPERAND_DEFAULT_SEG_DEFINED XED_OPERAND_DF32_DEFINED XED_OPERAND_DF64_DEFINED XED_OPERAND_DISP_DEFINED XED_OPERAND_DISP_WIDTH_DEFINED XED_OPERAND_DUMMY_DEFINED XED_OPERAND_EASZ_DEFINED XED_OPERAND_ELEMENT_SIZE_DEFINED XED_OPERAND_ELEMENT_TYPE_BFLOAT16_DEFINED XED_OPERAND_ELEMENT_TYPE_DOUBLE_DEFINED XED_OPERAND_ELEMENT_TYPE_FLOAT16_DEFINED XED_OPERAND_ELEMENT_TYPE_INT8_DEFINED XED_OPERAND_ELEMENT_TYPE_INT_DEFINED XED_OPERAND_ELEMENT_TYPE_INVALID_DEFINED XED_OPERAND_ELEMENT_TYPE_LAST_DEFINED XED_OPERAND_ELEMENT_TYPE_LONGBCD_DEFINED XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE_DEFINED XED_OPERAND_ELEMENT_TYPE_SINGLE_DEFINED XED_OPERAND_ELEMENT_TYPE_STRUCT_DEFINED XED_OPERAND_ELEMENT_TYPE_UINT8_DEFINED XED_OPERAND_ELEMENT_TYPE_UINT_DEFINED XED_OPERAND_ELEMENT_TYPE_VARIABLE_DEFINED XED_OPERAND_ENCODER_PREFERRED_DEFINED XED_OPERAND_ENCODE_FORCE_DEFINED XED_OPERAND_EOSZ_DEFINED XED_OPERAND_ERROR_DEFINED XED_OPERAND_ESRC_DEFINED XED_OPERAND_EVVSPACE_DEFINED XED_OPERAND_FIRST_F2F3_DEFINED XED_OPERAND_HAS_EGPR_DEFINED XED_OPERAND_HAS_MODRM_DEFINED XED_OPERAND_HAS_SIB_DEFINED XED_OPERAND_HINT_DEFINED XED_OPERAND_ICLASS_DEFINED XED_OPERAND_ILD_F2_DEFINED XED_OPERAND_ILD_F3_DEFINED XED_OPERAND_ILD_SEG_DEFINED XED_OPERAND_IMM0SIGNED_DEFINED XED_OPERAND_IMM0_DEFINED XED_OPERAND_IMM1_BYTES_DEFINED XED_OPERAND_IMM1_DEFINED XED_OPERAND_IMM_WIDTH_DEFINED XED_OPERAND_INDEX_DEFINED XED_OPERAND_INVALID_DEFINED XED_OPERAND_LAST_DEFINED XED_OPERAND_LAST_F2F3_DEFINED XED_OPERAND_LLRC_DEFINED XED_OPERAND_LOCK_DEFINED XED_OPERAND_LZCNT_DEFINED XED_OPERAND_MAP_DEFINED XED_OPERAND_MASK_DEFINED XED_OPERAND_MAX_BYTES_DEFINED XED_OPERAND_MEM0_DEFINED XED_OPERAND_MEM1_DEFINED XED_OPERAND_MEM_WIDTH_DEFINED XED_OPERAND_MODEP5_DEFINED XED_OPERAND_MODEP55C_DEFINED XED_OPERAND_MODE_DEFINED XED_OPERAND_MODE_FIRST_PREFIX_DEFINED XED_OPERAND_MODE_SHORT_UD0_DEFINED XED_OPERAND_MODRM_BYTE_DEFINED XED_OPERAND_MOD_DEFINED XED_OPERAND_MPXMODE_DEFINED XED_OPERAND_MUST_USE_EVEX_DEFINED XED_OPERAND_ND_DEFINED XED_OPERAND_NEEDREX_DEFINED XED_OPERAND_NEED_MEMDISP_DEFINED XED_OPERAND_NEED_SIB_DEFINED XED_OPERAND_NELEM_DEFINED XED_OPERAND_NF_DEFINED XED_OPERAND_NOMINAL_OPCODE_DEFINED XED_OPERAND_NOREX_DEFINED XED_OPERAND_NO_APX_DEFINED XED_OPERAND_NO_EVEX_DEFINED XED_OPERAND_NO_VEX_DEFINED XED_OPERAND_NPREFIXES_DEFINED XED_OPERAND_NREXES_DEFINED XED_OPERAND_NSEG_PREFIXES_DEFINED XED_OPERAND_OSZ_DEFINED XED_OPERAND_OUTREG_DEFINED XED_OPERAND_OUT_OF_BYTES_DEFINED XED_OPERAND_P4_DEFINED XED_OPERAND_POS_DISP_DEFINED XED_OPERAND_POS_IMM1_DEFINED XED_OPERAND_POS_IMM_DEFINED XED_OPERAND_POS_MODRM_DEFINED XED_OPERAND_POS_NOMINAL_OPCODE_DEFINED XED_OPERAND_POS_SIB_DEFINED XED_OPERAND_PREFIX66_DEFINED XED_OPERAND_PTR_DEFINED XED_OPERAND_REALMODE_DEFINED XED_OPERAND_REG0_DEFINED XED_OPERAND_REG1_DEFINED XED_OPERAND_REG2_DEFINED XED_OPERAND_REG3_DEFINED XED_OPERAND_REG4_DEFINED XED_OPERAND_REG5_DEFINED XED_OPERAND_REG6_DEFINED XED_OPERAND_REG7_DEFINED XED_OPERAND_REG8_DEFINED XED_OPERAND_REG9_DEFINED XED_OPERAND_REG_DEFINED XED_OPERAND_RELBR_DEFINED XED_OPERAND_REP_DEFINED XED_OPERAND_REX2_DEFINED XED_OPERAND_REXB4_DEFINED XED_OPERAND_REXB_DEFINED XED_OPERAND_REXR4_DEFINED XED_OPERAND_REXR_DEFINED XED_OPERAND_REXW_DEFINED XED_OPERAND_REXX4_DEFINED XED_OPERAND_REXX_DEFINED XED_OPERAND_REX_DEFINED XED_OPERAND_RM_DEFINED XED_OPERAND_ROUNDC_DEFINED XED_OPERAND_SAE_DEFINED XED_OPERAND_SCALE_DEFINED XED_OPERAND_SCC_DEFINED XED_OPERAND_SEG0_DEFINED XED_OPERAND_SEG1_DEFINED XED_OPERAND_SEG_OVD_DEFINED XED_OPERAND_SIBBASE_DEFINED XED_OPERAND_SIBINDEX_DEFINED XED_OPERAND_SIBSCALE_DEFINED XED_OPERAND_SKIP_OSZ_DEFINED XED_OPERAND_SMODE_DEFINED XED_OPERAND_SRM_DEFINED XED_OPERAND_TYPE_ERROR_DEFINED XED_OPERAND_TYPE_IMM_CONST_DEFINED XED_OPERAND_TYPE_IMM_DEFINED XED_OPERAND_TYPE_INVALID_DEFINED XED_OPERAND_TYPE_LAST_DEFINED XED_OPERAND_TYPE_NT_LOOKUP_FN2_DEFINED XED_OPERAND_TYPE_NT_LOOKUP_FN4_DEFINED XED_OPERAND_TYPE_NT_LOOKUP_FN_DEFINED XED_OPERAND_TYPE_REG_DEFINED XED_OPERAND_TZCNT_DEFINED XED_OPERAND_UBIT_DEFINED XED_OPERAND_UIMM0_DEFINED XED_OPERAND_UIMM1_DEFINED XED_OPERAND_USING_DEFAULT_SEGMENT0_DEFINED XED_OPERAND_USING_DEFAULT_SEGMENT1_DEFINED XED_OPERAND_VEXDEST3_DEFINED XED_OPERAND_VEXDEST4_DEFINED XED_OPERAND_VEXDEST210_DEFINED XED_OPERAND_VEXVALID_DEFINED XED_OPERAND_VEX_C4_DEFINED XED_OPERAND_VEX_PREFIX_DEFINED XED_OPERAND_VL_DEFINED XED_OPERAND_VL_IGN_DEFINED XED_OPERAND_WBNOINVD_DEFINED XED_OPERAND_WIDTH_A16_DEFINED XED_OPERAND_WIDTH_A32_DEFINED XED_OPERAND_WIDTH_ASZ_DEFINED XED_OPERAND_WIDTH_BND32_DEFINED XED_OPERAND_WIDTH_BND64_DEFINED XED_OPERAND_WIDTH_B_DEFINED XED_OPERAND_WIDTH_DQ_DEFINED XED_OPERAND_WIDTH_D_DEFINED XED_OPERAND_WIDTH_F16_DEFINED XED_OPERAND_WIDTH_F32_DEFINED XED_OPERAND_WIDTH_F64_DEFINED XED_OPERAND_WIDTH_F80_DEFINED XED_OPERAND_WIDTH_I1_DEFINED XED_OPERAND_WIDTH_I2_DEFINED XED_OPERAND_WIDTH_I3_DEFINED XED_OPERAND_WIDTH_I4_DEFINED XED_OPERAND_WIDTH_I5_DEFINED XED_OPERAND_WIDTH_I6_DEFINED XED_OPERAND_WIDTH_I7_DEFINED XED_OPERAND_WIDTH_I8_DEFINED XED_OPERAND_WIDTH_I16_DEFINED XED_OPERAND_WIDTH_I32_DEFINED XED_OPERAND_WIDTH_I64_DEFINED XED_OPERAND_WIDTH_INVALID_DEFINED XED_OPERAND_WIDTH_LAST_DEFINED XED_OPERAND_WIDTH_M64INT_DEFINED XED_OPERAND_WIDTH_M64REAL_DEFINED XED_OPERAND_WIDTH_M384_DEFINED XED_OPERAND_WIDTH_M512_DEFINED XED_OPERAND_WIDTH_MB_DEFINED XED_OPERAND_WIDTH_MD_DEFINED XED_OPERAND_WIDTH_MEM14_DEFINED XED_OPERAND_WIDTH_MEM16INT_DEFINED XED_OPERAND_WIDTH_MEM16_DEFINED XED_OPERAND_WIDTH_MEM28_DEFINED XED_OPERAND_WIDTH_MEM32INT_DEFINED XED_OPERAND_WIDTH_MEM32REAL_DEFINED XED_OPERAND_WIDTH_MEM80DEC_DEFINED XED_OPERAND_WIDTH_MEM80REAL_DEFINED XED_OPERAND_WIDTH_MEM94_DEFINED XED_OPERAND_WIDTH_MEM108_DEFINED XED_OPERAND_WIDTH_MFPXENV_DEFINED XED_OPERAND_WIDTH_MPREFETCH_DEFINED XED_OPERAND_WIDTH_MQ_DEFINED XED_OPERAND_WIDTH_MSKW_DEFINED XED_OPERAND_WIDTH_MW_DEFINED XED_OPERAND_WIDTH_MXSAVE_DEFINED XED_OPERAND_WIDTH_P2_DEFINED XED_OPERAND_WIDTH_PD_DEFINED XED_OPERAND_WIDTH_PI_DEFINED XED_OPERAND_WIDTH_PMMSZ16_DEFINED XED_OPERAND_WIDTH_PMMSZ32_DEFINED XED_OPERAND_WIDTH_PSEUDOX87_DEFINED XED_OPERAND_WIDTH_PSEUDO_DEFINED XED_OPERAND_WIDTH_PS_DEFINED XED_OPERAND_WIDTH_PTR_DEFINED XED_OPERAND_WIDTH_P_DEFINED XED_OPERAND_WIDTH_QQ_DEFINED XED_OPERAND_WIDTH_Q_DEFINED XED_OPERAND_WIDTH_S64_DEFINED XED_OPERAND_WIDTH_SD_DEFINED XED_OPERAND_WIDTH_SI_DEFINED XED_OPERAND_WIDTH_SPW2_DEFINED XED_OPERAND_WIDTH_SPW3_DEFINED XED_OPERAND_WIDTH_SPW5_DEFINED XED_OPERAND_WIDTH_SPW8_DEFINED XED_OPERAND_WIDTH_SPW_DEFINED XED_OPERAND_WIDTH_SSZ_DEFINED XED_OPERAND_WIDTH_SS_DEFINED XED_OPERAND_WIDTH_S_DEFINED XED_OPERAND_WIDTH_TMEMCOL_DEFINED XED_OPERAND_WIDTH_TMEMROW_DEFINED XED_OPERAND_WIDTH_TV_DEFINED XED_OPERAND_WIDTH_U8_DEFINED XED_OPERAND_WIDTH_U16_DEFINED XED_OPERAND_WIDTH_U32_DEFINED XED_OPERAND_WIDTH_U64_DEFINED XED_OPERAND_WIDTH_VAR_DEFINED XED_OPERAND_WIDTH_VV_DEFINED XED_OPERAND_WIDTH_V_DEFINED XED_OPERAND_WIDTH_WRD_DEFINED XED_OPERAND_WIDTH_W_DEFINED XED_OPERAND_WIDTH_X128_DEFINED XED_OPERAND_WIDTH_XB_DEFINED XED_OPERAND_WIDTH_XD_DEFINED XED_OPERAND_WIDTH_XQ_DEFINED XED_OPERAND_WIDTH_XUB_DEFINED XED_OPERAND_WIDTH_XUD_DEFINED XED_OPERAND_WIDTH_XUQ_DEFINED XED_OPERAND_WIDTH_XUW_DEFINED XED_OPERAND_WIDTH_XW_DEFINED XED_OPERAND_WIDTH_Y128_DEFINED XED_OPERAND_WIDTH_YB_DEFINED XED_OPERAND_WIDTH_YD_DEFINED XED_OPERAND_WIDTH_YPD_DEFINED XED_OPERAND_WIDTH_YPS_DEFINED XED_OPERAND_WIDTH_YQ_DEFINED XED_OPERAND_WIDTH_YUB_DEFINED XED_OPERAND_WIDTH_YUD_DEFINED XED_OPERAND_WIDTH_YUQ_DEFINED XED_OPERAND_WIDTH_YUW_DEFINED XED_OPERAND_WIDTH_YU_DEFINED XED_OPERAND_WIDTH_YW_DEFINED XED_OPERAND_WIDTH_Y_DEFINED XED_OPERAND_WIDTH_Z2F16_DEFINED XED_OPERAND_WIDTH_ZBF16_DEFINED XED_OPERAND_WIDTH_ZB_DEFINED XED_OPERAND_WIDTH_ZD0_DEFINED XED_OPERAND_WIDTH_ZD_DEFINED XED_OPERAND_WIDTH_ZF16_DEFINED XED_OPERAND_WIDTH_ZF32_DEFINED XED_OPERAND_WIDTH_ZF64_DEFINED XED_OPERAND_WIDTH_ZI8_DEFINED XED_OPERAND_WIDTH_ZI16_DEFINED XED_OPERAND_WIDTH_ZI32_DEFINED XED_OPERAND_WIDTH_ZI64_DEFINED XED_OPERAND_WIDTH_ZMSKW_DEFINED XED_OPERAND_WIDTH_ZQ_DEFINED XED_OPERAND_WIDTH_ZU8_DEFINED XED_OPERAND_WIDTH_ZU16_DEFINED XED_OPERAND_WIDTH_ZU32_DEFINED XED_OPERAND_WIDTH_ZU64_DEFINED XED_OPERAND_WIDTH_ZU128_DEFINED XED_OPERAND_WIDTH_ZUB_DEFINED XED_OPERAND_WIDTH_ZUD_DEFINED XED_OPERAND_WIDTH_ZUQ_DEFINED XED_OPERAND_WIDTH_ZUW_DEFINED XED_OPERAND_WIDTH_ZV_DEFINED XED_OPERAND_WIDTH_ZW_DEFINED XED_OPERAND_WIDTH_Z_DEFINED XED_OPERAND_XTYPE_2BF16_DEFINED XED_OPERAND_XTYPE_2F16_DEFINED XED_OPERAND_XTYPE_2I16_DEFINED XED_OPERAND_XTYPE_2U16_DEFINED XED_OPERAND_XTYPE_4I8_DEFINED XED_OPERAND_XTYPE_4U8_DEFINED XED_OPERAND_XTYPE_B80_DEFINED XED_OPERAND_XTYPE_BF16_DEFINED XED_OPERAND_XTYPE_F16_DEFINED XED_OPERAND_XTYPE_F32_DEFINED XED_OPERAND_XTYPE_F64_DEFINED XED_OPERAND_XTYPE_F80_DEFINED XED_OPERAND_XTYPE_I1_DEFINED XED_OPERAND_XTYPE_I8_DEFINED XED_OPERAND_XTYPE_I16_DEFINED XED_OPERAND_XTYPE_I32_DEFINED XED_OPERAND_XTYPE_I64_DEFINED XED_OPERAND_XTYPE_I128_DEFINED XED_OPERAND_XTYPE_INT_DEFINED XED_OPERAND_XTYPE_INVALID_DEFINED XED_OPERAND_XTYPE_LAST_DEFINED XED_OPERAND_XTYPE_STRUCT_DEFINED XED_OPERAND_XTYPE_U8_DEFINED XED_OPERAND_XTYPE_U16_DEFINED XED_OPERAND_XTYPE_U32_DEFINED XED_OPERAND_XTYPE_U64_DEFINED XED_OPERAND_XTYPE_U128_DEFINED XED_OPERAND_XTYPE_U256_DEFINED XED_OPERAND_XTYPE_UINT_DEFINED XED_OPERAND_XTYPE_VAR_DEFINED XED_OPERAND_ZEROING_DEFINED XED_OPVIS_EXPLICIT_DEFINED XED_OPVIS_IMPLICIT_DEFINED XED_OPVIS_INVALID_DEFINED XED_OPVIS_LAST_DEFINED XED_OPVIS_SUPPRESSED_DEFINED XED_REG_AH_DEFINED XED_REG_AL_DEFINED XED_REG_AX_DEFINED XED_REG_BH_DEFINED XED_REG_BL_DEFINED XED_REG_BND0_DEFINED XED_REG_BND1_DEFINED XED_REG_BND2_DEFINED XED_REG_BND3_DEFINED XED_REG_BNDCFGU_DEFINED XED_REG_BNDCFG_FIRST_DEFINED XED_REG_BNDCFG_LAST_DEFINED XED_REG_BNDSTATUS_DEFINED XED_REG_BNDSTAT_FIRST_DEFINED XED_REG_BNDSTAT_LAST_DEFINED XED_REG_BOUND_FIRST_DEFINED XED_REG_BOUND_LAST_DEFINED XED_REG_BPL_DEFINED XED_REG_BP_DEFINED XED_REG_BX_DEFINED XED_REG_CH_DEFINED XED_REG_CLASS_BNDCFG_DEFINED XED_REG_CLASS_BNDSTAT_DEFINED XED_REG_CLASS_BOUND_DEFINED XED_REG_CLASS_CR_DEFINED XED_REG_CLASS_DR_DEFINED XED_REG_CLASS_FLAGS_DEFINED XED_REG_CLASS_GPR8_DEFINED XED_REG_CLASS_GPR16_DEFINED XED_REG_CLASS_GPR32_DEFINED XED_REG_CLASS_GPR64_DEFINED XED_REG_CLASS_GPR_DEFINED XED_REG_CLASS_INVALID_DEFINED XED_REG_CLASS_IP_DEFINED XED_REG_CLASS_LAST_DEFINED XED_REG_CLASS_MASK_DEFINED XED_REG_CLASS_MMX_DEFINED XED_REG_CLASS_MSR_DEFINED XED_REG_CLASS_MXCSR_DEFINED XED_REG_CLASS_PSEUDOX87_DEFINED XED_REG_CLASS_PSEUDO_DEFINED XED_REG_CLASS_SR_DEFINED XED_REG_CLASS_TMP_DEFINED XED_REG_CLASS_TREG_DEFINED XED_REG_CLASS_UIF_DEFINED XED_REG_CLASS_X87_DEFINED XED_REG_CLASS_XCR_DEFINED XED_REG_CLASS_XMM_DEFINED XED_REG_CLASS_YMM_DEFINED XED_REG_CLASS_ZMM_DEFINED XED_REG_CL_DEFINED XED_REG_CR0_DEFINED XED_REG_CR1_DEFINED XED_REG_CR2_DEFINED XED_REG_CR3_DEFINED XED_REG_CR4_DEFINED XED_REG_CR5_DEFINED XED_REG_CR6_DEFINED XED_REG_CR7_DEFINED XED_REG_CR8_DEFINED XED_REG_CR9_DEFINED XED_REG_CR10_DEFINED XED_REG_CR11_DEFINED XED_REG_CR12_DEFINED XED_REG_CR13_DEFINED XED_REG_CR14_DEFINED XED_REG_CR15_DEFINED XED_REG_CR_FIRST_DEFINED XED_REG_CR_LAST_DEFINED XED_REG_CS_DEFINED XED_REG_CX_DEFINED XED_REG_DFV0_DEFINED XED_REG_DFV1_DEFINED XED_REG_DFV2_DEFINED XED_REG_DFV3_DEFINED XED_REG_DFV4_DEFINED XED_REG_DFV5_DEFINED XED_REG_DFV6_DEFINED XED_REG_DFV7_DEFINED XED_REG_DFV8_DEFINED XED_REG_DFV9_DEFINED XED_REG_DFV10_DEFINED XED_REG_DFV11_DEFINED XED_REG_DFV12_DEFINED XED_REG_DFV13_DEFINED XED_REG_DFV14_DEFINED XED_REG_DFV15_DEFINED XED_REG_DH_DEFINED XED_REG_DIL_DEFINED XED_REG_DI_DEFINED XED_REG_DL_DEFINED XED_REG_DR0_DEFINED XED_REG_DR1_DEFINED XED_REG_DR2_DEFINED XED_REG_DR3_DEFINED XED_REG_DR4_DEFINED XED_REG_DR5_DEFINED XED_REG_DR6_DEFINED XED_REG_DR7_DEFINED XED_REG_DR_FIRST_DEFINED XED_REG_DR_LAST_DEFINED XED_REG_DS_DEFINED XED_REG_DX_DEFINED XED_REG_EAX_DEFINED XED_REG_EBP_DEFINED XED_REG_EBX_DEFINED XED_REG_ECX_DEFINED XED_REG_EDI_DEFINED XED_REG_EDX_DEFINED XED_REG_EFLAGS_DEFINED XED_REG_EIP_DEFINED XED_REG_ERROR_DEFINED XED_REG_ESI_DEFINED XED_REG_ESP_DEFINED XED_REG_ES_DEFINED XED_REG_FLAGS_DEFINED XED_REG_FLAGS_FIRST_DEFINED XED_REG_FLAGS_LAST_DEFINED XED_REG_FSBASE_DEFINED XED_REG_FS_DEFINED XED_REG_GDTR_DEFINED XED_REG_GPR8_FIRST_DEFINED XED_REG_GPR8_LAST_DEFINED XED_REG_GPR8h_FIRST_DEFINED XED_REG_GPR8h_LAST_DEFINED XED_REG_GPR16_FIRST_DEFINED XED_REG_GPR16_LAST_DEFINED XED_REG_GPR32_FIRST_DEFINED XED_REG_GPR32_LAST_DEFINED XED_REG_GPR64_FIRST_DEFINED XED_REG_GPR64_LAST_DEFINED XED_REG_GSBASE_DEFINED XED_REG_GS_DEFINED XED_REG_IA32_KERNEL_GS_BASE_DEFINED XED_REG_IA32_U_CET_DEFINED XED_REG_IDTR_DEFINED XED_REG_INVALID_DEFINED XED_REG_INVALID_FIRST_DEFINED XED_REG_INVALID_LAST_DEFINED XED_REG_IP_DEFINED XED_REG_IP_FIRST_DEFINED XED_REG_IP_LAST_DEFINED XED_REG_K0_DEFINED XED_REG_K1_DEFINED XED_REG_K2_DEFINED XED_REG_K3_DEFINED XED_REG_K4_DEFINED XED_REG_K5_DEFINED XED_REG_K6_DEFINED XED_REG_K7_DEFINED XED_REG_LAST_DEFINED XED_REG_LDTR_DEFINED XED_REG_MASK_FIRST_DEFINED XED_REG_MASK_LAST_DEFINED XED_REG_MMX0_DEFINED XED_REG_MMX1_DEFINED XED_REG_MMX2_DEFINED XED_REG_MMX3_DEFINED XED_REG_MMX4_DEFINED XED_REG_MMX5_DEFINED XED_REG_MMX6_DEFINED XED_REG_MMX7_DEFINED XED_REG_MMX_FIRST_DEFINED XED_REG_MMX_LAST_DEFINED XED_REG_MSRS_DEFINED XED_REG_MSR_FIRST_DEFINED XED_REG_MSR_LAST_DEFINED XED_REG_MXCSR_DEFINED XED_REG_MXCSR_FIRST_DEFINED XED_REG_MXCSR_LAST_DEFINED XED_REG_PSEUDOX87_FIRST_DEFINED XED_REG_PSEUDOX87_LAST_DEFINED XED_REG_PSEUDO_FIRST_DEFINED XED_REG_PSEUDO_LAST_DEFINED XED_REG_R8B_DEFINED XED_REG_R8D_DEFINED XED_REG_R8W_DEFINED XED_REG_R8_DEFINED XED_REG_R9B_DEFINED XED_REG_R9D_DEFINED XED_REG_R9W_DEFINED XED_REG_R9_DEFINED XED_REG_R10B_DEFINED XED_REG_R10D_DEFINED XED_REG_R10W_DEFINED XED_REG_R10_DEFINED XED_REG_R11B_DEFINED XED_REG_R11D_DEFINED XED_REG_R11W_DEFINED XED_REG_R11_DEFINED XED_REG_R12B_DEFINED XED_REG_R12D_DEFINED XED_REG_R12W_DEFINED XED_REG_R12_DEFINED XED_REG_R13B_DEFINED XED_REG_R13D_DEFINED XED_REG_R13W_DEFINED XED_REG_R13_DEFINED XED_REG_R14B_DEFINED XED_REG_R14D_DEFINED XED_REG_R14W_DEFINED XED_REG_R14_DEFINED XED_REG_R15B_DEFINED XED_REG_R15D_DEFINED XED_REG_R15W_DEFINED XED_REG_R15_DEFINED XED_REG_R16B_DEFINED XED_REG_R16D_DEFINED XED_REG_R16W_DEFINED XED_REG_R16_DEFINED XED_REG_R17B_DEFINED XED_REG_R17D_DEFINED XED_REG_R17W_DEFINED XED_REG_R17_DEFINED XED_REG_R18B_DEFINED XED_REG_R18D_DEFINED XED_REG_R18W_DEFINED XED_REG_R18_DEFINED XED_REG_R19B_DEFINED XED_REG_R19D_DEFINED XED_REG_R19W_DEFINED XED_REG_R19_DEFINED XED_REG_R20B_DEFINED XED_REG_R20D_DEFINED XED_REG_R20W_DEFINED XED_REG_R20_DEFINED XED_REG_R21B_DEFINED XED_REG_R21D_DEFINED XED_REG_R21W_DEFINED XED_REG_R21_DEFINED XED_REG_R22B_DEFINED XED_REG_R22D_DEFINED XED_REG_R22W_DEFINED XED_REG_R22_DEFINED XED_REG_R23B_DEFINED XED_REG_R23D_DEFINED XED_REG_R23W_DEFINED XED_REG_R23_DEFINED XED_REG_R24B_DEFINED XED_REG_R24D_DEFINED XED_REG_R24W_DEFINED XED_REG_R24_DEFINED XED_REG_R25B_DEFINED XED_REG_R25D_DEFINED XED_REG_R25W_DEFINED XED_REG_R25_DEFINED XED_REG_R26B_DEFINED XED_REG_R26D_DEFINED XED_REG_R26W_DEFINED XED_REG_R26_DEFINED XED_REG_R27B_DEFINED XED_REG_R27D_DEFINED XED_REG_R27W_DEFINED XED_REG_R27_DEFINED XED_REG_R28B_DEFINED XED_REG_R28D_DEFINED XED_REG_R28W_DEFINED XED_REG_R28_DEFINED XED_REG_R29B_DEFINED XED_REG_R29D_DEFINED XED_REG_R29W_DEFINED XED_REG_R29_DEFINED XED_REG_R30B_DEFINED XED_REG_R30D_DEFINED XED_REG_R30W_DEFINED XED_REG_R30_DEFINED XED_REG_R31B_DEFINED XED_REG_R31D_DEFINED XED_REG_R31W_DEFINED XED_REG_R31_DEFINED XED_REG_RAX_DEFINED XED_REG_RBP_DEFINED XED_REG_RBX_DEFINED XED_REG_RCX_DEFINED XED_REG_RDI_DEFINED XED_REG_RDX_DEFINED XED_REG_RFLAGS_DEFINED XED_REG_RIP_DEFINED XED_REG_RSI_DEFINED XED_REG_RSP_DEFINED XED_REG_SIL_DEFINED XED_REG_SI_DEFINED XED_REG_SPL_DEFINED XED_REG_SP_DEFINED XED_REG_SR_FIRST_DEFINED XED_REG_SR_LAST_DEFINED XED_REG_SSP_DEFINED XED_REG_SS_DEFINED XED_REG_ST0_DEFINED XED_REG_ST1_DEFINED XED_REG_ST2_DEFINED XED_REG_ST3_DEFINED XED_REG_ST4_DEFINED XED_REG_ST5_DEFINED XED_REG_ST6_DEFINED XED_REG_ST7_DEFINED XED_REG_STACKPOP_DEFINED XED_REG_STACKPUSH_DEFINED XED_REG_TILECONFIG_DEFINED XED_REG_TMM0_DEFINED XED_REG_TMM1_DEFINED XED_REG_TMM2_DEFINED XED_REG_TMM3_DEFINED XED_REG_TMM4_DEFINED XED_REG_TMM5_DEFINED XED_REG_TMM6_DEFINED XED_REG_TMM7_DEFINED XED_REG_TMP0_DEFINED XED_REG_TMP1_DEFINED XED_REG_TMP2_DEFINED XED_REG_TMP3_DEFINED XED_REG_TMP4_DEFINED XED_REG_TMP5_DEFINED XED_REG_TMP6_DEFINED XED_REG_TMP7_DEFINED XED_REG_TMP8_DEFINED XED_REG_TMP9_DEFINED XED_REG_TMP10_DEFINED XED_REG_TMP11_DEFINED XED_REG_TMP12_DEFINED XED_REG_TMP13_DEFINED XED_REG_TMP14_DEFINED XED_REG_TMP15_DEFINED XED_REG_TMP_FIRST_DEFINED XED_REG_TMP_LAST_DEFINED XED_REG_TREG_FIRST_DEFINED XED_REG_TREG_LAST_DEFINED XED_REG_TR_DEFINED XED_REG_TSCAUX_DEFINED XED_REG_TSC_DEFINED XED_REG_UIF_DEFINED XED_REG_UIF_FIRST_DEFINED XED_REG_UIF_LAST_DEFINED XED_REG_X87CONTROL_DEFINED XED_REG_X87LASTCS_DEFINED XED_REG_X87LASTDP_DEFINED XED_REG_X87LASTDS_DEFINED XED_REG_X87LASTIP_DEFINED XED_REG_X87OPCODE_DEFINED XED_REG_X87POP2_DEFINED XED_REG_X87POP_DEFINED XED_REG_X87PUSH_DEFINED XED_REG_X87STATUS_DEFINED XED_REG_X87TAG_DEFINED XED_REG_X87_FIRST_DEFINED XED_REG_X87_LAST_DEFINED XED_REG_XCR0_DEFINED XED_REG_XCR_FIRST_DEFINED XED_REG_XCR_LAST_DEFINED XED_REG_XMM0_DEFINED XED_REG_XMM1_DEFINED XED_REG_XMM2_DEFINED XED_REG_XMM3_DEFINED XED_REG_XMM4_DEFINED XED_REG_XMM5_DEFINED XED_REG_XMM6_DEFINED XED_REG_XMM7_DEFINED XED_REG_XMM8_DEFINED XED_REG_XMM9_DEFINED XED_REG_XMM10_DEFINED XED_REG_XMM11_DEFINED XED_REG_XMM12_DEFINED XED_REG_XMM13_DEFINED XED_REG_XMM14_DEFINED XED_REG_XMM15_DEFINED XED_REG_XMM16_DEFINED XED_REG_XMM17_DEFINED XED_REG_XMM18_DEFINED XED_REG_XMM19_DEFINED XED_REG_XMM20_DEFINED XED_REG_XMM21_DEFINED XED_REG_XMM22_DEFINED XED_REG_XMM23_DEFINED XED_REG_XMM24_DEFINED XED_REG_XMM25_DEFINED XED_REG_XMM26_DEFINED XED_REG_XMM27_DEFINED XED_REG_XMM28_DEFINED XED_REG_XMM29_DEFINED XED_REG_XMM30_DEFINED XED_REG_XMM31_DEFINED XED_REG_XMM_FIRST_DEFINED XED_REG_XMM_LAST_DEFINED XED_REG_YMM0_DEFINED XED_REG_YMM1_DEFINED XED_REG_YMM2_DEFINED XED_REG_YMM3_DEFINED XED_REG_YMM4_DEFINED XED_REG_YMM5_DEFINED XED_REG_YMM6_DEFINED XED_REG_YMM7_DEFINED XED_REG_YMM8_DEFINED XED_REG_YMM9_DEFINED XED_REG_YMM10_DEFINED XED_REG_YMM11_DEFINED XED_REG_YMM12_DEFINED XED_REG_YMM13_DEFINED XED_REG_YMM14_DEFINED XED_REG_YMM15_DEFINED XED_REG_YMM16_DEFINED XED_REG_YMM17_DEFINED XED_REG_YMM18_DEFINED XED_REG_YMM19_DEFINED XED_REG_YMM20_DEFINED XED_REG_YMM21_DEFINED XED_REG_YMM22_DEFINED XED_REG_YMM23_DEFINED XED_REG_YMM24_DEFINED XED_REG_YMM25_DEFINED XED_REG_YMM26_DEFINED XED_REG_YMM27_DEFINED XED_REG_YMM28_DEFINED XED_REG_YMM29_DEFINED XED_REG_YMM30_DEFINED XED_REG_YMM31_DEFINED XED_REG_YMM_FIRST_DEFINED XED_REG_YMM_LAST_DEFINED XED_REG_ZMM0_DEFINED XED_REG_ZMM1_DEFINED XED_REG_ZMM2_DEFINED XED_REG_ZMM3_DEFINED XED_REG_ZMM4_DEFINED XED_REG_ZMM5_DEFINED XED_REG_ZMM6_DEFINED XED_REG_ZMM7_DEFINED XED_REG_ZMM8_DEFINED XED_REG_ZMM9_DEFINED XED_REG_ZMM10_DEFINED XED_REG_ZMM11_DEFINED XED_REG_ZMM12_DEFINED XED_REG_ZMM13_DEFINED XED_REG_ZMM14_DEFINED XED_REG_ZMM15_DEFINED XED_REG_ZMM16_DEFINED XED_REG_ZMM17_DEFINED XED_REG_ZMM18_DEFINED XED_REG_ZMM19_DEFINED XED_REG_ZMM20_DEFINED XED_REG_ZMM21_DEFINED XED_REG_ZMM22_DEFINED XED_REG_ZMM23_DEFINED XED_REG_ZMM24_DEFINED XED_REG_ZMM25_DEFINED XED_REG_ZMM26_DEFINED XED_REG_ZMM27_DEFINED XED_REG_ZMM28_DEFINED XED_REG_ZMM29_DEFINED XED_REG_ZMM30_DEFINED XED_REG_ZMM31_DEFINED XED_REG_ZMM_FIRST_DEFINED XED_REG_ZMM_LAST_DEFINED XED_SYNTAX_ATT_DEFINED XED_SYNTAX_INTEL_DEFINED XED_SYNTAX_INVALID_DEFINED XED_SYNTAX_LAST_DEFINED XED_SYNTAX_XED_DEFINED XED_VERBOSE XED_VERSION XED_VERY_VERBOSE _ATFILE_SOURCE _BITS_STDINT_INTN_H _BITS_STDINT_LEAST_H _BITS_STDINT_UINTN_H _BITS_TIME64_H _BITS_TYPESIZES_H _BITS_TYPES_H _BITS_WCHAR_H _DEFAULT_SOURCE _FEATURES_H _POSIX_C_SOURCE _POSIX_SOURCE _STDC_PREDEF_H _STDINT_H _SYS_CDEFS_H __FD_SETSIZE __GLIBC_MINOR__ __GLIBC_USE_C2X_STRTOL __GLIBC_USE_DEPRECATED_GETS __GLIBC_USE_DEPRECATED_SCANF __GLIBC_USE_IEC_60559_BFP_EXT __GLIBC_USE_IEC_60559_BFP_EXT_C2X __GLIBC_USE_IEC_60559_EXT __GLIBC_USE_IEC_60559_FUNCS_EXT __GLIBC_USE_IEC_60559_FUNCS_EXT_C2X __GLIBC_USE_IEC_60559_TYPES_EXT __GLIBC_USE_ISOC2X __GLIBC_USE_LIB_EXT2 __GLIBC__ __GNU_LIBRARY__ __HAVE_GENERIC_SELECTION __INO_T_MATCHES_INO64_T __KERNEL_OLD_TIMEVAL_MATCHES_TIMEVAL64 __LDOUBLE_REDIRECTS_TO_FLOAT128_ABI __OFF_T_MATCHES_OFF64_T __RLIM_T_MATCHES_RLIM64_T __STATFS_MATCHES_STATFS64 __STDC_IEC_559_COMPLEX__ __STDC_IEC_559__ __STDC_IEC_60559_BFP__ __STDC_IEC_60559_COMPLEX__ __STDC_ISO_10646__ __SYSCALL_WORDSIZE __TIMESIZE __USE_ATFILE __USE_FORTIFY_LEVEL __USE_ISOC11 __USE_ISOC95 __USE_ISOC99 __USE_MISC __USE_POSIX __USE_POSIX2 __USE_POSIX199309 __USE_POSIX199506 __USE_POSIX_IMPLICITLY __USE_XOPEN2K __USE_XOPEN2K8 __WORDSIZE __WORDSIZE_TIME64_COMPAT32 __glibc_c99_flexarr_available xed_verbose ⚠ str2xed_address_width_enum_t ⚠ This converts strings to #xed_address_width_enum_t types.
@param s A C-string.
@return #xed_address_width_enum_t
@ingroup ENUM str2xed_attribute_enum_t ⚠ This converts strings to #xed_attribute_enum_t types.
@param s A C-string.
@return #xed_attribute_enum_t
@ingroup ENUM str2xed_category_enum_t ⚠ This converts strings to #xed_category_enum_t types.
@param s A C-string.
@return #xed_category_enum_t
@ingroup ENUM str2xed_chip_enum_t ⚠ This converts strings to #xed_chip_enum_t types.
@param s A C-string.
@return #xed_chip_enum_t
@ingroup ENUM str2xed_cpuid_group_enum_t ⚠ This converts strings to #xed_cpuid_group_enum_t types.
@param s A C-string.
@return #xed_cpuid_group_enum_t
@ingroup ENUM str2xed_cpuid_rec_enum_t ⚠ This converts strings to #xed_cpuid_rec_enum_t types.
@param s A C-string.
@return #xed_cpuid_rec_enum_t
@ingroup ENUM str2xed_error_enum_t ⚠ This converts strings to #xed_error_enum_t types.
@param s A C-string.
@return #xed_error_enum_t
@ingroup ENUM str2xed_exception_enum_t ⚠ This converts strings to #xed_exception_enum_t types.
@param s A C-string.
@return #xed_exception_enum_t
@ingroup ENUM str2xed_extension_enum_t ⚠ This converts strings to #xed_extension_enum_t types.
@param s A C-string.
@return #xed_extension_enum_t
@ingroup ENUM str2xed_flag_action_enum_t ⚠ This converts strings to #xed_flag_action_enum_t types.
@param s A C-string.
@return #xed_flag_action_enum_t
@ingroup ENUM str2xed_flag_enum_t ⚠ This converts strings to #xed_flag_enum_t types.
@param s A C-string.
@return #xed_flag_enum_t
@ingroup ENUM str2xed_iclass_enum_t ⚠ This converts strings to #xed_iclass_enum_t types.
@param s A C-string.
@return #xed_iclass_enum_t
@ingroup ENUM str2xed_iform_enum_t ⚠ This converts strings to #xed_iform_enum_t types.
@param s A C-string.
@return #xed_iform_enum_t
@ingroup ENUM str2xed_isa_set_enum_t ⚠ This converts strings to #xed_isa_set_enum_t types.
@param s A C-string.
@return #xed_isa_set_enum_t
@ingroup ENUM str2xed_machine_mode_enum_t ⚠ This converts strings to #xed_machine_mode_enum_t types.
@param s A C-string.
@return #xed_machine_mode_enum_t
@ingroup ENUM str2xed_nonterminal_enum_t ⚠ This converts strings to #xed_nonterminal_enum_t types.
@param s A C-string.
@return #xed_nonterminal_enum_t
@ingroup ENUM str2xed_operand_action_enum_t ⚠ This converts strings to #xed_operand_action_enum_t types.
@param s A C-string.
@return #xed_operand_action_enum_t
@ingroup ENUM str2xed_operand_convert_enum_t ⚠ This converts strings to #xed_operand_convert_enum_t types.
@param s A C-string.
@return #xed_operand_convert_enum_t
@ingroup ENUM str2xed_operand_element_type_enum_t ⚠ This converts strings to #xed_operand_element_type_enum_t types.
@param s A C-string.
@return #xed_operand_element_type_enum_t
@ingroup ENUM str2xed_operand_element_xtype_enum_t ⚠ This converts strings to #xed_operand_element_xtype_enum_t types.
@param s A C-string.
@return #xed_operand_element_xtype_enum_t
@ingroup ENUM str2xed_operand_enum_t ⚠ This converts strings to #xed_operand_enum_t types.
@param s A C-string.
@return #xed_operand_enum_t
@ingroup ENUM str2xed_operand_type_enum_t ⚠ This converts strings to #xed_operand_type_enum_t types.
@param s A C-string.
@return #xed_operand_type_enum_t
@ingroup ENUM str2xed_operand_visibility_enum_t ⚠ This converts strings to #xed_operand_visibility_enum_t types.
@param s A C-string.
@return #xed_operand_visibility_enum_t
@ingroup ENUM str2xed_operand_width_enum_t ⚠ This converts strings to #xed_operand_width_enum_t types.
@param s A C-string.
@return #xed_operand_width_enum_t
@ingroup ENUM str2xed_reg_class_enum_t ⚠ This converts strings to #xed_reg_class_enum_t types.
@param s A C-string.
@return #xed_reg_class_enum_t
@ingroup ENUM str2xed_reg_enum_t ⚠ This converts strings to #xed_reg_enum_t types.
@param s A C-string.
@return #xed_reg_enum_t
@ingroup ENUM str2xed_syntax_enum_t ⚠ This converts strings to #xed_syntax_enum_t types.
@param s A C-string.
@return #xed_syntax_enum_t
@ingroup ENUM xed3_get_generic_operand ⚠ xed3_operand_get_absbr ⚠ xed3_operand_get_agen ⚠ xed3_operand_get_amd3dnow ⚠ xed3_operand_get_asz ⚠ xed3_operand_get_base0 ⚠ xed3_operand_get_base1 ⚠ xed3_operand_get_bcast ⚠ xed3_operand_get_bcrc ⚠ xed3_operand_get_brdisp_width ⚠ xed3_operand_get_cet ⚠ xed3_operand_get_chip ⚠ xed3_operand_get_cldemote ⚠ xed3_operand_get_default_seg ⚠ xed3_operand_get_df32 ⚠ xed3_operand_get_df64 ⚠ xed3_operand_get_disp ⚠ xed3_operand_get_disp_width ⚠ xed3_operand_get_dummy ⚠ xed3_operand_get_easz ⚠ xed3_operand_get_element_size ⚠ xed3_operand_get_encode_force ⚠ xed3_operand_get_encoder_preferred ⚠ xed3_operand_get_eosz ⚠ xed3_operand_get_error ⚠ xed3_operand_get_esrc ⚠ xed3_operand_get_evvspace ⚠ xed3_operand_get_first_f2f3 ⚠ xed3_operand_get_has_egpr ⚠ xed3_operand_get_has_modrm ⚠ xed3_operand_get_has_sib ⚠ xed3_operand_get_hint ⚠ xed3_operand_get_iclass ⚠ xed3_operand_get_ild_f2 ⚠ xed3_operand_get_ild_f3 ⚠ xed3_operand_get_ild_seg ⚠ xed3_operand_get_imm0 ⚠ xed3_operand_get_imm0signed ⚠ xed3_operand_get_imm1 ⚠ xed3_operand_get_imm1_bytes ⚠ xed3_operand_get_imm_width ⚠ xed3_operand_get_index ⚠ xed3_operand_get_last_f2f3 ⚠ xed3_operand_get_llrc ⚠ xed3_operand_get_lock ⚠ xed3_operand_get_lzcnt ⚠ xed3_operand_get_map ⚠ xed3_operand_get_mask ⚠ xed3_operand_get_max_bytes ⚠ xed3_operand_get_mem0 ⚠ xed3_operand_get_mem1 ⚠ xed3_operand_get_mem_width ⚠ xed3_operand_get_mod ⚠ xed3_operand_get_mode ⚠ xed3_operand_get_mode_first_prefix ⚠ xed3_operand_get_mode_short_ud0 ⚠ xed3_operand_get_modep5 ⚠ xed3_operand_get_modep55c ⚠ xed3_operand_get_modrm_byte ⚠ xed3_operand_get_mpxmode ⚠ xed3_operand_get_must_use_evex ⚠ xed3_operand_get_nd ⚠ xed3_operand_get_need_memdisp ⚠ xed3_operand_get_need_sib ⚠ xed3_operand_get_needrex ⚠ xed3_operand_get_nelem ⚠ xed3_operand_get_nf ⚠ xed3_operand_get_no_apx ⚠ xed3_operand_get_no_evex ⚠ xed3_operand_get_no_vex ⚠ xed3_operand_get_nominal_opcode ⚠ xed3_operand_get_norex ⚠ xed3_operand_get_nprefixes ⚠ xed3_operand_get_nrexes ⚠ xed3_operand_get_nseg_prefixes ⚠ xed3_operand_get_osz ⚠ xed3_operand_get_out_of_bytes ⚠ xed3_operand_get_outreg ⚠ xed3_operand_get_p4 ⚠ xed3_operand_get_pos_disp ⚠ xed3_operand_get_pos_imm ⚠ xed3_operand_get_pos_imm1 ⚠ xed3_operand_get_pos_modrm ⚠ xed3_operand_get_pos_nominal_opcode ⚠ xed3_operand_get_pos_sib ⚠ xed3_operand_get_prefix66 ⚠ xed3_operand_get_ptr ⚠ xed3_operand_get_realmode ⚠ xed3_operand_get_reg ⚠ xed3_operand_get_reg0 ⚠ xed3_operand_get_reg1 ⚠ xed3_operand_get_reg2 ⚠ xed3_operand_get_reg3 ⚠ xed3_operand_get_reg4 ⚠ xed3_operand_get_reg5 ⚠ xed3_operand_get_reg6 ⚠ xed3_operand_get_reg7 ⚠ xed3_operand_get_reg8 ⚠ xed3_operand_get_reg9 ⚠ xed3_operand_get_relbr ⚠ xed3_operand_get_rep ⚠ xed3_operand_get_rex ⚠ xed3_operand_get_rex2 ⚠ xed3_operand_get_rexb ⚠ xed3_operand_get_rexb4 ⚠ xed3_operand_get_rexr ⚠ xed3_operand_get_rexr4 ⚠ xed3_operand_get_rexw ⚠ xed3_operand_get_rexx ⚠ xed3_operand_get_rexx4 ⚠ xed3_operand_get_rm ⚠ xed3_operand_get_roundc ⚠ xed3_operand_get_sae ⚠ xed3_operand_get_scale ⚠ xed3_operand_get_scc ⚠ xed3_operand_get_seg0 ⚠ xed3_operand_get_seg1 ⚠ xed3_operand_get_seg_ovd ⚠ xed3_operand_get_sibbase ⚠ xed3_operand_get_sibindex ⚠ xed3_operand_get_sibscale ⚠ xed3_operand_get_skip_osz ⚠ xed3_operand_get_smode ⚠ xed3_operand_get_srm ⚠ xed3_operand_get_tzcnt ⚠ xed3_operand_get_ubit ⚠ xed3_operand_get_uimm0 ⚠ xed3_operand_get_uimm1 ⚠ xed3_operand_get_using_default_segment0 ⚠ xed3_operand_get_using_default_segment1 ⚠ xed3_operand_get_vex_c4 ⚠ xed3_operand_get_vex_prefix ⚠ xed3_operand_get_vexdest3 ⚠ xed3_operand_get_vexdest4 ⚠ xed3_operand_get_vexdest210 ⚠ xed3_operand_get_vexvalid ⚠ xed3_operand_get_vl ⚠ xed3_operand_get_vl_ign ⚠ xed3_operand_get_wbnoinvd ⚠ xed3_operand_get_zeroing ⚠ xed3_operand_set_absbr ⚠ xed3_operand_set_agen ⚠ xed3_operand_set_amd3dnow ⚠ xed3_operand_set_asz ⚠ xed3_operand_set_base0 ⚠ xed3_operand_set_base1 ⚠ xed3_operand_set_bcast ⚠ xed3_operand_set_bcrc ⚠ xed3_operand_set_brdisp_width ⚠ xed3_operand_set_cet ⚠ xed3_operand_set_chip ⚠ xed3_operand_set_cldemote ⚠ xed3_operand_set_default_seg ⚠ xed3_operand_set_df32 ⚠ xed3_operand_set_df64 ⚠ xed3_operand_set_disp ⚠ xed3_operand_set_disp_width ⚠ xed3_operand_set_dummy ⚠ xed3_operand_set_easz ⚠ xed3_operand_set_element_size ⚠ xed3_operand_set_encode_force ⚠ xed3_operand_set_encoder_preferred ⚠ xed3_operand_set_eosz ⚠ xed3_operand_set_error ⚠ xed3_operand_set_esrc ⚠ xed3_operand_set_evvspace ⚠ xed3_operand_set_first_f2f3 ⚠ xed3_operand_set_has_egpr ⚠ xed3_operand_set_has_modrm ⚠ xed3_operand_set_has_sib ⚠ xed3_operand_set_hint ⚠ xed3_operand_set_iclass ⚠ xed3_operand_set_ild_f2 ⚠ xed3_operand_set_ild_f3 ⚠ xed3_operand_set_ild_seg ⚠ xed3_operand_set_imm0 ⚠ xed3_operand_set_imm0signed ⚠ xed3_operand_set_imm1 ⚠ xed3_operand_set_imm1_bytes ⚠ xed3_operand_set_imm_width ⚠ xed3_operand_set_index ⚠ xed3_operand_set_last_f2f3 ⚠ xed3_operand_set_llrc ⚠ xed3_operand_set_lock ⚠ xed3_operand_set_lzcnt ⚠ xed3_operand_set_map ⚠ xed3_operand_set_mask ⚠ xed3_operand_set_max_bytes ⚠ xed3_operand_set_mem0 ⚠ xed3_operand_set_mem1 ⚠ xed3_operand_set_mem_width ⚠ xed3_operand_set_mod ⚠ xed3_operand_set_mode ⚠ xed3_operand_set_mode_first_prefix ⚠ xed3_operand_set_mode_short_ud0 ⚠ xed3_operand_set_modep5 ⚠ xed3_operand_set_modep55c ⚠ xed3_operand_set_modrm_byte ⚠ xed3_operand_set_mpxmode ⚠ xed3_operand_set_must_use_evex ⚠ xed3_operand_set_nd ⚠ xed3_operand_set_need_memdisp ⚠ xed3_operand_set_need_sib ⚠ xed3_operand_set_needrex ⚠ xed3_operand_set_nelem ⚠ xed3_operand_set_nf ⚠ xed3_operand_set_no_apx ⚠ xed3_operand_set_no_evex ⚠ xed3_operand_set_no_vex ⚠ xed3_operand_set_nominal_opcode ⚠ xed3_operand_set_norex ⚠ xed3_operand_set_nprefixes ⚠ xed3_operand_set_nrexes ⚠ xed3_operand_set_nseg_prefixes ⚠ xed3_operand_set_osz ⚠ xed3_operand_set_out_of_bytes ⚠ xed3_operand_set_outreg ⚠ xed3_operand_set_p4 ⚠ xed3_operand_set_pos_disp ⚠ xed3_operand_set_pos_imm ⚠ xed3_operand_set_pos_imm1 ⚠ xed3_operand_set_pos_modrm ⚠ xed3_operand_set_pos_nominal_opcode ⚠ xed3_operand_set_pos_sib ⚠ xed3_operand_set_prefix66 ⚠ xed3_operand_set_ptr ⚠ xed3_operand_set_realmode ⚠ xed3_operand_set_reg ⚠ xed3_operand_set_reg0 ⚠ xed3_operand_set_reg1 ⚠ xed3_operand_set_reg2 ⚠ xed3_operand_set_reg3 ⚠ xed3_operand_set_reg4 ⚠ xed3_operand_set_reg5 ⚠ xed3_operand_set_reg6 ⚠ xed3_operand_set_reg7 ⚠ xed3_operand_set_reg8 ⚠ xed3_operand_set_reg9 ⚠ xed3_operand_set_relbr ⚠ xed3_operand_set_rep ⚠ xed3_operand_set_rex ⚠ xed3_operand_set_rex2 ⚠ xed3_operand_set_rexb ⚠ xed3_operand_set_rexb4 ⚠ xed3_operand_set_rexr ⚠ xed3_operand_set_rexr4 ⚠ xed3_operand_set_rexw ⚠ xed3_operand_set_rexx ⚠ xed3_operand_set_rexx4 ⚠ xed3_operand_set_rm ⚠ xed3_operand_set_roundc ⚠ xed3_operand_set_sae ⚠ xed3_operand_set_scale ⚠ xed3_operand_set_scc ⚠ xed3_operand_set_seg0 ⚠ xed3_operand_set_seg1 ⚠ xed3_operand_set_seg_ovd ⚠ xed3_operand_set_sibbase ⚠ xed3_operand_set_sibindex ⚠ xed3_operand_set_sibscale ⚠ xed3_operand_set_skip_osz ⚠ xed3_operand_set_smode ⚠ xed3_operand_set_srm ⚠ xed3_operand_set_tzcnt ⚠ xed3_operand_set_ubit ⚠ xed3_operand_set_uimm0 ⚠ xed3_operand_set_uimm1 ⚠ xed3_operand_set_using_default_segment0 ⚠ xed3_operand_set_using_default_segment1 ⚠ xed3_operand_set_vex_c4 ⚠ xed3_operand_set_vex_prefix ⚠ xed3_operand_set_vexdest3 ⚠ xed3_operand_set_vexdest4 ⚠ xed3_operand_set_vexdest210 ⚠ xed3_operand_set_vexvalid ⚠ xed3_operand_set_vl ⚠ xed3_operand_set_vl_ign ⚠ xed3_operand_set_wbnoinvd ⚠ xed3_operand_set_zeroing ⚠ xed3_set_generic_operand ⚠ xed_absbr ⚠ @ingroup ENCHL
an absolute branch displacement operand
@param brdisp The branch displacement
@param width_bits The width of the displacement in bits.
@returns xed_encoder_operand_t An operand. xed_addr ⚠ @ingroup ENCHL
This is to specify effective address size different than the
default. For things with base or index regs, XED picks it up from the
registers. But for things that have implicit memops, or no base or index
reg, we must allow the user to set the address width directly.
@param x The #xed_encoder_instruction_t being filled in.
@param width_bits The intended effective address size in bits. Values: 16, 32 or 64. xed_address_width_enum_t2str ⚠ This converts strings to #xed_address_width_enum_t types.
@param p An enumeration element of type xed_address_width_enum_t.
@return string
@ingroup ENUM xed_address_width_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_address_width_enum_t The last element of the enumeration.
@ingroup ENUM xed_agen ⚠ Using the registered callbacks, compute the memory address for a
specified memop in a decoded instruction. memop_index can have the
value 0 for XED_OPERAND_MEM0, XED_OPERAND_AGEN, or 1 for
XED_OPERAND_MEM1. Any other value results in an error being
returned. The context parameter which is passed to the registered
callbacks can be used to identify which thread’s state is being
referenced. The context parameter can also be used to specify which
element of a vector register should be returned for gather an scatter
operations.
@ingroup AGEN xed_agen_register_callback ⚠ Initialize the callback functions. Tell XED what to call when using
#xed_agen.
@ingroup AGEN xed_attribute ⚠ @ingroup DEC
Return the i’th global attribute in a linear sequence, independent of
any instruction. This is used for scanning and printing all attributes. xed_attribute_enum_t2str ⚠ This converts strings to #xed_attribute_enum_t types.
@param p An enumeration element of type xed_attribute_enum_t.
@return string
@ingroup ENUM xed_attribute_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_attribute_enum_t The last element of the enumeration.
@ingroup ENUM xed_attribute_max ⚠ @ingroup DEC
Return the maximum number of defined attributes, independent of any
instruction. xed_category_enum_t2str ⚠ This converts strings to #xed_category_enum_t types.
@param p An enumeration element of type xed_category_enum_t.
@return string
@ingroup ENUM xed_category_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_category_enum_t The last element of the enumeration.
@ingroup ENUM xed_chip_enum_t2str ⚠ This converts strings to #xed_chip_enum_t types.
@param p An enumeration element of type xed_chip_enum_t.
@return string
@ingroup ENUM xed_chip_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_chip_enum_t The last element of the enumeration.
@ingroup ENUM xed_classify_amx ⚠ @ingroup DEC
True for AMX instructions xed_classify_apx ⚠ @ingroup DEC
True for APX instructions, includes instructions with EGPRs, REX2 and
encodings that are treated as illegal on non-APX systems xed_classify_avx ⚠ @ingroup DEC
True for AVX/AVX2 SIMD VEX-encoded operations. Does not include BMI/BMI2 instructions. xed_classify_avx512 ⚠ @ingroup DEC
True for AVX512 (EVEX-encoded) SIMD and (VEX encoded) K-mask instructions xed_classify_avx512_maskop ⚠ @ingroup DEC
True for AVX512 (VEX-encoded) K-mask operations xed_classify_sse ⚠ @ingroup DEC
True for SSE/SSE2/etc. SIMD operations. Includes AES and PCLMULQDQ xed_convert_to_encoder_request ⚠ @ingroup ENCHL
convert a #xed_encoder_instruction_t to a #xed_encoder_request_t for
encoding xed_cpuid_group_enum_t2str ⚠ This converts strings to #xed_cpuid_group_enum_t types.
@param p An enumeration element of type xed_cpuid_group_enum_t.
@return string
@ingroup ENUM xed_cpuid_group_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_cpuid_group_enum_t The last element of the enumeration.
@ingroup ENUM xed_cpuid_rec_enum_t2str ⚠ This converts strings to #xed_cpuid_rec_enum_t types.
@param p An enumeration element of type xed_cpuid_rec_enum_t.
@return string
@ingroup ENUM xed_cpuid_rec_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_cpuid_rec_enum_t The last element of the enumeration.
@ingroup ENUM xed_decode ⚠ This is the main interface to the decoder.
@param xedd the decoded instruction of type #xed_decoded_inst_t . Mode/state sent in via xedd; See the #xed_state_t
@param itext the pointer to the array of instruction text bytes
@param bytes the length of the itext input array. 1 to 15 bytes, anything more is ignored.
@return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or failure. Note failure can be due to not
enough bytes in the input array. xed_decode_with_features ⚠ @ingroup DEC
See #xed_decode(). This version of the decode API adds a CPUID feature
vector to support restricting decode based on both a specified chip via
#xed_decoded_inst_set_input_chip() and a modify-able cpuid feature
vector obtained from #xed_get_chip_features(). xed_decoded_inst_avx512_dest_elements ⚠ Returns the maximum number elements processed for an AVX512 vector
instruction. Scalars report 1 element.
@ingroup DEC xed_decoded_inst_conditionally_writes_registers ⚠ @ingroup DEC xed_decoded_inst_dump ⚠ @ingroup PRINT
Print out all the information about the decoded instruction to the
buffer buf whose length is maximally buflen. This is for debugging. xed_decoded_inst_dump_xed_format ⚠ @ingroup PRINT
Print the instruction information in a verbose format.
This is for debugging.
@param p a #xed_decoded_inst_t for a decoded instruction
@param buf a buffer to write the disassembly in to.
@param buflen maximum length of the disassembly buffer
@param runtime_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches.
@return Returns 0 if the disassembly fails, 1 otherwise. xed_decoded_inst_get_attribute ⚠ @ingroup DEC
Returns 1 if the attribute is defined for this instruction. xed_decoded_inst_get_attributes ⚠ @ingroup DEC
Returns the attribute bitvector xed_decoded_inst_get_base_reg ⚠ @ingroup DEC xed_decoded_inst_get_branch_displacement ⚠ @ingroup DEC xed_decoded_inst_get_branch_displacement_width ⚠ @ingroup DEC
Result in BYTES xed_decoded_inst_get_branch_displacement_width_bits ⚠ @ingroup DEC
Result in BITS xed_decoded_inst_get_byte ⚠ @ingroup DEC
Read itext byte. xed_decoded_inst_get_category ⚠ @ingroup DEC
Return the instruction #xed_category_enum_t enumeration xed_decoded_inst_get_extension ⚠ @ingroup DEC
Return the instruction #xed_extension_enum_t enumeration xed_decoded_inst_get_iclass ⚠ @ingroup DEC
Return the instruction #xed_iclass_enum_t enumeration. xed_decoded_inst_get_iform_enum ⚠ @ingroup DEC
Return the instruction iform enum of type #xed_iform_enum_t . xed_decoded_inst_get_iform_enum_dispatch ⚠ @ingroup DEC
Return the instruction zero-based iform number based on masking the
corresponding #xed_iform_enum_t. This value is suitable for
dispatching. The maximum value for a particular iclass is provided by
#xed_iform_max_per_iclass() . xed_decoded_inst_get_immediate_is_signed ⚠ @ingroup DEC
Return true if the first immediate (IMM0) is signed xed_decoded_inst_get_immediate_width ⚠ @ingroup DEC
Return the immediate width in BYTES. xed_decoded_inst_get_immediate_width_bits ⚠ @ingroup DEC
Return the immediate width in BITS. xed_decoded_inst_get_index_reg ⚠ xed_decoded_inst_get_input_chip ⚠ Return the user-specified #xed_chip_enum_t chip name, or
XED_CHIP_INVALID if not set.
@ingroup DEC xed_decoded_inst_get_isa_set ⚠ @ingroup DEC
Return the instruction #xed_isa_set_enum_t enumeration xed_decoded_inst_get_length ⚠ @ingroup DEC
Return the length of the decoded instruction in bytes. xed_decoded_inst_get_machine_mode_bits ⚠ @ingroup DEC
Returns 16/32/64 indicating the machine mode with in bits. This is
derived from the input mode information. xed_decoded_inst_get_memop_address_width ⚠ @ingroup DEC xed_decoded_inst_get_memory_displacement ⚠ @ingroup DEC xed_decoded_inst_get_memory_displacement_width ⚠ @ingroup DEC
Result in BYTES xed_decoded_inst_get_memory_displacement_width_bits ⚠ @ingroup DEC
Result in BITS xed_decoded_inst_get_memory_operand_length ⚠ returns bytes
@ingroup DEC xed_decoded_inst_get_modrm ⚠ @ingroup DEC
Returns the modrm byte xed_decoded_inst_get_nprefixes ⚠ @ingroup DEC
Returns the number of legacy prefixes. xed_decoded_inst_get_operand_width ⚠ Returns the operand width in bits: 8/16/32/64. This is different than
the #xed_operand_values_get_effective_operand_width() which only
returns 16/32/64. This factors in the BYTEOP attribute when computing
its return value. This function provides a information for that is only
useful for (scalable) GPR-operations. Individual operands have more
specific information available from
#xed_decoded_inst_operand_element_size_bits()
@ingroup DEC xed_decoded_inst_get_reg ⚠ @ingroup DEC
Return the specified register operand. The specifier is of type
#xed_operand_enum_t . xed_decoded_inst_get_rflags_info ⚠ See the comment on xed_decoded_inst_uses_rflags(). This can return
0 if the flags are really not used by this instruction.
@ingroup DEC xed_decoded_inst_get_scale ⚠ @ingroup DEC xed_decoded_inst_get_second_immediate ⚠ @ingroup DEC
Return the second immediate. xed_decoded_inst_get_seg_reg ⚠ @ingroup DEC xed_decoded_inst_get_signed_immediate ⚠ @ingroup DEC xed_decoded_inst_get_stack_address_mode_bits ⚠ @ingroup DEC
Returns 16/32/64 indicating the stack addressing mode with in
bits. This is derived from the input mode information. xed_decoded_inst_get_unsigned_immediate ⚠ @ingroup DEC xed_decoded_inst_get_user_data ⚠ @ingroup DEC
Return a user data field for arbitrary use by the user after decoding. xed_decoded_inst_has_mpx_prefix ⚠ @ingroup DEC
Returns 1 if the instruction has mpx prefix. xed_decoded_inst_inst ⚠ @ingroup DEC
Return the #xed_inst_t structure for this instruction. This is the
route to the basic operands form information. xed_decoded_inst_is_apx_zu ⚠ @ingroup DEC xed_decoded_inst_is_broadcast ⚠ @ingroup DEC
Return 1 for broadcast instructions or AVX512 load-op instructions using the broadcast feature
0 otherwise. Logical OR of
#xed_decoded_inst_is_broadcast_instruction() and
#xed_decoded_inst_uses_embedded_broadcast(). xed_decoded_inst_is_broadcast_instruction ⚠ @ingroup DEC
Return 1 for broadcast instruction. (NOT including AVX512 load-op instructions)
0 otherwise. Just a category check. xed_decoded_inst_is_prefetch ⚠ @ingroup DEC
Returns true if the instruction is a prefetch xed_decoded_inst_is_xacquire ⚠ @ingroup DEC
Returns 1 if the instruction is xacquire. xed_decoded_inst_is_xrelease ⚠ @ingroup DEC
Returns 1 if the instruction is xrelease. xed_decoded_inst_masked_vector_operation ⚠ @ingroup DEC
Returns 1 iff the instruction uses destination-masking. This is 0 for
blend operations that use their mask field as a control. xed_decoded_inst_masking ⚠ Returns true if the instruction uses write-masking
@ingroup DEC xed_decoded_inst_mem_read ⚠ @ingroup DEC xed_decoded_inst_mem_written ⚠ @ingroup DEC xed_decoded_inst_mem_written_only ⚠ @ingroup DEC xed_decoded_inst_merging ⚠ Returns true if the instruction uses write-masking with merging
@ingroup DEC xed_decoded_inst_noperands ⚠ Return the number of operands
@ingroup DEC xed_decoded_inst_number_of_memory_operands ⚠ @ingroup DEC xed_decoded_inst_operand_action ⚠ Interpret the operand action in light of AVX512 masking and
zeroing/merging. If masking and merging are used together, the dest
operand may also be read. If masking and merging are used together,
the elemnents of dest operand register may be conditionally written (so
that input values live on in the output register).
@ingroup DEC xed_decoded_inst_operand_element_size_bits ⚠ Return the size of an element in bits (for SSE and AVX operands)
@ingroup DEC xed_decoded_inst_operand_element_type ⚠ Return the type of an element of type #xed_operand_element_type_enum_t
(for SSE and AVX operands)
@ingroup DEC xed_decoded_inst_operand_elements ⚠ Return the number of element in the operand (for SSE and AVX operands)
@ingroup DEC xed_decoded_inst_operand_length ⚠ Deprecated – returns the length in bytes of the operand_index’th
operand. Use #xed_decoded_inst_operand_length_bits() instead.
@ingroup DEC xed_decoded_inst_operand_length_bits ⚠ Return the length in bits of the operand_index’th operand.
@ingroup DEC xed_decoded_inst_operands ⚠ @ingroup DEC
Obtain a non-constant pointer to the operands xed_decoded_inst_operands_const ⚠ @ingroup DEC
Obtain a constant pointer to the operands xed_decoded_inst_set_branch_displacement ⚠ @ingroup DEC
Set the branch displacement using a BYTE length xed_decoded_inst_set_branch_displacement_bits ⚠ @ingroup DEC
Set the branch displacement a BITS length xed_decoded_inst_set_immediate_signed ⚠ @ingroup DEC
Set the signed immediate a BYTE length xed_decoded_inst_set_immediate_signed_bits ⚠ @ingroup DEC
Set the signed immediate a BITS length xed_decoded_inst_set_immediate_unsigned ⚠ @ingroup DEC
Set the unsigned immediate a BYTE length xed_decoded_inst_set_immediate_unsigned_bits ⚠ @ingroup DEC
Set the unsigned immediate a BITS length xed_decoded_inst_set_input_chip ⚠ Set a user-specified #xed_chip_enum_t chip name for restricting decode
@ingroup DEC xed_decoded_inst_set_memory_displacement ⚠ @ingroup DEC
Set the memory displacement using a BYTE length xed_decoded_inst_set_memory_displacement_bits ⚠ @ingroup DEC
Set the memory displacement a BITS length xed_decoded_inst_set_mode ⚠ @ingroup DEC
Set the machine mode and stack addressing width directly. This is NOT a
full initialization; Call #xed_decoded_inst_zero() before using this if
you want a clean slate. xed_decoded_inst_set_scale ⚠ @ingroup DEC xed_decoded_inst_set_user_data ⚠ @ingroup DEC
Modify the user data field. xed_decoded_inst_uses_embedded_broadcast ⚠ @ingroup DEC
Return 1 for AVX512 load-op instructions using the broadcast feature,
0 otherwise. xed_decoded_inst_uses_rflags ⚠ This returns 1 if the flags are read or written. This will return 0
otherwise. This will return 0 if the flags are really not used by this
instruction. For some shifts/rotates, XED puts a flags operand in the
operand array before it knows if the flags are used because of
mode-dependent masking effects on the immediate.
@ingroup DEC xed_decoded_inst_valid ⚠ @ingroup DEC
Return true if the instruction is valid xed_decoded_inst_valid_for_chip ⚠ Indicate if this decoded instruction is valid for the specified
#xed_chip_enum_t chip
@ingroup DEC xed_decoded_inst_vector_length_bits ⚠ @ingroup DEC
Returns 128, 256 or 512 for operations in the VEX, EVEX (or XOP)
encoding space and returns 0 for (most) nonvector operations.
This usually the content of the VEX.L or EVEX.LL field, reinterpreted.
Some GPR instructions (like the BMI1/BMI2) are encoded in the VEX space
and return non-zero values from this API. xed_decoded_inst_zero ⚠ @ingroup DEC
Zero the decode structure completely. Re-initializes all operands. xed_decoded_inst_zero_keep_mode ⚠ @ingroup DEC
Zero the decode structure, but preserve the existing machine state/mode
information. Re-initializes all operands. xed_decoded_inst_zero_keep_mode_from_operands ⚠ @ingroup DEC
Zero the decode structure, but copy the existing machine state/mode
information from the supplied operands pointer. Same as
#xed_decoded_inst_zero_keep_mode. xed_decoded_inst_zero_set_mode ⚠ @ingroup DEC
Zero the decode structure, but set the machine state/mode
information. Re-initializes all operands. xed_decoded_inst_zeroing ⚠ Returns true if the instruction uses write-masking with zeroing
@ingroup DEC xed_disp ⚠ @ingroup ENCHL
a memory displacement (not for branches)
@param displacement The value of the displacement
@param displacement_bits The width of the displacement in bits. Typically 8 or 32.
@returns #xed_enc_displacement_t xed_encode ⚠ This is the main interface to the encoder. The array should be
at most 15 bytes long. The ilen parameter should indicate
this length. If the array is too short, the encoder may fail to
encode the request. Failure is indicated by a return value of
type #xed_error_enum_t that is not equal to
#XED_ERROR_NONE. Otherwise, #XED_ERROR_NONE is returned and the
length of the encoded instruction is returned in olen. xed_encode_nop ⚠ This function will attempt to encode a NOP of exactly ilen
bytes. If such a NOP is not encodeable, then false will be returned. xed_encode_request_print ⚠ @ingroup ENC xed_encoder_request_get_iclass ⚠ @ingroup ENC xed_encoder_request_get_operand_order ⚠ @ingroup ENC
Retrieve the name of the n’th operand in the operand order. xed_encoder_request_init_from_decode ⚠ @ingroup ENC
Converts an decoder request to a valid encoder request. xed_encoder_request_operand_order_entries ⚠ @ingroup ENC
Retrieve the number of entries in the encoder operand order array
@return The number of entries in the encoder operand order array xed_encoder_request_operands ⚠ @ingroup ENC xed_encoder_request_operands_const ⚠ @ingroup ENC xed_encoder_request_set_absbr ⚠ @ingroup ENC xed_encoder_request_set_agen ⚠ @ingroup ENC xed_encoder_request_set_base0 ⚠ @ingroup ENC xed_encoder_request_set_base1 ⚠ @ingroup ENC xed_encoder_request_set_branch_displacement ⚠ @ingroup ENC xed_encoder_request_set_effective_address_size ⚠ @ingroup ENC xed_encoder_request_set_effective_operand_width ⚠ @ingroup ENC xed_encoder_request_set_iclass ⚠ @ingroup ENC xed_encoder_request_set_index ⚠ @ingroup ENC xed_encoder_request_set_mem0 ⚠ @ingroup ENC xed_encoder_request_set_mem1 ⚠ @ingroup ENC xed_encoder_request_set_memory_displacement ⚠ @ingroup ENC xed_encoder_request_set_memory_operand_length ⚠ @ingroup ENC xed_encoder_request_set_operand_order ⚠ @ingroup ENC
Specify the name as the n’th operand in the operand order. xed_encoder_request_set_ptr ⚠ @ingroup ENC xed_encoder_request_set_reg ⚠ @ingroup ENC xed_encoder_request_set_relbr ⚠ @ingroup ENC xed_encoder_request_set_scale ⚠ @ingroup ENC xed_encoder_request_set_seg0 ⚠ @ingroup ENC xed_encoder_request_set_seg1 ⚠ @ingroup ENC xed_encoder_request_set_simm ⚠ @ingroup ENC
same storage as uimm0 xed_encoder_request_set_uimm0 ⚠ @ingroup ENC
Set the uimm0 using a BYTE width. xed_encoder_request_set_uimm0_bits ⚠ @ingroup ENC
Set the uimm0 using a BIT width. xed_encoder_request_set_uimm1 ⚠ @ingroup ENC xed_encoder_request_zero ⚠ @ingroup ENC xed_encoder_request_zero_operand_order ⚠ @ingroup ENC
clear the operand order array
@param[in] p xed_encoder_request_t xed_encoder_request_zero_set_mode ⚠ @ingroup ENC xed_error_enum_t2str ⚠ This converts strings to #xed_error_enum_t types.
@param p An enumeration element of type xed_error_enum_t.
@return string
@ingroup ENUM xed_error_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_error_enum_t The last element of the enumeration.
@ingroup ENUM xed_exception_enum_t2str ⚠ This converts strings to #xed_exception_enum_t types.
@param p An enumeration element of type xed_exception_enum_t.
@return string
@ingroup ENUM xed_exception_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_exception_enum_t The last element of the enumeration.
@ingroup ENUM xed_extension_enum_t2str ⚠ This converts strings to #xed_extension_enum_t types.
@param p An enumeration element of type xed_extension_enum_t.
@return string
@ingroup ENUM xed_extension_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_extension_enum_t The last element of the enumeration.
@ingroup ENUM xed_flag_action_action_invalid ⚠ @ingroup FLAGS
returns true if the specified action is invalid. Only the 2nd flag might be invalid. xed_flag_action_enum_t2str ⚠ This converts strings to #xed_flag_action_enum_t types.
@param p An enumeration element of type xed_flag_action_enum_t.
@return string
@ingroup ENUM xed_flag_action_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_flag_action_enum_t The last element of the enumeration.
@ingroup ENUM xed_flag_action_get_action ⚠ @ingroup FLAGS
return the action xed_flag_action_get_flag_name ⚠ @ingroup FLAGS
get the name of the flag xed_flag_action_print ⚠ @ingroup FLAGS
print the flag & actions xed_flag_action_read_action ⚠ @ingroup FLAGS
test to see if the specific action is a read xed_flag_action_read_flag ⚠ @ingroup FLAGS
returns true if either action is a read xed_flag_action_write_action ⚠ @ingroup FLAGS
test to see if a specific action is a write xed_flag_action_writes_flag ⚠ @ingroup FLAGS
returns true if either action is a write xed_flag_enum_t2str ⚠ This converts strings to #xed_flag_enum_t types.
@param p An enumeration element of type xed_flag_enum_t.
@return string
@ingroup ENUM xed_flag_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_flag_enum_t The last element of the enumeration.
@ingroup ENUM xed_flag_set_is_subset_of ⚠ @ingroup FLAGS
returns true if this object has a subset of the flags of the
“other” object. xed_flag_set_mask ⚠ @ingroup FLAGS
Return the flags as a mask xed_flag_set_print ⚠ @ingroup FLAGS
print the flag set in the supplied buffer xed_format_context ⚠ Disassemble the decoded instruction using the specified syntax.
The output buffer must be at least 25 bytes long. Returns true if
disassembly proceeded without errors.
@param syntax a #xed_syntax_enum_t the specifies the disassembly format
@param xedd a #xed_decoded_inst_t for a decoded instruction
@param out_buffer a buffer to write the disassembly in to.
@param buffer_len maximum length of the disassembly buffer
@param runtime_instruction_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches.
@param context A void* used only for the call back routine for symbolic disassembly if one is provided. Can be zero.
@param symbolic_callback A function pointer for obtaining symbolic disassembly. Can be zero.
@return Returns 0 if the disassembly fails, 1 otherwise.
@ingroup PRINT xed_format_generic ⚠ @ingroup PRINT
Disassemble the instruction information to a buffer. See the
#xed_print_info_t for the required public fields of the argument.
This is the preferred method of doing disassembly.
The output buffer must be at least 25 bytes long.
@param pi a #xed_print_info_t
@return Returns 0 if the disassembly fails, 1 otherwise. xed_format_set_options ⚠ Optionally, customize the disassembly formatting options by passing
in a #xed_format_options_t structure.
@ingroup PRINT xed_get_byte ⚠ xed_get_chip_features ⚠ fill in the contents of p with the vector of chip features. xed_get_copyright ⚠ @ingroup INIT
Returns a copyright string. xed_get_cpuid_group_enum_for_isa_set ⚠ Returns the name of the i’th cpuid group associated with this isa-set.
Call this repeatedly, with 0 <= i <
XED_MAX_CPUID_GROUPS_PER_ISA_SET. Give up when i ==
XED_MAX_CPUID_GROUPS_PER_ISA_SET or the return value is
XED_CPUID_GROUP_INVALID.
An ISA-SET is supported by a chip if CPUID match is found for a single CPUID
group (OR relationship between groups). xed_get_cpuid_rec ⚠ This provides the details of the CPUID specification, if the
enumeration value is not sufficient. Returns 1 on success and fills in
the structure pointed to by p. Returns 0 on failure. xed_get_cpuid_rec_enum_for_group ⚠ Returns the name of the i’th cpuid record associated with this cpuid group.
Call this repeatedly, with 0 <= i <
XED_MAX_CPUID_RECS_PER_GROUP. Give up when i ==
XED_MAX_CPUID_RECS_PER_GROUP or the return value is
XED_CPUID_REC_INVALID.
A cpuid group is satisfied if all of its cpuid records are
set (AND relationship between records). xed_get_largest_enclosing_register ⚠ Returns the largest enclosing register for any kind of register; This
is mostly useful for GPRs. (64b mode assumed)
@ingroup REGINTFC xed_get_largest_enclosing_register32 ⚠ Returns the largest enclosing register for any kind of register; This
is mostly useful for GPRs in 32b mode.
@ingroup REGINTFC xed_get_register_width_bits ⚠ Returns the width, in bits, of the named register. 32b mode
@ingroup REGINTFC xed_get_register_width_bits64 ⚠ Returns the width, in bits, of the named register. 64b mode.
@ingroup REGINTFC xed_get_version ⚠ @ingroup INIT
Returns a string representing XED svn commit revision and time stamp. xed_gpr_reg_class ⚠ Returns the specific width GPR reg class (like XED_REG_CLASS_GPR32 or
XED_REG_CLASS_GPR64)
for a given GPR register. Or XED_REG_INVALID if not a GPR.
@ingroup REGINTFC xed_iclass_enum_t2str ⚠ This converts strings to #xed_iclass_enum_t types.
@param p An enumeration element of type xed_iclass_enum_t.
@return string
@ingroup ENUM xed_iclass_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_iclass_enum_t The last element of the enumeration.
@ingroup ENUM xed_iform_enum_t2str ⚠ This converts strings to #xed_iform_enum_t types.
@param p An enumeration element of type xed_iform_enum_t.
@return string
@ingroup ENUM xed_iform_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_iform_enum_t The last element of the enumeration.
@ingroup ENUM xed_iform_first_per_iclass ⚠ @ingroup IFORM
Return the first of the iforms for a particular iclass. This function
returns valid data as soon as global data is initialized. (This
function does not require a decoded instruction as input). xed_iform_map ⚠ @ingroup IFORM
Map the #xed_iform_enum_t to a pointer to a #xed_iform_info_t which
indicates the #xed_iclass_enum_t, the #xed_category_enum_t and the
#xed_extension_enum_t for the iform. Returns 0 if the iform is not a
valid iform. xed_iform_max_per_iclass ⚠ @ingroup IFORM
Return the maximum number of iforms for a particular iclass. This
function returns valid data as soon as global data is
initialized. (This function does not require a decoded instruction as
input). xed_iform_to_category ⚠ @ingroup IFORM
Return the category for a given iform. This
function returns valid data as soon as global data is initialized. (This
function does not require a decoded instruction as input). xed_iform_to_extension ⚠ @ingroup IFORM
Return the extension for a given iform. This function returns valid
data as soon as global data is initialized. (This function does not
require a decoded instruction as input). xed_iform_to_iclass ⚠ @ingroup IFORM
Return the iclass for a given iform. This
function returns valid data as soon as global data is initialized. (This
function does not require a decoded instruction as input). xed_iform_to_iclass_string_att ⚠ @ingroup IFORM
Return a pointer to a character string of the iclass. This
translates the internal disambiguated names to the more ambiguous
names that people like to see. This returns the ATT SYSV-syntax name. xed_iform_to_iclass_string_intel ⚠ @ingroup IFORM
Return a pointer to a character string of the iclass. This
translates the internal disambiguated names to the more ambiguous
names that people like to see. This returns the Intel-syntax name. xed_iform_to_isa_set ⚠ @ingroup IFORM
Return the isa_set for a given iform. This function returns valid data
as soon as global data is initialized. (This function does not require
a decoded instruction as input). xed_iformfl_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_iformfl_enum_t The last element of the enumeration.
@ingroup ENUM xed_ild_decode ⚠ This function just does instruction length decoding.
It does not return a fully decoded instruction.
@param xedd the decoded instruction of type #xed_decoded_inst_t .
Mode/state sent in via xedd; See the #xed_state_t .
@param itext the pointer to the array of instruction text bytes
@param bytes the length of the itext input array.
1 to 15 bytes, anything more is ignored.
@return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or
failure.
Only two failure codes are valid for this function:
#XED_ERROR_BUFFER_TOO_SHORT and #XED_ERROR_GENERAL_ERROR.
In general this function cannot tell if the instruction is valid or
not. For valid instructions, XED can figure out if enough bytes were
provided to decode the instruction. If not enough were provided,
XED returns #XED_ERROR_BUFFER_TOO_SHORT.
From this function, the #XED_ERROR_GENERAL_ERROR is an indication
that XED could not decode the instruction’s length because the
instruction was so invalid that even its length
may across implmentations. xed_imm0 ⚠ @ingroup ENCHL
a first immediate operand (known as IMM0)
@param v An immdediate operand.
@param width_bits The immediate width in bits.
@returns xed_encoder_operand_t An operand. xed_imm1 ⚠ @ingroup ENCHL
The 2nd immediate operand (known as IMM1) for rare instructions that require it.
@param v The 2nd immdediate (byte-width) operand
@returns xed_encoder_operand_t An operand. xed_init_print_info ⚠ @ingroup PRINT xed_inst ⚠ @ingroup ENCHL
instruction with an array of operands. The maximum number is
XED_ENCODER_OPERANDS_MAX. The array’s contents are copied.
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param number_of_operands length of the subsequent array
@param operand_array An array of #xed_encoder_operand_t objects xed_inst0 ⚠ @ingroup ENCHL
instruction with no operands
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits xed_inst1 ⚠ @ingroup ENCHL
instruction with one operand
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param op0 the operand xed_inst2 ⚠ @ingroup ENCHL
instruction with two operands
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param op0 the 1st operand
@param op1 the 2nd operand xed_inst3 ⚠ @ingroup ENCHL
instruction with three operands
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param op0 the 1st operand
@param op1 the 2nd operand
@param op2 the 3rd operand xed_inst4 ⚠ @ingroup ENCHL
instruction with four operands
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param op0 the 1st operand
@param op1 the 2nd operand
@param op2 the 3rd operand
@param op3 the 4th operand xed_inst5 ⚠ @ingroup ENCHL
instruction with five operands
@param inst The #xed_encoder_instruction_t to be filled in
@param mode The xed_state_t including the machine mode and stack address width.
@param iclass The #xed_iclass_enum_t
@param effective_operand_width in bits
@param op0 the 1st operand
@param op1 the 2nd operand
@param op2 the 3rd operand
@param op3 the 4th operand
@param op4 the 5th operand xed_inst_category ⚠ xed_inst_cpl ⚠ @ingroup DEC
xed_inst_cpl() is DEPRECATED. Please use
“xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)”
instead.
Return the current privilege level (CPL) required for execution, 0 or
3. If the value is zero, then the instruction can only execute in ring 0. xed_inst_exception ⚠ @ingroup DEC
Return #xed_exception_enum_t if present for the specified instruction.
This is currently only used for SSE and AVX instructions. xed_inst_extension ⚠ xed_inst_flag_info_index ⚠ xed_inst_get_attribute ⚠ @ingroup DEC
Scan for the attribute attr and return 1 if it is found, 0 otherwise. xed_inst_get_attributes ⚠ @ingroup DEC
Return the attributes bit vector xed_inst_iclass ⚠ xed_inst_iform_enum ⚠ xed_inst_isa_set ⚠ xed_inst_noperands ⚠ @ingroup DEC
Number of instruction operands xed_inst_operand ⚠ @ingroup DEC
Obtain a pointer to an individual operand xed_inst_table_base ⚠ @ingroup DEC
Return the base of instruction table. xed_internal_assert ⚠ xed_isa_set_enum_t2str ⚠ This converts strings to #xed_isa_set_enum_t types.
@param p An enumeration element of type xed_isa_set_enum_t.
@return string
@ingroup ENUM xed_isa_set_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_isa_set_enum_t The last element of the enumeration.
@ingroup ENUM xed_isa_set_is_valid_for_chip ⚠ @ingroup ISASET
return 1 if the isa_set is part included in the specified chip, 0
otherwise. xed_itoa ⚠ xed_itoa_hex ⚠ defaults to lowercase xed_itoa_hex_ul ⚠ xed_itoa_hex_zeros ⚠ defaults to lowercase xed_machine_mode_enum_t2str ⚠ This converts strings to #xed_machine_mode_enum_t types.
@param p An enumeration element of type xed_machine_mode_enum_t.
@return string
@ingroup ENUM xed_machine_mode_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_machine_mode_enum_t The last element of the enumeration.
@ingroup ENUM xed_make_int64 ⚠ xed_make_uint64 ⚠ xed_mem_b ⚠ @ingroup ENCHL
memory operand - base only
@param base The base register
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_bd ⚠ @ingroup ENCHL
memory operand - base and displacement only
@param base The base register
@param disp The displacement
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_bisd ⚠ @ingroup ENCHL
memory operand - base, index, scale, displacement
@param base The base register
@param index The index register
@param scale The scale for the index register value
@param disp The displacement
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_gb ⚠ @ingroup ENCHL
memory operand - segment and base only
@param seg The segment override register
@param base The base register
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_gbd ⚠ @ingroup ENCHL
memory operand - segment, base and displacement only
@param seg The segment override register
@param base The base register
@param disp The displacement
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_gbisd ⚠ @ingroup ENCHL
memory operand - segment, base, index, scale, and displacement
@param seg The segment override register
@param base The base register
@param index The index register
@param scale The scale for the index register value
@param disp The displacement
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_mem_gd ⚠ @ingroup ENCHL
memory operand - segment and displacement only
@param seg The segment override register
@param disp The displacement
@param width_bits The length of the memory reference in bits.
@returns xed_encoder_operand_t An operand. xed_modify_chip_features ⚠ present = 1 to turn the feature on. present=0 to remove the feature. xed_nonterminal_enum_t2str ⚠ This converts strings to #xed_nonterminal_enum_t types.
@param p An enumeration element of type xed_nonterminal_enum_t.
@return string
@ingroup ENUM xed_nonterminal_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_nonterminal_enum_t The last element of the enumeration.
@ingroup ENUM xed_norep_map ⚠ @ingroup DEC Take an #xed_iclass_enum_t value for an instruction with a
REP/REPNE/REPE prefix and return the corresponding #xed_iclass_enum_t
without that prefix. If the input instruction does not have a
REP/REPNE/REPE prefix, this function returns XED_ICLASS_INVALID. xed_operand_action_conditional_read ⚠ xed_operand_action_conditional_write ⚠ xed_operand_action_enum_t2str ⚠ This converts strings to #xed_operand_action_enum_t types.
@param p An enumeration element of type xed_operand_action_enum_t.
@return string
@ingroup ENUM xed_operand_action_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_action_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_action_read ⚠ xed_operand_action_read_and_written ⚠ xed_operand_action_read_only ⚠ xed_operand_action_written ⚠ xed_operand_action_written_only ⚠ xed_operand_conditional_read ⚠ @ingroup DEC
If the operand has a conditional read (may also write) xed_operand_conditional_write ⚠ @ingroup DEC
If the operand has a conditional write (may also read) xed_operand_convert_enum_t2str ⚠ This converts strings to #xed_operand_convert_enum_t types.
@param p An enumeration element of type xed_operand_convert_enum_t.
@return string
@ingroup ENUM xed_operand_convert_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_convert_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_element_type_enum_t2str ⚠ This converts strings to #xed_operand_element_type_enum_t types.
@param p An enumeration element of type xed_operand_element_type_enum_t.
@return string
@ingroup ENUM xed_operand_element_type_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_element_type_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_element_xtype_enum_t2str ⚠ This converts strings to #xed_operand_element_xtype_enum_t types.
@param p An enumeration element of type xed_operand_element_xtype_enum_t.
@return string
@ingroup ENUM xed_operand_element_xtype_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_element_xtype_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_enum_t2str ⚠ This converts strings to #xed_operand_enum_t types.
@param p An enumeration element of type xed_operand_enum_t.
@return string
@ingroup ENUM xed_operand_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_imm ⚠ @ingroup DEC
@param p an operand template, #xed_operand_t.
These operands represent branch displacements, memory displacements and
various immediates xed_operand_is_memory_addressing_register ⚠ @ingroup DEC
Tests the enum for inclusion in XED_OPERAND_{BASE0,BASE1,INDEX,SEG0,SEG1}
@param name the operand name, type #xed_operand_enum_t
@return 1 if the operand name is for a memory addressing register operand, 0
otherwise. See also #xed_operand_is_register . xed_operand_is_register ⚠ @ingroup DEC
Tests the enum for inclusion in XED_OPERAND_REG0 through XED_OPERAND_REG9.
@param name the operand name, type #xed_operand_enum_t
@return 1 if the operand name is REG0…REG9, 0 otherwise. xed_operand_name ⚠ @ingroup DEC xed_operand_nonterminal_name ⚠ @ingroup DEC xed_operand_operand_visibility ⚠ @ingroup DEC xed_operand_print ⚠ @ingroup DEC
Print the operand p into the buffer buf, of length buflen.
@param p an operand template, #xed_operand_t.
@param buf buffer that gets filled in
@param buflen maximum buffer length xed_operand_read ⚠ @ingroup DEC
If the operand is read, including conditional reads xed_operand_read_and_written ⚠ @ingroup DEC
If the operand is read-and-written, conditional reads and conditional writes xed_operand_read_only ⚠ @ingroup DEC
If the operand is read-only, including conditional reads xed_operand_reg ⚠ @ingroup DEC
Careful with this one – use #xed_decoded_inst_get_reg()! This one is
probably not what you think it is. It is only used for hard-coded
registers implicit in the instruction encoding. Most likely you want to
get the #xed_operand_enum_t and then look up the instruction using
#xed_decoded_inst_get_reg(). The hard-coded registers are also available
that way.
@param p an operand template, #xed_operand_t.
@return the implicit or suppressed registers, type #xed_reg_enum_t xed_operand_rw ⚠ @ingroup DEC
DEPRECATED: Returns the raw R/W action. There are many cases for conditional reads
and writes. See #xed_decoded_inst_operand_action(). xed_operand_template_is_register ⚠ @ingroup DEC
Careful with this one; See #xed_operand_is_register().
@param p an operand template, #xed_operand_t.
@return 1 if the operand template represents are register-type
operand. xed_operand_type ⚠ @ingroup DEC
@return The #xed_operand_type_enum_t of the operand template.
This is probably not what you want. xed_operand_type_enum_t2str ⚠ This converts strings to #xed_operand_type_enum_t types.
@param p An enumeration element of type xed_operand_type_enum_t.
@return string
@ingroup ENUM xed_operand_type_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_type_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_values_accesses_memory ⚠ @ingroup OPERANDS xed_operand_values_branch_not_taken_hint ⚠ @ingroup OPERANDS
Returns true if 0x2E prefix on Jcc xed_operand_values_branch_taken_hint ⚠ @ingroup OPERANDS
Returns true if 0x3E prefix on Jcc xed_operand_values_cet_no_track ⚠ @ingroup OPERANDS
Returns true for indirect call/jmp with 0x3E prefix (if the legacy prefix rules are obeyed) xed_operand_values_clear_rep ⚠ @ingroup OPERANDS
DO NOT USE - DEPRECATED. The correct way to do remove a rep prefix is by changing the iclass xed_operand_values_dump ⚠ @ingroup OPERANDS
Dump all the information about the operands to buf. xed_operand_values_get_atomic ⚠ @ingroup OPERANDS
Returns true if the memory operation has atomic read-modify-write
semantics. An XCHG accessing memory is atomic with or without a
LOCK prefix. xed_operand_values_get_base_reg ⚠ @ingroup OPERANDS xed_operand_values_get_branch_displacement_byte ⚠ @ingroup OPERANDS xed_operand_values_get_branch_displacement_int64 ⚠ @ingroup OPERANDS xed_operand_values_get_branch_displacement_length ⚠ @ingroup OPERANDS
Return the branch displacement width in bytes xed_operand_values_get_branch_displacement_length_bits ⚠ @ingroup OPERANDS
Return the branch displacement width in bits xed_operand_values_get_displacement_for_memop ⚠ @ingroup OPERANDS
Deprecated. Compatibility function for XED0. See has_memory_displacement(). xed_operand_values_get_effective_address_width ⚠ @ingroup OPERANDS
Returns The effective address width in bits: 16/32/64. xed_operand_values_get_effective_operand_width ⚠ @ingroup OPERANDS
Returns The effective operand width in bits: 16/32/64. Note this is not
the same as the width of the operand which can vary! For 8 bit
operations, the effective operand width is the machine mode’s default
width. If you also want to identify byte operations use the higher
level function #xed_decoded_inst_get_operand_width() . xed_operand_values_get_iclass ⚠ @ingroup OPERANDS xed_operand_values_get_immediate_byte ⚠ @ingroup OPERANDS
Return the i’th byte of the immediate xed_operand_values_get_immediate_int64 ⚠ @ingroup OPERANDS xed_operand_values_get_immediate_is_signed ⚠ @ingroup OPERANDS
Return true if the first immediate (IMM0) is signed xed_operand_values_get_immediate_uint64 ⚠ @ingroup OPERANDS xed_operand_values_get_index_reg ⚠ @ingroup OPERANDS xed_operand_values_get_long_mode ⚠ @ingroup OPERANDS xed_operand_values_get_memory_displacement_byte ⚠ @ingroup OPERANDS xed_operand_values_get_memory_displacement_int64 ⚠ Returns the potentially scaled value of the memory
displacement. Certain AVX512 memory displacements are scaled before
they are used. @ingroup OPERANDS xed_operand_values_get_memory_displacement_int64_raw ⚠ Returns the unscaled (raw) memory displacement. Certain AVX512 memory
displacements are scaled before they are used. @ingroup OPERANDS xed_operand_values_get_memory_displacement_length ⚠ @ingroup OPERANDS
Return the memory displacement width in BYTES xed_operand_values_get_memory_displacement_length_bits ⚠ @ingroup OPERANDS
Return the memory displacement width in BITS xed_operand_values_get_memory_displacement_length_bits_raw ⚠ @ingroup OPERANDS
Return the raw memory displacement width in BITS(ignores scaling) xed_operand_values_get_memory_operand_length ⚠ return bytes
@ingroup OPERANDS xed_operand_values_get_pp_vex_prefix ⚠ @ingroup OPERANDS
Return the [VEX,EVEX].PP encoding value (2 bits) xed_operand_values_get_real_mode ⚠ @ingroup OPERANDS xed_operand_values_get_scale ⚠ @ingroup OPERANDS xed_operand_values_get_second_immediate ⚠ @ingroup OPERANDS xed_operand_values_get_seg_reg ⚠ @ingroup OPERANDS xed_operand_values_get_stack_address_width ⚠ @ingroup OPERANDS
Returns The stack address width in bits: 16/32/64. xed_operand_values_has_66_prefix ⚠ @ingroup OPERANDS
This includes any 66 prefix that shows up even if it is ignored. xed_operand_values_has_address_size_prefix ⚠ @ingroup OPERANDS
This indicates the presence of a 67 prefix. xed_operand_values_has_branch_displacement ⚠ @ingroup OPERANDS
True if there is a branch displacement xed_operand_values_has_disp ⚠ @ingroup OPERANDS
ALIAS for has_displacement().
Deprecated. See has_memory_displacement() and
has_branch_displacement(). xed_operand_values_has_displacement ⚠ @ingroup OPERANDS
True if there is a memory or branch displacement xed_operand_values_has_immediate ⚠ @ingroup OPERANDS
Return true if there is an immediate operand xed_operand_values_has_lock_prefix ⚠ @ingroup OPERANDS
Returns true if the memory operation has a valid lock prefix. xed_operand_values_has_memory_displacement ⚠ @ingroup OPERANDS
True if there is a memory displacement xed_operand_values_has_modrm_byte ⚠ @ingroup OPERANDS
Returns true if the instruction has a MODRM byte. xed_operand_values_has_operand_size_prefix ⚠ @ingroup OPERANDS
This does not include the cases when the 66 prefix is used an
opcode-refining prefix for multibyte opcodes. xed_operand_values_has_real_rep ⚠ @ingroup OPERANDS
True if the instruction has a real REP prefix. This returns false if
there is no F2/F3 prefix or the F2/F3 prefix is used to refine the
opcode as in some SSE operations. xed_operand_values_has_rep_prefix ⚠ @ingroup OPERANDS
True if the instruction as a F3 REP prefix (used for opcode refining,
for rep for string operations, or ignored). xed_operand_values_has_repne_prefix ⚠ @ingroup OPERANDS
True if the instruction as a F2 REP prefix (used for opcode refining,
for rep for string operations, or ignored). xed_operand_values_has_rexw_prefix ⚠ @ingroup OPERANDS
This instruction has a REX prefix with the W bit set. xed_operand_values_has_segment_prefix ⚠ @ingroup OPERANDS xed_operand_values_has_sib_byte ⚠ @ingroup OPERANDS
Returns true if the instruction has a SIB byte. xed_operand_values_init ⚠ @ingroup OPERANDS
Initializes operand structure xed_operand_values_init_keep_mode ⚠ @ingroup OPERANDS
Initializes dst operand structure but preserves the existing
MODE/SMODE values from the src operand structure. xed_operand_values_init_set_mode ⚠ @ingroup OPERANDS
Initializes the operand storage and sets mode values. xed_operand_values_is_nop ⚠ @ingroup OPERANDS xed_operand_values_is_prefetch ⚠ @ingroup OPERANDS xed_operand_values_lockable ⚠ @ingroup OPERANDS
Returns true if the instruction could be re-encoded to have a lock
prefix but does not have one currently. xed_operand_values_mandatory_66_prefix ⚠ @ingroup OPERANDS
This is exclusive to cases whereby the 66 prefix is mandatory. xed_operand_values_memop_without_modrm ⚠ @ingroup OPERANDS
Returns true if the instruction access memory but without using a MODRM
byte limiting its addressing modes. xed_operand_values_number_of_memory_operands ⚠ @ingroup OPERANDS xed_operand_values_print_short ⚠ @ingroup OPERANDS
More tersely dump all the information about the operands to buf. xed_operand_values_segment_prefix ⚠ @ingroup OPERANDS
Return the segment prefix, if any, as a #xed_reg_enum_t value. xed_operand_values_set_absbr ⚠ @ingroup OPERANDS
Indicate that we have an absolute branch. xed_operand_values_set_base_reg ⚠ @ingroup OPERANDS xed_operand_values_set_branch_displacement ⚠ @ingroup OPERANDS
Set the branch displacement using a BYTES length xed_operand_values_set_branch_displacement_bits ⚠ @ingroup OPERANDS
Set the branch displacement using a BITS length xed_operand_values_set_effective_address_width ⚠ @ingroup OPERANDS
width is bits 16, 32, 64 xed_operand_values_set_effective_operand_width ⚠ @ingroup OPERANDS
width is bits 8, 16, 32, 64 xed_operand_values_set_iclass ⚠ @ingroup OPERANDS xed_operand_values_set_immediate_signed ⚠ @ingroup OPERANDS
Set the signed immediate using a BYTES length xed_operand_values_set_immediate_signed_bits ⚠ @ingroup OPERANDS
Set the signed immediate using a BITS length xed_operand_values_set_immediate_unsigned ⚠ @ingroup OPERANDS
Set the unsigned immediate using a BYTE length. xed_operand_values_set_immediate_unsigned_bits ⚠ @ingroup OPERANDS
Set the unsigned immediate using a BIT length. xed_operand_values_set_index_reg ⚠ @ingroup OPERANDS xed_operand_values_set_lock ⚠ @ingroup OPERANDS xed_operand_values_set_memory_displacement ⚠ @ingroup OPERANDS
Set the memory displacement using a BYTES length xed_operand_values_set_memory_displacement_bits ⚠ @ingroup OPERANDS
Set the memory displacement using a BITS length xed_operand_values_set_memory_operand_length ⚠ takes bytes, not bits, as an argument
@ingroup OPERANDS xed_operand_values_set_mode ⚠ @ingroup OPERANDS
Set the mode values xed_operand_values_set_operand_reg ⚠ @ingroup OPERANDS
Set the operand storage field entry named ‘operand_name’ to the
register value specified by ‘reg_name’. xed_operand_values_set_relbr ⚠ @ingroup OPERANDS
Indicate that we have a relative branch. xed_operand_values_set_scale ⚠ @ingroup OPERANDS xed_operand_values_set_seg_reg ⚠ @ingroup OPERANDS xed_operand_values_using_default_segment ⚠ @ingroup OPERANDS
Indicates if the default segment is being used.
@param[in] p the pointer to the #xed_operand_values_t structure.
@param[in] i 0 or 1, indicating which memory operation.
@return true if the memory operation is using the default segment for
the associated addressing mode base register. xed_operand_values_zero_branch_displacement ⚠ @ingroup OPERANDS xed_operand_values_zero_immediate ⚠ @ingroup OPERANDS xed_operand_values_zero_memory_displacement ⚠ @ingroup OPERANDS xed_operand_values_zero_segment_override ⚠ @ingroup OPERANDS xed_operand_visibility_enum_t2str ⚠ This converts strings to #xed_operand_visibility_enum_t types.
@param p An enumeration element of type xed_operand_visibility_enum_t.
@return string
@ingroup ENUM xed_operand_visibility_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_visibility_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_width ⚠ @ingroup DEC xed_operand_width_bits ⚠ @ingroup DEC
@param p an operand template, #xed_operand_t.
@param eosz effective operand size of the instruction, 1 | 2 | 3 for
16 | 32 | 64 bits respectively. 0 is invalid.
@return the actual width of operand in bits.
See xed_decoded_inst_operand_length_bits() for a more general solution. xed_operand_width_enum_t2str ⚠ This converts strings to #xed_operand_width_enum_t types.
@param p An enumeration element of type xed_operand_width_enum_t.
@return string
@ingroup ENUM xed_operand_width_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_operand_width_enum_t The last element of the enumeration.
@ingroup ENUM xed_operand_written ⚠ @ingroup DEC
If the operand is written, including conditional writes xed_operand_written_only ⚠ @ingroup DEC
If the operand is written-only, including conditional writes xed_operand_xtype ⚠ @ingroup DEC
@return The #xed_operand_element_xtype_enum_t of the operand template.
This is probably not what you want. xed_other ⚠ @ingroup ENCHL
an operand storage field name and value xed_patch_brdisp ⚠ Replace a relative/absolute branch displacement.
The widths of original displacement and replacement must match.
@param xedd A decoded instruction.
@param itext The corresponding encoder output, byte array.
@param disp A xed_encoder_operand_t object describing the new displacement.
@returns xed_bool_t 1=success, 0=failure
@ingroup ENCHLPATCH xed_patch_disp ⚠ Replace a memory displacement.
The widths of original displacement and replacement must match.
@param xedd A decoded instruction.
@param itext The corresponding encoder output, byte array.
@param disp A xed_enc_displacement_t object describing the new displacement.
@returns xed_bool_t 1=success, 0=failure
@ingroup ENCHLPATCH xed_patch_imm0 ⚠ Replace an imm0 immediate value.
The widths of original immediate and replacement must match.
@param xedd A decoded instruction.
@param itext The corresponding encoder output, byte array.
@param imm0 A xed_encoder_operand_t object describing the new immediate.
@returns xed_bool_t 1=success, 0=failure
@ingroup ENCHLPATCH xed_ptr ⚠ @ingroup ENCHL
a relative displacement for a PTR operand – the subsequent imm0 holds
the 16b selector
@param brdisp The displacement for a far pointer operand
@param width_bits The width of the far pointr displacement in bits.
@returns xed_encoder_operand_t An operand. xed_reg ⚠ @ingroup ENCHL
a register operand
@param reg A #xed_reg_enum_t register operand
@returns xed_encoder_operand_t An operand. xed_reg_class ⚠ Returns the register class of the given input register.
@ingroup REGINTFC xed_reg_class_enum_t2str ⚠ This converts strings to #xed_reg_class_enum_t types.
@param p An enumeration element of type xed_reg_class_enum_t.
@return string
@ingroup ENUM xed_reg_class_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_reg_class_enum_t The last element of the enumeration.
@ingroup ENUM xed_reg_enum_t2str ⚠ This converts strings to #xed_reg_enum_t types.
@param p An enumeration element of type xed_reg_enum_t.
@return string
@ingroup ENUM xed_reg_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_reg_enum_t The last element of the enumeration.
@ingroup ENUM xed_register_abort_function ⚠ @ingroup INIT
This is for registering a function to be called during XED’s assert
processing. If you do not register an abort function, then the system’s
abort function will be called. If your supplied function returns, then
abort() will still be called. xed_relbr ⚠ @ingroup ENCHL
a relative branch displacement operand
@param brdisp The branch displacement
@param width_bits The width of the displacement in bits. Typically 8 or 32.
@returns xed_encoder_operand_t An operand. xed_rep ⚠ @ingroup ENCHL
To add a REP (0xF3) prefix.
@param x The #xed_encoder_instruction_t being filled in. xed_rep_map ⚠ @ingroup DEC Take an #xed_iclass_enum_t value without a REP prefix and
return the corresponding #xed_iclass_enum_t with a REP prefix. If the
input instruction cannot have a REP prefix, this function returns
XED_ICLASS_INVALID. xed_rep_remove ⚠ @ingroup DEC Take an instruction with a REP/REPE/REPNE prefix and
return the corresponding xed_iclass_enum_t without that prefix. The
return value differs from the other functions in this group: If the
input iclass does not have REP/REPNE/REPE prefix, the function returns
the original instruction. xed_repe_map ⚠ @ingroup DEC Take an #xed_iclass_enum_t value without a REPE prefix and
return the corresponding #xed_iclass_enum_t with a REPE prefix. If the
input instruction cannot have have a REPE prefix, this function returns
XED_ICLASS_INVALID. xed_repne ⚠ @ingroup ENCHL
To add a REPNE (0xF2) prefix.
@param x The #xed_encoder_instruction_t being filled in. xed_repne_map ⚠ @ingroup DEC Take an #xed_iclass_enum_t value without a REPNE prefix
and return the corresponding #xed_iclass_enum_t with a REPNE prefix. If
the input instruction cannot have a REPNE prefix, this function returns
XED_ICLASS_INVALID. xed_seg0 ⚠ @ingroup ENCHL
seg reg override for implicit suppressed memory ops xed_seg1 ⚠ @ingroup ENCHL
seg reg override for implicit suppressed memory ops xed_set_log_file ⚠ Set the FILE* for XED’s log msgs. This takes a FILE* as a void* because
some software defines their own FILE* types creating conflicts. xed_set_verbosity ⚠ Set the verbosity level for XED xed_shortest_width_signed ⚠ returns the number of bytes required to store the SIGNED number x
given a mask of legal lengths. For the legal_widths argument, bit 0 implies 1
byte is a legal return width, bit 1 implies that 2 bytes is a legal
return width, bit 2 implies that 4 bytes is a legal return width. This
returns 8 (indicating 8B) if none of the provided legal widths applies. xed_shortest_width_unsigned ⚠ returns the number of bytes required to store the UNSIGNED number x
given a mask of legal lengths. For the legal_widths argument, bit 0
implies 1 byte is a legal return width, bit 1 implies that 2 bytes is a
legal return width, bit 2 implies that 4 bytes is a legal return width.
This returns 8 (indicating 8B) if none of the provided legal widths
applies. xed_sign_extend8_16 ⚠ xed_sign_extend8_32 ⚠ xed_sign_extend8_64 ⚠ xed_sign_extend16_32 ⚠ xed_sign_extend16_64 ⚠ xed_sign_extend32_64 ⚠ xed_sign_extend_arbitrary_to_32 ⚠ arbitrary sign extension from a qty of “bits” length to 32b xed_sign_extend_arbitrary_to_64 ⚠ arbitrary sign extension from a qty of “bits” length to 64b xed_simm0 ⚠ @ingroup ENCHL
an 32b signed immediate operand
@param v An signed immdediate operand.
@param width_bits The immediate width in bits.
@returns xed_encoder_operand_t An operand. xed_simple_flag_get_flag_action ⚠ @ingroup FLAGS
return the specific flag-action. Very detailed low level information xed_simple_flag_get_may_write ⚠ @ingroup FLAGS
Indicates the flags are only conditionally written. Usually MAY-writes
of the flags instructions that are dependent on a REP count. xed_simple_flag_get_must_write ⚠ @ingroup FLAGS
the flags always written xed_simple_flag_get_nflags ⚠ @ingroup FLAGS
returns the number of flag-actions xed_simple_flag_get_read_flag_set ⚠ @ingroup FLAGS
return union of bits for read flags xed_simple_flag_get_undefined_flag_set ⚠ @ingroup FLAGS
return union of bits for undefined flags xed_simple_flag_get_written_flag_set ⚠ @ingroup FLAGS
return union of bits for written flags xed_simple_flag_print ⚠ @ingroup FLAGS
print the flags xed_simple_flag_reads_flags ⚠ @ingroup FLAGS
boolean test to see if flags are read, scans the flags xed_simple_flag_writes_flags ⚠ @ingroup FLAGS
boolean test to see if flags are written, scans the flags xed_state_get_address_width ⚠ return the address width
@ingroup INIT xed_state_get_machine_mode ⚠ return the machine mode
@ingroup INIT xed_state_get_stack_address_width ⚠ Return the STACK address width
@ingroup INIT xed_state_init ⚠ Constructor.
DEPRECATED: use #xed_state_init2().
The mode, and addresses widths are enumerations that specify the number
of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and
stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine
modes, you must specify valid addressing widths. xed_state_init2 ⚠ Constructor.
The mode, and addresses widths are enumerations that specify the number
of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and
stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine
modes, you must specify valid addressing widths. xed_state_long64_mode ⚠ true iff the machine is in LONG_64 mode
@ingroup INIT xed_state_mode_width_16 ⚠ @ingroup INIT xed_state_mode_width_32 ⚠ @ingroup INIT xed_state_print ⚠ @ingroup INIT xed_state_real_mode ⚠ @ingroup INIT xed_state_set_machine_mode ⚠ Set the machine mode which corresponds to the default data operand size
@ingroup INIT xed_state_set_stack_address_width ⚠ set the STACK address width
@ingroup INIT xed_state_zero ⚠ clear the xed_state_t
@ingroup INIT xed_strcat ⚠ xed_strcpy ⚠ xed_strlen ⚠ xed_strncat ⚠ returns the number of bytes remaining for the next use of
#xed_strncpy() or #xed_strncat() . xed_strncpy ⚠ returns the number of bytes remaining for the next use of
#xed_strncpy() or #xed_strncat() . xed_syntax_enum_t2str ⚠ This converts strings to #xed_syntax_enum_t types.
@param p An enumeration element of type xed_syntax_enum_t.
@return string
@ingroup ENUM xed_syntax_enum_t_last ⚠ Returns the last element of the enumeration
@return xed_syntax_enum_t The last element of the enumeration.
@ingroup ENUM xed_tables_init ⚠ @ingroup INIT
This is the call to initialize the XED encode and decode tables. It
must be called once before using XED. xed_zero_extend8_16 ⚠ xed_zero_extend8_32 ⚠ xed_zero_extend8_64 ⚠ xed_zero_extend16_32 ⚠ xed_zero_extend16_64 ⚠ xed_zero_extend32_64 ⚠ __blkcnt64_t __blkcnt_t __blksize_t __caddr_t __clock_t __clockid_t __daddr_t __dev_t __fsblkcnt64_t __fsblkcnt_t __fsfilcnt64_t __fsfilcnt_t __fsword_t __gid_t __id_t __ino64_t __ino_t __int8_t __int16_t __int32_t __int64_t __int_least8_t __int_least16_t __int_least32_t __int_least64_t __intmax_t __intptr_t __key_t __loff_t __mode_t __nlink_t __off64_t __off_t __pid_t __quad_t __rlim64_t __rlim_t __sig_atomic_t __socklen_t __ssize_t __suseconds64_t __suseconds_t __syscall_slong_t __syscall_ulong_t __time_t __timer_t __u_char __u_int __u_long __u_quad_t __u_short __uid_t __uint8_t __uint16_t __uint32_t __uint64_t __uint_least8_t __uint_least16_t __uint_least32_t __uint_least64_t __uintmax_t __useconds_t int_fast8_t int_fast16_t int_fast32_t int_fast64_t int_least8_t int_least16_t int_least32_t int_least64_t intmax_t uint_fast8_t uint_fast16_t uint_fast32_t uint_fast64_t uint_least8_t uint_least16_t uint_least32_t uint_least64_t uintmax_t xed_addr_t xed_bits_t xed_bool_t xed_decoded_inst_t @ingroup DEC
The main container for instructions. After decode, it holds an array of
operands with derived information from decode and also valid
#xed_inst_t pointer which describes the operand templates and the
operand order. See @ref DEC for API documentation. xed_disassembly_callback_fn_t @param address The input address for which we want symbolic name and offset
@param symbol_buffer A buffer to hold the symbol name. The callback function should fill this in and terminate
with a null byte.
@param buffer_length The maximum length of the symbol_buffer including then null
@param offset A pointer to a xed_uint64_t to hold the offset from the provided symbol.
@param context This void* pointer passed to the disassembler’s new interface so that the caller can identify
the proper context against which to resolve the symbols.
The disassembler passes this value to
the callback. The legacy formatters
that do not have context will pass zero for this parameter.
@return 0 on failure, 1 on success. xed_encoder_iforms_t xed_encoder_request_s @ingroup ENC xed_encoder_request_t @ingroup ENC xed_flag_action_t @ingroup FLAGS
Associated with each flag field there can be one action. xed_flag_set_t @ingroup FLAGS
a union of flags bits xed_iform_info_t @ingroup IFORM
Statically available information about iforms.
Values are returned by #xed_iform_map(). xed_inst_t @ingroup DEC
constant information about a decoded instruction form, including
the pointer to the constant operand properties #xed_operand_t for this
instruction form. xed_int_t xed_operand_extractor_fn_t xed_operand_storage_t xed_operand_t @ingroup DEC
Constant information about an individual generic operand, like an
operand template, describing the operand properties. See @ref DEC for
API information. xed_operand_values_t @ingroup DEC
The main container for instructions. After decode, it holds an array of
operands with derived information from decode and also valid
#xed_inst_t pointer which describes the operand templates and the
operand order. See @ref DEC for API documentation. xed_register_callback_fn_t A function for obtaining register values. 32b return values should be
zero extended to 64b. The error value is set to nonzero if the callback
experiences some sort of problem. @ingroup AGEN xed_segment_base_callback_fn_t A function for obtaining the segment base values. 32b return values
should be zero extended zero extended to 64b. The error value is set to
nonzero if the callback experiences some sort of problem.
@ingroup AGEN xed_simple_flag_t @ingroup FLAGS
A collection of #xed_flag_action_t’s and unions of read and written flags xed_state_t Encapsulates machine modes for decoder/encoder requests.
It specifies the machine operating mode as a
#xed_machine_mode_enum_t
for decoding and encoding. The machine mode corresponds to the default
data operand width for that mode. For all modes other than the 64b long
mode (XED_MACHINE_MODE_LONG_64), a default addressing width, and a
stack addressing width must be supplied of type
#xed_address_width_enum_t . @ingroup INIT xed_uint_t xed_user_abort_function_t xed_decoded_inst_s__bindgen_ty_1 xed_decoded_inst_s__bindgen_ty_2 xed_encoder_operand_t__bindgen_ty_1 xed_encoder_prefixes_t xed_flag_set_s @ingroup FLAGS
a union of flags bits xed_ild_vars_t xed_operand_s__bindgen_ty_1 xed_union16_t xed_union32_t xed_union64_t