Crate xed_sys

Source

Expand description

Intel XED Bindings.

For the real docs see: https://intelxed.github.io

Note that xed_tables_init() must be called before using the library.

§Features

bindgen - Don’t use the bundled bindings files and instead regenerate rust bindings from scratch at compile time. You should never need to enable this manually but it will be enabled by other features.

Structs§

__BindgenBitfieldUnit
xed_attributes_t
xed_chip_features_t: @ingroup ISASET
xed_cpuid_rec_t: @ingroup CPUID @brief a data structure representing a CPUID record
xed_decoded_inst_s: @ingroup DEC The main container for instructions. After decode, it holds an array of operands with derived information from decode and also valid #xed_inst_t pointer which describes the operand templates and the operand order. See @ref DEC for API documentation.
xed_decoder_vars_s
xed_enc_displacement_t
xed_encoder_iforms_s
xed_encoder_instruction_t
xed_encoder_operand_t
xed_encoder_operand_t__bindgen_ty_1__bindgen_ty_1
xed_encoder_prefixes_t__bindgen_ty_1
xed_encoder_vars_s
xed_flag_dfv_s__bindgen_ty_1
xed_flag_enum_s: @ingroup FLAGS Associated with each flag field there can be one action.
xed_flag_set_s__bindgen_ty_1
xed_format_options_t: Options for the disasembly formatting functions. Set once during initialization by a calling #xed_format_set_options @ingroup PRINT
xed_iform_info_s: @ingroup IFORM Statically available information about iforms. Values are returned by #xed_iform_map().
xed_ild_vars_t__bindgen_ty_1
xed_inst_s: @ingroup DEC constant information about a decoded instruction form, including the pointer to the constant operand properties #xed_operand_t for this instruction form.
xed_memop_t
xed_operand_s: @ingroup DEC Constant information about an individual generic operand, like an operand template, describing the operand properties. See @ref DEC for API information.
xed_operand_storage_s
xed_print_info_t: @ingroup PRINT This contains the information used by the various disassembly printers. Call xed_init_print_info to initialize the fields. Then change the required and optional fields when required.
xed_simple_flag_s: @ingroup FLAGS A collection of #xed_flag_action_t’s and unions of read and written flags
xed_state_s: Encapsulates machine modes for decoder/encoder requests. It specifies the machine operating mode as a #xed_machine_mode_enum_t for decoding and encoding. The machine mode corresponds to the default data operand width for that mode. For all modes other than the 64b long mode (XED_MACHINE_MODE_LONG_64), a default addressing width, and a stack addressing width must be supplied of type #xed_address_width_enum_t . @ingroup INIT
xed_union16_t__bindgen_ty_1
xed_union32_t__bindgen_ty_1
xed_union32_t__bindgen_ty_2
xed_union64_t__bindgen_ty_1
xed_union64_t__bindgen_ty_2
xed_union64_t__bindgen_ty_3

Constants§

XED_64B
XED_ADDRESS_WIDTH_16b: < 16b addressing
XED_ADDRESS_WIDTH_32b: < 32b addressing
XED_ADDRESS_WIDTH_64b: < 64b addressing
XED_ADDRESS_WIDTH_INVALID
XED_ADDRESS_WIDTH_LAST
XED_ATTRIBUTE_AMDONLY
XED_ATTRIBUTE_APX_NDD
XED_ATTRIBUTE_APX_NF
XED_ATTRIBUTE_ATOMIC
XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION
XED_ATTRIBUTE_BROADCAST_ENABLED
XED_ATTRIBUTE_BYTEOP
XED_ATTRIBUTE_DISP8_EIGHTHMEM
XED_ATTRIBUTE_DISP8_FULL
XED_ATTRIBUTE_DISP8_FULLMEM
XED_ATTRIBUTE_DISP8_GPR_READER
XED_ATTRIBUTE_DISP8_GPR_READER_BYTE
XED_ATTRIBUTE_DISP8_GPR_READER_WORD
XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D
XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q
XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE
XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE
XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD
XED_ATTRIBUTE_DISP8_GSCAT
XED_ATTRIBUTE_DISP8_HALF
XED_ATTRIBUTE_DISP8_HALFMEM
XED_ATTRIBUTE_DISP8_MEM128
XED_ATTRIBUTE_DISP8_MOVDDUP
XED_ATTRIBUTE_DISP8_NO_SCALE
XED_ATTRIBUTE_DISP8_QUARTER
XED_ATTRIBUTE_DISP8_QUARTERMEM
XED_ATTRIBUTE_DISP8_SCALAR
XED_ATTRIBUTE_DISP8_TUPLE1
XED_ATTRIBUTE_DISP8_TUPLE2
XED_ATTRIBUTE_DISP8_TUPLE4
XED_ATTRIBUTE_DISP8_TUPLE8
XED_ATTRIBUTE_DISP8_TUPLE1_4X
XED_ATTRIBUTE_DISP8_TUPLE1_BYTE
XED_ATTRIBUTE_DISP8_TUPLE1_WORD
XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP
XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT
XED_ATTRIBUTE_DWORD_INDICES
XED_ATTRIBUTE_ELEMENT_SIZE_D
XED_ATTRIBUTE_ELEMENT_SIZE_Q
XED_ATTRIBUTE_EXCEPTION_BR
XED_ATTRIBUTE_FAR_XFER
XED_ATTRIBUTE_FIXED_BASE0
XED_ATTRIBUTE_FIXED_BASE1
XED_ATTRIBUTE_FIXED_ROUNDING_RNE
XED_ATTRIBUTE_FLUSH_INPUT_DENORM
XED_ATTRIBUTE_FLUSH_OUTPUT_DENORM
XED_ATTRIBUTE_GATHER
XED_ATTRIBUTE_HALF_WIDE_OUTPUT
XED_ATTRIBUTE_HLE_ACQ_ABLE
XED_ATTRIBUTE_HLE_REL_ABLE
XED_ATTRIBUTE_IGNORES_OSFXSR
XED_ATTRIBUTE_IMPLICIT_ONE
XED_ATTRIBUTE_INDEX_REG_IS_POINTER
XED_ATTRIBUTE_INDIRECT_BRANCH
XED_ATTRIBUTE_INVALID
XED_ATTRIBUTE_KMASK
XED_ATTRIBUTE_LAST
XED_ATTRIBUTE_LOCKABLE
XED_ATTRIBUTE_LOCKED
XED_ATTRIBUTE_MASKOP
XED_ATTRIBUTE_MASKOP_EVEX
XED_ATTRIBUTE_MASK_AS_CONTROL
XED_ATTRIBUTE_MASK_VARIABLE_MEMOP
XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION
XED_ATTRIBUTE_MMX_EXCEPT
XED_ATTRIBUTE_MPX_PREFIX_ABLE
XED_ATTRIBUTE_MULTIDEST2
XED_ATTRIBUTE_MULTISOURCE4
XED_ATTRIBUTE_MXCSR
XED_ATTRIBUTE_MXCSR_RD
XED_ATTRIBUTE_NONTEMPORAL
XED_ATTRIBUTE_NOP
XED_ATTRIBUTE_NOTSX
XED_ATTRIBUTE_NOTSX_COND
XED_ATTRIBUTE_NO_REG_MATCH
XED_ATTRIBUTE_NO_RIP_REL
XED_ATTRIBUTE_NO_SRC_DEST_MATCH
XED_ATTRIBUTE_PREFETCH
XED_ATTRIBUTE_PROTECTED_MODE
XED_ATTRIBUTE_QWORD_INDICES
XED_ATTRIBUTE_REP
XED_ATTRIBUTE_REQUIRES_ALIGNMENT
XED_ATTRIBUTE_REQUIRES_ALIGNMENT_4B
XED_ATTRIBUTE_REQUIRES_ALIGNMENT_8B
XED_ATTRIBUTE_RING0
XED_ATTRIBUTE_SCALABLE
XED_ATTRIBUTE_SCATTER
XED_ATTRIBUTE_SIMD_SCALAR
XED_ATTRIBUTE_SKIPLOW32
XED_ATTRIBUTE_SKIPLOW64
XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED
XED_ATTRIBUTE_STACKPOP0
XED_ATTRIBUTE_STACKPOP1
XED_ATTRIBUTE_STACKPUSH0
XED_ATTRIBUTE_STACKPUSH1
XED_ATTRIBUTE_UNDOCUMENTED
XED_ATTRIBUTE_USES_DAZ
XED_ATTRIBUTE_USES_FTZ
XED_ATTRIBUTE_X87_CONTROL
XED_ATTRIBUTE_X87_MMX_STATE_CW
XED_ATTRIBUTE_X87_MMX_STATE_R
XED_ATTRIBUTE_X87_MMX_STATE_W
XED_ATTRIBUTE_X87_NOWAIT
XED_ATTRIBUTE_XMM_STATE_CW
XED_ATTRIBUTE_XMM_STATE_R
XED_ATTRIBUTE_XMM_STATE_W
XED_CATEGORY_3DNOW
XED_CATEGORY_ADOX_ADCX
XED_CATEGORY_AES
XED_CATEGORY_AMX_TILE
XED_CATEGORY_APX
XED_CATEGORY_AVX
XED_CATEGORY_AVX2
XED_CATEGORY_AVX2GATHER
XED_CATEGORY_AVX512
XED_CATEGORY_AVX512_4FMAPS
XED_CATEGORY_AVX512_4VNNIW
XED_CATEGORY_AVX512_BITALG
XED_CATEGORY_AVX512_VBMI
XED_CATEGORY_AVX512_VP2INTERSECT
XED_CATEGORY_AVX_IFMA
XED_CATEGORY_BINARY
XED_CATEGORY_BITBYTE
XED_CATEGORY_BLEND
XED_CATEGORY_BMI1
XED_CATEGORY_BMI2
XED_CATEGORY_BROADCAST
XED_CATEGORY_CALL
XED_CATEGORY_CET
XED_CATEGORY_CLDEMOTE
XED_CATEGORY_CLFLUSHOPT
XED_CATEGORY_CLWB
XED_CATEGORY_CLZERO
XED_CATEGORY_CMOV
XED_CATEGORY_COMPRESS
XED_CATEGORY_COND_BR
XED_CATEGORY_CONFLICT
XED_CATEGORY_CONVERT
XED_CATEGORY_DATAXFER
XED_CATEGORY_DECIMAL
XED_CATEGORY_ENQCMD
XED_CATEGORY_EXPAND
XED_CATEGORY_FCMOV
XED_CATEGORY_FLAGOP
XED_CATEGORY_FMA4
XED_CATEGORY_FP16
XED_CATEGORY_FRED
XED_CATEGORY_GATHER
XED_CATEGORY_GFNI
XED_CATEGORY_HRESET
XED_CATEGORY_IFMA
XED_CATEGORY_INTERRUPT
XED_CATEGORY_INVALID
XED_CATEGORY_IO
XED_CATEGORY_IOSTRINGOP
XED_CATEGORY_KEYLOCKER
XED_CATEGORY_KEYLOCKER_WIDE
XED_CATEGORY_KMASK
XED_CATEGORY_LAST
XED_CATEGORY_LEGACY
XED_CATEGORY_LKGS
XED_CATEGORY_LOGICAL
XED_CATEGORY_LOGICAL_FP
XED_CATEGORY_LZCNT
XED_CATEGORY_MISC
XED_CATEGORY_MMX
XED_CATEGORY_MOVDIR
XED_CATEGORY_MPX
XED_CATEGORY_MSRLIST
XED_CATEGORY_NOP
XED_CATEGORY_PBNDKB
XED_CATEGORY_PCLMULQDQ
XED_CATEGORY_PCONFIG
XED_CATEGORY_PKU
XED_CATEGORY_POP
XED_CATEGORY_PREFETCH
XED_CATEGORY_PREFETCHWT1
XED_CATEGORY_PTWRITE
XED_CATEGORY_PUSH
XED_CATEGORY_RDPID
XED_CATEGORY_RDPRU
XED_CATEGORY_RDRAND
XED_CATEGORY_RDSEED
XED_CATEGORY_RDWRFSGS
XED_CATEGORY_RET
XED_CATEGORY_ROTATE
XED_CATEGORY_SCATTER
XED_CATEGORY_SEGOP
XED_CATEGORY_SEMAPHORE
XED_CATEGORY_SERIALIZE
XED_CATEGORY_SETCC
XED_CATEGORY_SGX
XED_CATEGORY_SHA
XED_CATEGORY_SHA512
XED_CATEGORY_SHIFT
XED_CATEGORY_SMAP
XED_CATEGORY_SSE
XED_CATEGORY_STRINGOP
XED_CATEGORY_STTNI
XED_CATEGORY_SYSCALL
XED_CATEGORY_SYSRET
XED_CATEGORY_SYSTEM
XED_CATEGORY_TBM
XED_CATEGORY_TSX_LDTRK
XED_CATEGORY_UINTR
XED_CATEGORY_UNCOND_BR
XED_CATEGORY_USER_MSR
XED_CATEGORY_VAES
XED_CATEGORY_VBMI2
XED_CATEGORY_VEX
XED_CATEGORY_VFMA
XED_CATEGORY_VIA_PADLOCK
XED_CATEGORY_VPCLMULQDQ
XED_CATEGORY_VTX
XED_CATEGORY_WAITPKG
XED_CATEGORY_WIDENOP
XED_CATEGORY_WRMSRNS
XED_CATEGORY_X87_ALU
XED_CATEGORY_XOP
XED_CATEGORY_XSAVE
XED_CATEGORY_XSAVEOPT
XED_CHIP_ALDER_LAKE
XED_CHIP_ALL
XED_CHIP_ALLREAL
XED_CHIP_AMD_BULLDOZER
XED_CHIP_AMD_FUTURE
XED_CHIP_AMD_K10
XED_CHIP_AMD_PILEDRIVER
XED_CHIP_AMD_ZEN
XED_CHIP_AMD_ZEN2
XED_CHIP_AMD_ZENPLUS
XED_CHIP_ARROW_LAKE
XED_CHIP_BONNELL
XED_CHIP_BROADWELL
XED_CHIP_CANNONLAKE
XED_CHIP_CASCADE_LAKE
XED_CHIP_CLEARWATER_FOREST
XED_CHIP_COMET_LAKE
XED_CHIP_COOPER_LAKE
XED_CHIP_EMERALD_RAPIDS
XED_CHIP_FUTURE
XED_CHIP_GOLDMONT
XED_CHIP_GOLDMONT_PLUS
XED_CHIP_GRANITE_RAPIDS
XED_CHIP_HASWELL
XED_CHIP_I86
XED_CHIP_I86FP
XED_CHIP_I186
XED_CHIP_I286
XED_CHIP_I386
XED_CHIP_I486
XED_CHIP_I186FP
XED_CHIP_I286REAL
XED_CHIP_I386FP
XED_CHIP_I386REAL
XED_CHIP_I486REAL
XED_CHIP_I2186FP
XED_CHIP_ICE_LAKE
XED_CHIP_ICE_LAKE_SERVER
XED_CHIP_INVALID
XED_CHIP_IVYBRIDGE
XED_CHIP_KNL
XED_CHIP_KNM
XED_CHIP_LAKEFIELD
XED_CHIP_LAST
XED_CHIP_LUNAR_LAKE
XED_CHIP_MEROM
XED_CHIP_NEHALEM
XED_CHIP_P4PRESCOTT
XED_CHIP_P4PRESCOTT_NOLAHF
XED_CHIP_P4PRESCOTT_VTX
XED_CHIP_PANTHER_LAKE
XED_CHIP_PENRYN
XED_CHIP_PENRYN_E
XED_CHIP_PENTIUM
XED_CHIP_PENTIUM2
XED_CHIP_PENTIUM3
XED_CHIP_PENTIUM4
XED_CHIP_PENTIUMMMX
XED_CHIP_PENTIUMMMXREAL
XED_CHIP_PENTIUMPRO
XED_CHIP_PENTIUMREAL
XED_CHIP_QUARK
XED_CHIP_SALTWELL
XED_CHIP_SANDYBRIDGE
XED_CHIP_SAPPHIRE_RAPIDS
XED_CHIP_SIERRA_FOREST
XED_CHIP_SILVERMONT
XED_CHIP_SKYLAKE
XED_CHIP_SKYLAKE_SERVER
XED_CHIP_SNOW_RIDGE
XED_CHIP_TIGER_LAKE
XED_CHIP_TREMONT
XED_CHIP_VIA
XED_CHIP_WESTMERE
XED_CPUID_GROUP_ADOX_ADCX
XED_CPUID_GROUP_AES
XED_CPUID_GROUP_AMX_BF16
XED_CPUID_GROUP_AMX_COMPLEX
XED_CPUID_GROUP_AMX_FP16
XED_CPUID_GROUP_AMX_INT8
XED_CPUID_GROUP_AMX_TILE
XED_CPUID_GROUP_APX_F
XED_CPUID_GROUP_APX_F_ADX
XED_CPUID_GROUP_APX_F_AMX
XED_CPUID_GROUP_APX_F_BMI1
XED_CPUID_GROUP_APX_F_BMI2
XED_CPUID_GROUP_APX_F_CET
XED_CPUID_GROUP_APX_F_CMPCCXADD
XED_CPUID_GROUP_APX_F_ENQCMD
XED_CPUID_GROUP_APX_F_INVPCID
XED_CPUID_GROUP_APX_F_KOPB
XED_CPUID_GROUP_APX_F_KOPB_AVX10
XED_CPUID_GROUP_APX_F_KOPD
XED_CPUID_GROUP_APX_F_KOPD_AVX10
XED_CPUID_GROUP_APX_F_KOPQ
XED_CPUID_GROUP_APX_F_KOPQ_AVX10
XED_CPUID_GROUP_APX_F_KOPW
XED_CPUID_GROUP_APX_F_KOPW_AVX10
XED_CPUID_GROUP_APX_F_LZCNT
XED_CPUID_GROUP_APX_F_MOVBE
XED_CPUID_GROUP_APX_F_MOVDIR64B
XED_CPUID_GROUP_APX_F_MOVDIRI
XED_CPUID_GROUP_APX_F_POPCNT
XED_CPUID_GROUP_APX_F_RAO_INT
XED_CPUID_GROUP_APX_F_USER_MSR
XED_CPUID_GROUP_APX_F_VMX
XED_CPUID_GROUP_AVX
XED_CPUID_GROUP_AVX2
XED_CPUID_GROUP_AVX2GATHER
XED_CPUID_GROUP_AVX512BW_128
XED_CPUID_GROUP_AVX512BW_256
XED_CPUID_GROUP_AVX512BW_512
XED_CPUID_GROUP_AVX512BW_128N
XED_CPUID_GROUP_AVX512BW_128N_AVX10
XED_CPUID_GROUP_AVX512BW_128_AVX10
XED_CPUID_GROUP_AVX512BW_256_AVX10
XED_CPUID_GROUP_AVX512BW_512_AVX10
XED_CPUID_GROUP_AVX512BW_KOPD
XED_CPUID_GROUP_AVX512BW_KOPD_AVX10
XED_CPUID_GROUP_AVX512BW_KOPQ
XED_CPUID_GROUP_AVX512BW_KOPQ_AVX10
XED_CPUID_GROUP_AVX512CD_128
XED_CPUID_GROUP_AVX512CD_256
XED_CPUID_GROUP_AVX512CD_512
XED_CPUID_GROUP_AVX512CD_128_AVX10
XED_CPUID_GROUP_AVX512CD_256_AVX10
XED_CPUID_GROUP_AVX512CD_512_AVX10
XED_CPUID_GROUP_AVX512DQ_128
XED_CPUID_GROUP_AVX512DQ_256
XED_CPUID_GROUP_AVX512DQ_512
XED_CPUID_GROUP_AVX512DQ_128N
XED_CPUID_GROUP_AVX512DQ_128N_AVX10
XED_CPUID_GROUP_AVX512DQ_128_AVX10
XED_CPUID_GROUP_AVX512DQ_256_AVX10
XED_CPUID_GROUP_AVX512DQ_512_AVX10
XED_CPUID_GROUP_AVX512DQ_KOPB
XED_CPUID_GROUP_AVX512DQ_KOPB_AVX10
XED_CPUID_GROUP_AVX512DQ_KOPW
XED_CPUID_GROUP_AVX512DQ_KOPW_AVX10
XED_CPUID_GROUP_AVX512DQ_SCALAR
XED_CPUID_GROUP_AVX512DQ_SCALAR_AVX10
XED_CPUID_GROUP_AVX512ER_512
XED_CPUID_GROUP_AVX512ER_SCALAR
XED_CPUID_GROUP_AVX512F_128
XED_CPUID_GROUP_AVX512F_256
XED_CPUID_GROUP_AVX512F_512
XED_CPUID_GROUP_AVX512F_128N
XED_CPUID_GROUP_AVX512F_128N_AVX10
XED_CPUID_GROUP_AVX512F_128_AVX10
XED_CPUID_GROUP_AVX512F_256_AVX10
XED_CPUID_GROUP_AVX512F_512_AVX10
XED_CPUID_GROUP_AVX512F_KOPW
XED_CPUID_GROUP_AVX512F_KOPW_AVX10
XED_CPUID_GROUP_AVX512F_SCALAR
XED_CPUID_GROUP_AVX512F_SCALAR_AVX10
XED_CPUID_GROUP_AVX512PF_512
XED_CPUID_GROUP_AVX512_4FMAPS_512
XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR
XED_CPUID_GROUP_AVX512_4VNNIW_512
XED_CPUID_GROUP_AVX512_BF16_128
XED_CPUID_GROUP_AVX512_BF16_256
XED_CPUID_GROUP_AVX512_BF16_512
XED_CPUID_GROUP_AVX512_BF16_128_AVX10
XED_CPUID_GROUP_AVX512_BF16_256_AVX10
XED_CPUID_GROUP_AVX512_BF16_512_AVX10
XED_CPUID_GROUP_AVX512_BITALG_128
XED_CPUID_GROUP_AVX512_BITALG_256
XED_CPUID_GROUP_AVX512_BITALG_512
XED_CPUID_GROUP_AVX512_BITALG_128_AVX10
XED_CPUID_GROUP_AVX512_BITALG_256_AVX10
XED_CPUID_GROUP_AVX512_BITALG_512_AVX10
XED_CPUID_GROUP_AVX512_FP16_128
XED_CPUID_GROUP_AVX512_FP16_256
XED_CPUID_GROUP_AVX512_FP16_512
XED_CPUID_GROUP_AVX512_FP16_128N
XED_CPUID_GROUP_AVX512_FP16_128N_AVX10
XED_CPUID_GROUP_AVX512_FP16_128_AVX10
XED_CPUID_GROUP_AVX512_FP16_256_AVX10
XED_CPUID_GROUP_AVX512_FP16_512_AVX10
XED_CPUID_GROUP_AVX512_FP16_SCALAR
XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10
XED_CPUID_GROUP_AVX512_GFNI_128
XED_CPUID_GROUP_AVX512_GFNI_256
XED_CPUID_GROUP_AVX512_GFNI_512
XED_CPUID_GROUP_AVX512_GFNI_128_AVX10
XED_CPUID_GROUP_AVX512_GFNI_256_AVX10
XED_CPUID_GROUP_AVX512_GFNI_512_AVX10
XED_CPUID_GROUP_AVX512_IFMA_128
XED_CPUID_GROUP_AVX512_IFMA_256
XED_CPUID_GROUP_AVX512_IFMA_512
XED_CPUID_GROUP_AVX512_IFMA_128_AVX10
XED_CPUID_GROUP_AVX512_IFMA_256_AVX10
XED_CPUID_GROUP_AVX512_IFMA_512_AVX10
XED_CPUID_GROUP_AVX512_VAES_128
XED_CPUID_GROUP_AVX512_VAES_256
XED_CPUID_GROUP_AVX512_VAES_512
XED_CPUID_GROUP_AVX512_VAES_128_AVX10
XED_CPUID_GROUP_AVX512_VAES_256_AVX10
XED_CPUID_GROUP_AVX512_VAES_512_AVX10
XED_CPUID_GROUP_AVX512_VBMI2_128
XED_CPUID_GROUP_AVX512_VBMI2_256
XED_CPUID_GROUP_AVX512_VBMI2_512
XED_CPUID_GROUP_AVX512_VBMI2_128_AVX10
XED_CPUID_GROUP_AVX512_VBMI2_256_AVX10
XED_CPUID_GROUP_AVX512_VBMI2_512_AVX10
XED_CPUID_GROUP_AVX512_VBMI_128
XED_CPUID_GROUP_AVX512_VBMI_256
XED_CPUID_GROUP_AVX512_VBMI_512
XED_CPUID_GROUP_AVX512_VBMI_128_AVX10
XED_CPUID_GROUP_AVX512_VBMI_256_AVX10
XED_CPUID_GROUP_AVX512_VBMI_512_AVX10
XED_CPUID_GROUP_AVX512_VNNI_128
XED_CPUID_GROUP_AVX512_VNNI_256
XED_CPUID_GROUP_AVX512_VNNI_512
XED_CPUID_GROUP_AVX512_VNNI_128_AVX10
XED_CPUID_GROUP_AVX512_VNNI_256_AVX10
XED_CPUID_GROUP_AVX512_VNNI_512_AVX10
XED_CPUID_GROUP_AVX512_VP2INTERSECT_128
XED_CPUID_GROUP_AVX512_VP2INTERSECT_256
XED_CPUID_GROUP_AVX512_VP2INTERSECT_512
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_128
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_256
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_512
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_128_AVX10
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_256_AVX10
XED_CPUID_GROUP_AVX512_VPCLMULQDQ_512_AVX10
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_128
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_256
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_512
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_128_AVX10
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_256_AVX10
XED_CPUID_GROUP_AVX512_VPOPCNTDQ_512_AVX10
XED_CPUID_GROUP_AVXAES
XED_CPUID_GROUP_AVX_GFNI
XED_CPUID_GROUP_AVX_IFMA
XED_CPUID_GROUP_AVX_NE_CONVERT
XED_CPUID_GROUP_AVX_VNNI
XED_CPUID_GROUP_AVX_VNNI_INT8
XED_CPUID_GROUP_AVX_VNNI_INT16
XED_CPUID_GROUP_BMI1
XED_CPUID_GROUP_BMI2
XED_CPUID_GROUP_CET
XED_CPUID_GROUP_CLDEMOTE
XED_CPUID_GROUP_CLFLUSHOPT
XED_CPUID_GROUP_CLFSH
XED_CPUID_GROUP_CLWB
XED_CPUID_GROUP_CMOV
XED_CPUID_GROUP_CMPCCXADD
XED_CPUID_GROUP_CMPXCHG16B
XED_CPUID_GROUP_ENQCMD
XED_CPUID_GROUP_F16C
XED_CPUID_GROUP_FCMOV
XED_CPUID_GROUP_FCOMI
XED_CPUID_GROUP_FMA
XED_CPUID_GROUP_FRED
XED_CPUID_GROUP_FXSAVE
XED_CPUID_GROUP_FXSAVE64
XED_CPUID_GROUP_GFNI
XED_CPUID_GROUP_HRESET
XED_CPUID_GROUP_ICACHE_PREFETCH
XED_CPUID_GROUP_INVALID
XED_CPUID_GROUP_INVPCID
XED_CPUID_GROUP_KEYLOCKER
XED_CPUID_GROUP_KEYLOCKER_WIDE
XED_CPUID_GROUP_LAHF
XED_CPUID_GROUP_LAST
XED_CPUID_GROUP_LKGS
XED_CPUID_GROUP_LONGMODE
XED_CPUID_GROUP_LZCNT
XED_CPUID_GROUP_MCOMMIT
XED_CPUID_GROUP_MONITOR
XED_CPUID_GROUP_MONITORX
XED_CPUID_GROUP_MOVBE
XED_CPUID_GROUP_MOVDIR64B
XED_CPUID_GROUP_MOVDIRI
XED_CPUID_GROUP_MPX
XED_CPUID_GROUP_MSRLIST
XED_CPUID_GROUP_PBNDKB
XED_CPUID_GROUP_PCLMULQDQ
XED_CPUID_GROUP_PCONFIG
XED_CPUID_GROUP_PENTIUMMMX
XED_CPUID_GROUP_PKU
XED_CPUID_GROUP_POPCNT
XED_CPUID_GROUP_PREFETCHW
XED_CPUID_GROUP_PREFETCHWT1
XED_CPUID_GROUP_PTWRITE
XED_CPUID_GROUP_RAO_INT
XED_CPUID_GROUP_RDPID
XED_CPUID_GROUP_RDPRU
XED_CPUID_GROUP_RDRAND
XED_CPUID_GROUP_RDSEED
XED_CPUID_GROUP_RDTSCP
XED_CPUID_GROUP_RDWRFSGS
XED_CPUID_GROUP_RTM
XED_CPUID_GROUP_SEP
XED_CPUID_GROUP_SERIALIZE
XED_CPUID_GROUP_SGX
XED_CPUID_GROUP_SHA
XED_CPUID_GROUP_SHA512
XED_CPUID_GROUP_SM3
XED_CPUID_GROUP_SM4
XED_CPUID_GROUP_SMAP
XED_CPUID_GROUP_SMX
XED_CPUID_GROUP_SNP
XED_CPUID_GROUP_SSE
XED_CPUID_GROUP_SSE2
XED_CPUID_GROUP_SSE3
XED_CPUID_GROUP_SSE4
XED_CPUID_GROUP_SSE2MMX
XED_CPUID_GROUP_SSE3X87
XED_CPUID_GROUP_SSE4A
XED_CPUID_GROUP_SSE42
XED_CPUID_GROUP_SSEMXCSR
XED_CPUID_GROUP_SSSE3
XED_CPUID_GROUP_SSSE3MMX
XED_CPUID_GROUP_TSX_LDTRK
XED_CPUID_GROUP_UINTR
XED_CPUID_GROUP_USER_MSR
XED_CPUID_GROUP_VAES
XED_CPUID_GROUP_VIA_PADLOCK_AES
XED_CPUID_GROUP_VIA_PADLOCK_MONTMUL
XED_CPUID_GROUP_VIA_PADLOCK_RNG
XED_CPUID_GROUP_VIA_PADLOCK_SHA
XED_CPUID_GROUP_VPCLMULQDQ
XED_CPUID_GROUP_VTX
XED_CPUID_GROUP_WAITPKG
XED_CPUID_GROUP_WBNOINVD
XED_CPUID_GROUP_WRMSRNS
XED_CPUID_GROUP_XSAVE
XED_CPUID_GROUP_XSAVEC
XED_CPUID_GROUP_XSAVEOPT
XED_CPUID_GROUP_XSAVES
XED_CPUID_REC_ADOXADCX
XED_CPUID_REC_AES
XED_CPUID_REC_AMX_BF16
XED_CPUID_REC_AMX_COMPLEX
XED_CPUID_REC_AMX_FP16
XED_CPUID_REC_AMX_INT8
XED_CPUID_REC_AMX_TILES
XED_CPUID_REC_APX_F
XED_CPUID_REC_AVX
XED_CPUID_REC_AVX2
XED_CPUID_REC_AVX10_128VL
XED_CPUID_REC_AVX10_256VL
XED_CPUID_REC_AVX10_512VL
XED_CPUID_REC_AVX10_ENABLED
XED_CPUID_REC_AVX10_VER1
XED_CPUID_REC_AVX512BW
XED_CPUID_REC_AVX512CD
XED_CPUID_REC_AVX512DQ
XED_CPUID_REC_AVX512ER
XED_CPUID_REC_AVX512F
XED_CPUID_REC_AVX512IFMA
XED_CPUID_REC_AVX512PF
XED_CPUID_REC_AVX512VBMI
XED_CPUID_REC_AVX512VL
XED_CPUID_REC_AVX512_4FMAPS
XED_CPUID_REC_AVX512_4VNNIW
XED_CPUID_REC_AVX512_BITALG
XED_CPUID_REC_AVX512_FP16
XED_CPUID_REC_AVX512_VBMI2
XED_CPUID_REC_AVX512_VNNI
XED_CPUID_REC_AVX512_VP2INTERSECT
XED_CPUID_REC_AVX512_VPOPCNTDQ
XED_CPUID_REC_AVX_IFMA
XED_CPUID_REC_AVX_NE_CONVERT
XED_CPUID_REC_AVX_VNNI
XED_CPUID_REC_AVX_VNNI_INT8
XED_CPUID_REC_AVX_VNNI_INT16
XED_CPUID_REC_BF16
XED_CPUID_REC_BMI1
XED_CPUID_REC_BMI2
XED_CPUID_REC_CET
XED_CPUID_REC_CLDEMOTE
XED_CPUID_REC_CLFLUSH
XED_CPUID_REC_CLFLUSHOPT
XED_CPUID_REC_CLWB
XED_CPUID_REC_CMOV
XED_CPUID_REC_CMPCCXADD
XED_CPUID_REC_CMPXCHG16B
XED_CPUID_REC_ENQCMD
XED_CPUID_REC_F16C
XED_CPUID_REC_FMA
XED_CPUID_REC_FPU
XED_CPUID_REC_FRED
XED_CPUID_REC_FXSAVE
XED_CPUID_REC_GFNI
XED_CPUID_REC_HRESET
XED_CPUID_REC_ICACHE_PREFETCH
XED_CPUID_REC_INTEL64
XED_CPUID_REC_INTELPT
XED_CPUID_REC_INVALID
XED_CPUID_REC_INVPCID
XED_CPUID_REC_KLENABLED
XED_CPUID_REC_KLSUPPORTED
XED_CPUID_REC_KLWIDE
XED_CPUID_REC_LAHF
XED_CPUID_REC_LAST
XED_CPUID_REC_LKGS
XED_CPUID_REC_LZCNT
XED_CPUID_REC_MCOMMIT
XED_CPUID_REC_MMX
XED_CPUID_REC_MONITOR
XED_CPUID_REC_MONITORX
XED_CPUID_REC_MOVDIR64B
XED_CPUID_REC_MOVDIRI
XED_CPUID_REC_MOVEBE
XED_CPUID_REC_MPX
XED_CPUID_REC_MSRLIST
XED_CPUID_REC_OSPKU
XED_CPUID_REC_OSXSAVE
XED_CPUID_REC_PBNDKB
XED_CPUID_REC_PCLMULQDQ
XED_CPUID_REC_PCONFIG
XED_CPUID_REC_PKU
XED_CPUID_REC_POPCNT
XED_CPUID_REC_PREFETCHW
XED_CPUID_REC_PREFETCHWT1
XED_CPUID_REC_PTWRITE
XED_CPUID_REC_RAO_INT
XED_CPUID_REC_RDP
XED_CPUID_REC_RDPRU
XED_CPUID_REC_RDRAND
XED_CPUID_REC_RDSEED
XED_CPUID_REC_RDTSCP
XED_CPUID_REC_RDWRFSGS
XED_CPUID_REC_RTM
XED_CPUID_REC_SEP
XED_CPUID_REC_SERIALIZE
XED_CPUID_REC_SGX
XED_CPUID_REC_SHA
XED_CPUID_REC_SHA512
XED_CPUID_REC_SM3
XED_CPUID_REC_SM4
XED_CPUID_REC_SMAP
XED_CPUID_REC_SMX
XED_CPUID_REC_SNP
XED_CPUID_REC_SSE
XED_CPUID_REC_SSE2
XED_CPUID_REC_SSE3
XED_CPUID_REC_SSE4
XED_CPUID_REC_SSE4A
XED_CPUID_REC_SSE42
XED_CPUID_REC_SSSE3
XED_CPUID_REC_TSX_LDTRK
XED_CPUID_REC_UINTR
XED_CPUID_REC_USER_MSR
XED_CPUID_REC_VAES
XED_CPUID_REC_VIA_PADLOCK_AES
XED_CPUID_REC_VIA_PADLOCK_AES_EN
XED_CPUID_REC_VIA_PADLOCK_PMM
XED_CPUID_REC_VIA_PADLOCK_PMM_EN
XED_CPUID_REC_VIA_PADLOCK_RNG
XED_CPUID_REC_VIA_PADLOCK_RNG_EN
XED_CPUID_REC_VIA_PADLOCK_SHA
XED_CPUID_REC_VIA_PADLOCK_SHA_EN
XED_CPUID_REC_VMX
XED_CPUID_REC_VPCLMULQDQ
XED_CPUID_REC_WAITPKG
XED_CPUID_REC_WBNOINVD
XED_CPUID_REC_WRMSRNS
XED_CPUID_REC_XSAVE
XED_CPUID_REC_XSAVEC
XED_CPUID_REC_XSAVEOPT
XED_CPUID_REC_XSAVES
XED_EMIT_MESSAGES
XED_ENCODER_OPERANDS_MAX
XED_ENCODER_OPERAND_TYPE_ABS_BRDISP
XED_ENCODER_OPERAND_TYPE_IMM0
XED_ENCODER_OPERAND_TYPE_IMM1
XED_ENCODER_OPERAND_TYPE_INVALID
XED_ENCODER_OPERAND_TYPE_MEM
XED_ENCODER_OPERAND_TYPE_OTHER
XED_ENCODER_OPERAND_TYPE_PTR
XED_ENCODER_OPERAND_TYPE_REG
XED_ENCODER_OPERAND_TYPE_REL_BRDISP
XED_ENCODER_OPERAND_TYPE_SEG0
XED_ENCODER_OPERAND_TYPE_SEG1
XED_ENCODER_OPERAND_TYPE_SIMM0
XED_ENCODE_FB_VALUES_TABLE_SIZE
XED_ENCODE_MAX_EMIT_PATTERNS
XED_ENCODE_MAX_FB_PATTERNS
XED_ENCODE_MAX_IFORMS
XED_ENCODE_ORDER_MAX_ENTRIES
XED_ENCODE_ORDER_MAX_OPERANDS
XED_ENC_GROUPS
XED_ERROR_BAD_EVEX_LL: < EVEX.LL must not ==3 unless using embedded rounding
XED_ERROR_BAD_EVEX_V_PRIME: < EVEX.V’=0 was detected in a non-64b mode instruction.
XED_ERROR_BAD_EVEX_Z_NO_MASKING: < EVEX.Z!=0 when EVEX.aaa==0
XED_ERROR_BAD_LEGACY_PREFIX: < A 66, F2 or F3 prefix was found where none is allowed.
XED_ERROR_BAD_LOCK_PREFIX: < A lock prefix was found where none is allowed.
XED_ERROR_BAD_MAP: < An illegal value for the MAP field was detected in the instruction.
XED_ERROR_BAD_MEMOP_INDEX: < Memop indices must be 0 or 1.
XED_ERROR_BAD_REGISTER: < XED could not decode the given instruction because an invalid register encoding was used.
XED_ERROR_BAD_REG_MATCH: < Some registers must not match for this instruction (e.g. source with dest or dest with dest).
XED_ERROR_BAD_REP_PREFIX: < An F2 or F3 prefix was found where none is allowed.
XED_ERROR_BAD_REX_PREFIX: < A REX prefix was found where none is allowed.
XED_ERROR_BUFFER_TOO_SHORT: < There were not enough bytes in the given buffer
XED_ERROR_CALLBACK_PROBLEM: < The register or segment callback for xed_agen experienced a problem
XED_ERROR_GATHER_REGS: < The index, dest and mask regs for AVX2 gathers must be different.
XED_ERROR_GENERAL_ERROR: < XED could not decode the given instruction
XED_ERROR_INSTR_TOO_LONG: < Full decode of instruction would exeed 15B.
XED_ERROR_INVALID_FOR_CHIP: < The instruciton is not valid for the specified chip
XED_ERROR_INVALID_MODE: < The instruction was not valid for the specified mode
XED_ERROR_LAST
XED_ERROR_NONE: < There was no error
XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED: < One or both of the callbacks for xed_agen were missing.
XED_ERROR_NO_OUTPUT_POINTER: < The output pointer for xed_agen was zero
XED_EXCEPTION_AMX_E1
XED_EXCEPTION_AMX_E2
XED_EXCEPTION_AMX_E3
XED_EXCEPTION_AMX_E4
XED_EXCEPTION_AMX_E5
XED_EXCEPTION_AMX_E6
XED_EXCEPTION_AMX_E1_EVEX
XED_EXCEPTION_AMX_E2_EVEX
XED_EXCEPTION_AMX_E3_EVEX
XED_EXCEPTION_APX_EVEX_BMI
XED_EXCEPTION_APX_EVEX_CCMP
XED_EXCEPTION_APX_EVEX_CET_WRSS
XED_EXCEPTION_APX_EVEX_CET_WRUSS
XED_EXCEPTION_APX_EVEX_CFCMOV
XED_EXCEPTION_APX_EVEX_CMPCCXADD
XED_EXCEPTION_APX_EVEX_ENQCMD
XED_EXCEPTION_APX_EVEX_INT
XED_EXCEPTION_APX_EVEX_INVEPT
XED_EXCEPTION_APX_EVEX_INVPCID
XED_EXCEPTION_APX_EVEX_INVVPID
XED_EXCEPTION_APX_EVEX_KMOV
XED_EXCEPTION_APX_EVEX_PP2
XED_EXCEPTION_APX_EVEX_RAO_INT
XED_EXCEPTION_APX_LEGACY_JMPABS
XED_EXCEPTION_AVX512_E1
XED_EXCEPTION_AVX512_E2
XED_EXCEPTION_AVX512_E3
XED_EXCEPTION_AVX512_E4
XED_EXCEPTION_AVX512_E5
XED_EXCEPTION_AVX512_E6
XED_EXCEPTION_AVX512_E1NF
XED_EXCEPTION_AVX512_E3NF
XED_EXCEPTION_AVX512_E4NF
XED_EXCEPTION_AVX512_E5NF
XED_EXCEPTION_AVX512_E6NF
XED_EXCEPTION_AVX512_E7NM
XED_EXCEPTION_AVX512_E7NM128
XED_EXCEPTION_AVX512_E9NF
XED_EXCEPTION_AVX512_E10
XED_EXCEPTION_AVX512_E11
XED_EXCEPTION_AVX512_E12
XED_EXCEPTION_AVX512_E10NF
XED_EXCEPTION_AVX512_E12NP
XED_EXCEPTION_AVX512_K20
XED_EXCEPTION_AVX512_K21
XED_EXCEPTION_AVX_TYPE_1
XED_EXCEPTION_AVX_TYPE_2
XED_EXCEPTION_AVX_TYPE_3
XED_EXCEPTION_AVX_TYPE_4
XED_EXCEPTION_AVX_TYPE_5
XED_EXCEPTION_AVX_TYPE_6
XED_EXCEPTION_AVX_TYPE_7
XED_EXCEPTION_AVX_TYPE_8
XED_EXCEPTION_AVX_TYPE_2D
XED_EXCEPTION_AVX_TYPE_4M
XED_EXCEPTION_AVX_TYPE_5L
XED_EXCEPTION_AVX_TYPE_11
XED_EXCEPTION_AVX_TYPE_12
XED_EXCEPTION_AVX_TYPE_14
XED_EXCEPTION_INVALID
XED_EXCEPTION_LAST
XED_EXCEPTION_LEGACY_RAO_INT
XED_EXCEPTION_MMX_FP
XED_EXCEPTION_MMX_FP_16ALIGN
XED_EXCEPTION_MMX_MEM
XED_EXCEPTION_MMX_NOFP
XED_EXCEPTION_MMX_NOFP2
XED_EXCEPTION_MMX_NOMEM
XED_EXCEPTION_SSE_TYPE_1
XED_EXCEPTION_SSE_TYPE_2
XED_EXCEPTION_SSE_TYPE_3
XED_EXCEPTION_SSE_TYPE_4
XED_EXCEPTION_SSE_TYPE_5
XED_EXCEPTION_SSE_TYPE_7
XED_EXCEPTION_SSE_TYPE_2D
XED_EXCEPTION_SSE_TYPE_4M
XED_EXCEPTION_USER_MSR_EVEX
XED_EXCEPTION_USER_MSR_LEGACY
XED_EXCEPTION_USER_MSR_VEX
XED_EXTENSION_3DNOW
XED_EXTENSION_3DNOW_PREFETCH
XED_EXTENSION_ADOX_ADCX
XED_EXTENSION_AES
XED_EXTENSION_AMD_INVLPGB
XED_EXTENSION_AMX_TILE
XED_EXTENSION_APXEVEX
XED_EXTENSION_APXLEGACY
XED_EXTENSION_AVX
XED_EXTENSION_AVX2
XED_EXTENSION_AVX2GATHER
XED_EXTENSION_AVX512EVEX
XED_EXTENSION_AVX512VEX
XED_EXTENSION_AVXAES
XED_EXTENSION_AVX_IFMA
XED_EXTENSION_AVX_NE_CONVERT
XED_EXTENSION_AVX_VNNI
XED_EXTENSION_AVX_VNNI_INT8
XED_EXTENSION_AVX_VNNI_INT16
XED_EXTENSION_BASE
XED_EXTENSION_BMI1
XED_EXTENSION_BMI2
XED_EXTENSION_CET
XED_EXTENSION_CLDEMOTE
XED_EXTENSION_CLFLUSHOPT
XED_EXTENSION_CLFSH
XED_EXTENSION_CLWB
XED_EXTENSION_CLZERO
XED_EXTENSION_CMPCCXADD
XED_EXTENSION_ENQCMD
XED_EXTENSION_F16C
XED_EXTENSION_FMA
XED_EXTENSION_FMA4
XED_EXTENSION_FRED
XED_EXTENSION_GFNI
XED_EXTENSION_HRESET
XED_EXTENSION_ICACHE_PREFETCH
XED_EXTENSION_INVALID
XED_EXTENSION_INVPCID
XED_EXTENSION_KEYLOCKER
XED_EXTENSION_KEYLOCKER_WIDE
XED_EXTENSION_LAST
XED_EXTENSION_LKGS
XED_EXTENSION_LONGMODE
XED_EXTENSION_LZCNT
XED_EXTENSION_MCOMMIT
XED_EXTENSION_MMX
XED_EXTENSION_MONITOR
XED_EXTENSION_MONITORX
XED_EXTENSION_MOVBE
XED_EXTENSION_MOVDIR
XED_EXTENSION_MPX
XED_EXTENSION_MSRLIST
XED_EXTENSION_PAUSE
XED_EXTENSION_PBNDKB
XED_EXTENSION_PCLMULQDQ
XED_EXTENSION_PCONFIG
XED_EXTENSION_PKU
XED_EXTENSION_PREFETCHWT1
XED_EXTENSION_PTWRITE
XED_EXTENSION_RAO_INT
XED_EXTENSION_RDPID
XED_EXTENSION_RDPRU
XED_EXTENSION_RDRAND
XED_EXTENSION_RDSEED
XED_EXTENSION_RDTSCP
XED_EXTENSION_RDWRFSGS
XED_EXTENSION_RTM
XED_EXTENSION_SERIALIZE
XED_EXTENSION_SGX
XED_EXTENSION_SGX_ENCLV
XED_EXTENSION_SHA
XED_EXTENSION_SHA512
XED_EXTENSION_SM3
XED_EXTENSION_SM4
XED_EXTENSION_SMAP
XED_EXTENSION_SMX
XED_EXTENSION_SNP
XED_EXTENSION_SSE
XED_EXTENSION_SSE2
XED_EXTENSION_SSE3
XED_EXTENSION_SSE4
XED_EXTENSION_SSE4A
XED_EXTENSION_SSSE3
XED_EXTENSION_SVM
XED_EXTENSION_TBM
XED_EXTENSION_TDX
XED_EXTENSION_TSX_LDTRK
XED_EXTENSION_UINTR
XED_EXTENSION_USER_MSR
XED_EXTENSION_VAES
XED_EXTENSION_VIA_PADLOCK_AES
XED_EXTENSION_VIA_PADLOCK_MONTMUL
XED_EXTENSION_VIA_PADLOCK_RNG
XED_EXTENSION_VIA_PADLOCK_SHA
XED_EXTENSION_VMFUNC
XED_EXTENSION_VPCLMULQDQ
XED_EXTENSION_VTX
XED_EXTENSION_WAITPKG
XED_EXTENSION_WBNOINVD
XED_EXTENSION_WRMSRNS
XED_EXTENSION_X87
XED_EXTENSION_XOP
XED_EXTENSION_XSAVE
XED_EXTENSION_XSAVEC
XED_EXTENSION_XSAVEOPT
XED_EXTENSION_XSAVES
XED_FEATURE_VECTOR_MAX
XED_FLAG_ACTION_0: < value will be zero (write)
XED_FLAG_ACTION_1: < value will be 1 (write)
XED_FLAG_ACTION_INVALID
XED_FLAG_ACTION_LAST
XED_FLAG_ACTION_ah: < value comes from AH (write)
XED_FLAG_ACTION_mod: < modification (write)
XED_FLAG_ACTION_pop: < value comes from the stack (write)
XED_FLAG_ACTION_tst: < test (read)
XED_FLAG_ACTION_u: < undefined (treated as a write)
XED_FLAG_INVALID
XED_FLAG_LAST
XED_FLAG_ac: < alignment check
XED_FLAG_af: < auxiliary flag
XED_FLAG_cf: < carry flag
XED_FLAG_df: < direction flag
XED_FLAG_fc0: < x87 FC0 flag
XED_FLAG_fc1: < x87 FC1 flag
XED_FLAG_fc2: < x87 FC2 flag
XED_FLAG_fc3: < x87 FC3 flag
XED_FLAG_id: < ID flag
XED_FLAG_if: < interrupt flag
XED_FLAG_iopl: < I/O privilege level
XED_FLAG_nt: < nested task
XED_FLAG_of: << overflow flag
XED_FLAG_pf: < parity flag
XED_FLAG_rf: < resume flag
XED_FLAG_sf: < sign flag
XED_FLAG_tf: < traf flag
XED_FLAG_vif: < virtual interrupt flag
XED_FLAG_vip: < virtual interrupt pending
XED_FLAG_vm: < virtual-8086 mode
XED_FLAG_zf: < zero flag
XED_FMT_08X
XED_FMT_9U
XED_FMT_D
XED_FMT_LD
XED_FMT_LU
XED_FMT_LU12
XED_FMT_LX
XED_FMT_LX16
XED_FMT_LX16_UPPER
XED_FMT_LX_UPPER
XED_FMT_SIZET
XED_FMT_U
XED_FMT_X
XED_ICLASS_AAA
XED_ICLASS_AAD
XED_ICLASS_AADD
XED_ICLASS_AAM
XED_ICLASS_AAND
XED_ICLASS_AAS
XED_ICLASS_ADC
XED_ICLASS_ADCX
XED_ICLASS_ADC_LOCK
XED_ICLASS_ADD
XED_ICLASS_ADDPD
XED_ICLASS_ADDPS
XED_ICLASS_ADDSD
XED_ICLASS_ADDSS
XED_ICLASS_ADDSUBPD
XED_ICLASS_ADDSUBPS
XED_ICLASS_ADD_LOCK
XED_ICLASS_ADOX
XED_ICLASS_AESDEC
XED_ICLASS_AESDEC128KL
XED_ICLASS_AESDEC256KL
XED_ICLASS_AESDECLAST
XED_ICLASS_AESDECWIDE128KL
XED_ICLASS_AESDECWIDE256KL
XED_ICLASS_AESENC
XED_ICLASS_AESENC128KL
XED_ICLASS_AESENC256KL
XED_ICLASS_AESENCLAST
XED_ICLASS_AESENCWIDE128KL
XED_ICLASS_AESENCWIDE256KL
XED_ICLASS_AESIMC
XED_ICLASS_AESKEYGENASSIST
XED_ICLASS_AND
XED_ICLASS_ANDN
XED_ICLASS_ANDNPD
XED_ICLASS_ANDNPS
XED_ICLASS_ANDPD
XED_ICLASS_ANDPS
XED_ICLASS_AND_LOCK
XED_ICLASS_AOR
XED_ICLASS_ARPL
XED_ICLASS_AXOR
XED_ICLASS_BEXTR
XED_ICLASS_BEXTR_XOP
XED_ICLASS_BLCFILL
XED_ICLASS_BLCI
XED_ICLASS_BLCIC
XED_ICLASS_BLCMSK
XED_ICLASS_BLCS
XED_ICLASS_BLENDPD
XED_ICLASS_BLENDPS
XED_ICLASS_BLENDVPD
XED_ICLASS_BLENDVPS
XED_ICLASS_BLSFILL
XED_ICLASS_BLSI
XED_ICLASS_BLSIC
XED_ICLASS_BLSMSK
XED_ICLASS_BLSR
XED_ICLASS_BNDCL
XED_ICLASS_BNDCN
XED_ICLASS_BNDCU
XED_ICLASS_BNDLDX
XED_ICLASS_BNDMK
XED_ICLASS_BNDMOV
XED_ICLASS_BNDSTX
XED_ICLASS_BOUND
XED_ICLASS_BSF
XED_ICLASS_BSR
XED_ICLASS_BSWAP
XED_ICLASS_BT
XED_ICLASS_BTC
XED_ICLASS_BTC_LOCK
XED_ICLASS_BTR
XED_ICLASS_BTR_LOCK
XED_ICLASS_BTS
XED_ICLASS_BTS_LOCK
XED_ICLASS_BZHI
XED_ICLASS_CALL_FAR
XED_ICLASS_CALL_NEAR
XED_ICLASS_CBW
XED_ICLASS_CCMPB
XED_ICLASS_CCMPBE
XED_ICLASS_CCMPF
XED_ICLASS_CCMPL
XED_ICLASS_CCMPLE
XED_ICLASS_CCMPNB
XED_ICLASS_CCMPNBE
XED_ICLASS_CCMPNL
XED_ICLASS_CCMPNLE
XED_ICLASS_CCMPNO
XED_ICLASS_CCMPNS
XED_ICLASS_CCMPNZ
XED_ICLASS_CCMPO
XED_ICLASS_CCMPS
XED_ICLASS_CCMPT
XED_ICLASS_CCMPZ
XED_ICLASS_CDQ
XED_ICLASS_CDQE
XED_ICLASS_CFCMOVB
XED_ICLASS_CFCMOVBE
XED_ICLASS_CFCMOVL
XED_ICLASS_CFCMOVLE
XED_ICLASS_CFCMOVNB
XED_ICLASS_CFCMOVNBE
XED_ICLASS_CFCMOVNL
XED_ICLASS_CFCMOVNLE
XED_ICLASS_CFCMOVNO
XED_ICLASS_CFCMOVNP
XED_ICLASS_CFCMOVNS
XED_ICLASS_CFCMOVNZ
XED_ICLASS_CFCMOVO
XED_ICLASS_CFCMOVP
XED_ICLASS_CFCMOVS
XED_ICLASS_CFCMOVZ
XED_ICLASS_CLAC
XED_ICLASS_CLC
XED_ICLASS_CLD
XED_ICLASS_CLDEMOTE
XED_ICLASS_CLFLUSH
XED_ICLASS_CLFLUSHOPT
XED_ICLASS_CLGI
XED_ICLASS_CLI
XED_ICLASS_CLRSSBSY
XED_ICLASS_CLTS
XED_ICLASS_CLUI
XED_ICLASS_CLWB
XED_ICLASS_CLZERO
XED_ICLASS_CMC
XED_ICLASS_CMOVB
XED_ICLASS_CMOVBE
XED_ICLASS_CMOVL
XED_ICLASS_CMOVLE
XED_ICLASS_CMOVNB
XED_ICLASS_CMOVNBE
XED_ICLASS_CMOVNL
XED_ICLASS_CMOVNLE
XED_ICLASS_CMOVNO
XED_ICLASS_CMOVNP
XED_ICLASS_CMOVNS
XED_ICLASS_CMOVNZ
XED_ICLASS_CMOVO
XED_ICLASS_CMOVP
XED_ICLASS_CMOVS
XED_ICLASS_CMOVZ
XED_ICLASS_CMP
XED_ICLASS_CMPBEXADD
XED_ICLASS_CMPBXADD
XED_ICLASS_CMPLEXADD
XED_ICLASS_CMPLXADD
XED_ICLASS_CMPNBEXADD
XED_ICLASS_CMPNBXADD
XED_ICLASS_CMPNLEXADD
XED_ICLASS_CMPNLXADD
XED_ICLASS_CMPNOXADD
XED_ICLASS_CMPNPXADD
XED_ICLASS_CMPNSXADD
XED_ICLASS_CMPNZXADD
XED_ICLASS_CMPOXADD
XED_ICLASS_CMPPD
XED_ICLASS_CMPPS
XED_ICLASS_CMPPXADD
XED_ICLASS_CMPSB
XED_ICLASS_CMPSD
XED_ICLASS_CMPSD_XMM
XED_ICLASS_CMPSQ
XED_ICLASS_CMPSS
XED_ICLASS_CMPSW
XED_ICLASS_CMPSXADD
XED_ICLASS_CMPXCHG
XED_ICLASS_CMPXCHG8B
XED_ICLASS_CMPXCHG8B_LOCK
XED_ICLASS_CMPXCHG16B
XED_ICLASS_CMPXCHG16B_LOCK
XED_ICLASS_CMPXCHG_LOCK
XED_ICLASS_CMPZXADD
XED_ICLASS_COMISD
XED_ICLASS_COMISS
XED_ICLASS_CPUID
XED_ICLASS_CQO
XED_ICLASS_CRC32
XED_ICLASS_CTESTB
XED_ICLASS_CTESTBE
XED_ICLASS_CTESTF
XED_ICLASS_CTESTL
XED_ICLASS_CTESTLE
XED_ICLASS_CTESTNB
XED_ICLASS_CTESTNBE
XED_ICLASS_CTESTNL
XED_ICLASS_CTESTNLE
XED_ICLASS_CTESTNO
XED_ICLASS_CTESTNS
XED_ICLASS_CTESTNZ
XED_ICLASS_CTESTO
XED_ICLASS_CTESTS
XED_ICLASS_CTESTT
XED_ICLASS_CTESTZ
XED_ICLASS_CVTDQ2PD
XED_ICLASS_CVTDQ2PS
XED_ICLASS_CVTPD2DQ
XED_ICLASS_CVTPD2PI
XED_ICLASS_CVTPD2PS
XED_ICLASS_CVTPI2PD
XED_ICLASS_CVTPI2PS
XED_ICLASS_CVTPS2DQ
XED_ICLASS_CVTPS2PD
XED_ICLASS_CVTPS2PI
XED_ICLASS_CVTSD2SI
XED_ICLASS_CVTSD2SS
XED_ICLASS_CVTSI2SD
XED_ICLASS_CVTSI2SS
XED_ICLASS_CVTSS2SD
XED_ICLASS_CVTSS2SI
XED_ICLASS_CVTTPD2DQ
XED_ICLASS_CVTTPD2PI
XED_ICLASS_CVTTPS2DQ
XED_ICLASS_CVTTPS2PI
XED_ICLASS_CVTTSD2SI
XED_ICLASS_CVTTSS2SI
XED_ICLASS_CWD
XED_ICLASS_CWDE
XED_ICLASS_DAA
XED_ICLASS_DAS
XED_ICLASS_DEC
XED_ICLASS_DEC_LOCK
XED_ICLASS_DIV
XED_ICLASS_DIVPD
XED_ICLASS_DIVPS
XED_ICLASS_DIVSD
XED_ICLASS_DIVSS
XED_ICLASS_DPPD
XED_ICLASS_DPPS
XED_ICLASS_EMMS
XED_ICLASS_ENCLS
XED_ICLASS_ENCLU
XED_ICLASS_ENCLV
XED_ICLASS_ENCODEKEY128
XED_ICLASS_ENCODEKEY256
XED_ICLASS_ENDBR32
XED_ICLASS_ENDBR64
XED_ICLASS_ENQCMD
XED_ICLASS_ENQCMDS
XED_ICLASS_ENTER
XED_ICLASS_ERETS
XED_ICLASS_ERETU
XED_ICLASS_EXTRACTPS
XED_ICLASS_EXTRQ
XED_ICLASS_F2XM1
XED_ICLASS_FABS
XED_ICLASS_FADD
XED_ICLASS_FADDP
XED_ICLASS_FBLD
XED_ICLASS_FBSTP
XED_ICLASS_FCHS
XED_ICLASS_FCMOVB
XED_ICLASS_FCMOVBE
XED_ICLASS_FCMOVE
XED_ICLASS_FCMOVNB
XED_ICLASS_FCMOVNBE
XED_ICLASS_FCMOVNE
XED_ICLASS_FCMOVNU
XED_ICLASS_FCMOVU
XED_ICLASS_FCOM
XED_ICLASS_FCOMI
XED_ICLASS_FCOMIP
XED_ICLASS_FCOMP
XED_ICLASS_FCOMPP
XED_ICLASS_FCOS
XED_ICLASS_FDECSTP
XED_ICLASS_FDISI8087_NOP
XED_ICLASS_FDIV
XED_ICLASS_FDIVP
XED_ICLASS_FDIVR
XED_ICLASS_FDIVRP
XED_ICLASS_FEMMS
XED_ICLASS_FENI8087_NOP
XED_ICLASS_FFREE
XED_ICLASS_FFREEP
XED_ICLASS_FIADD
XED_ICLASS_FICOM
XED_ICLASS_FICOMP
XED_ICLASS_FIDIV
XED_ICLASS_FIDIVR
XED_ICLASS_FILD
XED_ICLASS_FIMUL
XED_ICLASS_FINCSTP
XED_ICLASS_FIST
XED_ICLASS_FISTP
XED_ICLASS_FISTTP
XED_ICLASS_FISUB
XED_ICLASS_FISUBR
XED_ICLASS_FLD
XED_ICLASS_FLD1
XED_ICLASS_FLDCW
XED_ICLASS_FLDENV
XED_ICLASS_FLDL2E
XED_ICLASS_FLDL2T
XED_ICLASS_FLDLG2
XED_ICLASS_FLDLN2
XED_ICLASS_FLDPI
XED_ICLASS_FLDZ
XED_ICLASS_FMUL
XED_ICLASS_FMULP
XED_ICLASS_FNCLEX
XED_ICLASS_FNINIT
XED_ICLASS_FNOP
XED_ICLASS_FNSAVE
XED_ICLASS_FNSTCW
XED_ICLASS_FNSTENV
XED_ICLASS_FNSTSW
XED_ICLASS_FPATAN
XED_ICLASS_FPREM
XED_ICLASS_FPREM1
XED_ICLASS_FPTAN
XED_ICLASS_FRNDINT
XED_ICLASS_FRSTOR
XED_ICLASS_FSCALE
XED_ICLASS_FSETPM287_NOP
XED_ICLASS_FSIN
XED_ICLASS_FSINCOS
XED_ICLASS_FSQRT
XED_ICLASS_FST
XED_ICLASS_FSTP
XED_ICLASS_FSTPNCE
XED_ICLASS_FSUB
XED_ICLASS_FSUBP
XED_ICLASS_FSUBR
XED_ICLASS_FSUBRP
XED_ICLASS_FTST
XED_ICLASS_FUCOM
XED_ICLASS_FUCOMI
XED_ICLASS_FUCOMIP
XED_ICLASS_FUCOMP
XED_ICLASS_FUCOMPP
XED_ICLASS_FWAIT
XED_ICLASS_FXAM
XED_ICLASS_FXCH
XED_ICLASS_FXRSTOR
XED_ICLASS_FXRSTOR64
XED_ICLASS_FXSAVE
XED_ICLASS_FXSAVE64
XED_ICLASS_FXTRACT
XED_ICLASS_FYL2X
XED_ICLASS_FYL2XP1
XED_ICLASS_GETSEC
XED_ICLASS_GF2P8AFFINEINVQB
XED_ICLASS_GF2P8AFFINEQB
XED_ICLASS_GF2P8MULB
XED_ICLASS_HADDPD
XED_ICLASS_HADDPS
XED_ICLASS_HLT
XED_ICLASS_HRESET
XED_ICLASS_HSUBPD
XED_ICLASS_HSUBPS
XED_ICLASS_IDIV
XED_ICLASS_IMUL
XED_ICLASS_IN
XED_ICLASS_INC
XED_ICLASS_INCSSPD
XED_ICLASS_INCSSPQ
XED_ICLASS_INC_LOCK
XED_ICLASS_INSB
XED_ICLASS_INSD
XED_ICLASS_INSERTPS
XED_ICLASS_INSERTQ
XED_ICLASS_INSW
XED_ICLASS_INT
XED_ICLASS_INT1
XED_ICLASS_INT3
XED_ICLASS_INTO
XED_ICLASS_INVALID
XED_ICLASS_INVD
XED_ICLASS_INVEPT
XED_ICLASS_INVLPG
XED_ICLASS_INVLPGA
XED_ICLASS_INVLPGB
XED_ICLASS_INVPCID
XED_ICLASS_INVVPID
XED_ICLASS_IRET
XED_ICLASS_IRETD
XED_ICLASS_IRETQ
XED_ICLASS_JB
XED_ICLASS_JBE
XED_ICLASS_JCXZ
XED_ICLASS_JECXZ
XED_ICLASS_JL
XED_ICLASS_JLE
XED_ICLASS_JMP
XED_ICLASS_JMPABS
XED_ICLASS_JMP_FAR
XED_ICLASS_JNB
XED_ICLASS_JNBE
XED_ICLASS_JNL
XED_ICLASS_JNLE
XED_ICLASS_JNO
XED_ICLASS_JNP
XED_ICLASS_JNS
XED_ICLASS_JNZ
XED_ICLASS_JO
XED_ICLASS_JP
XED_ICLASS_JRCXZ
XED_ICLASS_JS
XED_ICLASS_JZ
XED_ICLASS_KADDB
XED_ICLASS_KADDD
XED_ICLASS_KADDQ
XED_ICLASS_KADDW
XED_ICLASS_KANDB
XED_ICLASS_KANDD
XED_ICLASS_KANDNB
XED_ICLASS_KANDND
XED_ICLASS_KANDNQ
XED_ICLASS_KANDNW
XED_ICLASS_KANDQ
XED_ICLASS_KANDW
XED_ICLASS_KMOVB
XED_ICLASS_KMOVD
XED_ICLASS_KMOVQ
XED_ICLASS_KMOVW
XED_ICLASS_KNOTB
XED_ICLASS_KNOTD
XED_ICLASS_KNOTQ
XED_ICLASS_KNOTW
XED_ICLASS_KORB
XED_ICLASS_KORD
XED_ICLASS_KORQ
XED_ICLASS_KORTESTB
XED_ICLASS_KORTESTD
XED_ICLASS_KORTESTQ
XED_ICLASS_KORTESTW
XED_ICLASS_KORW
XED_ICLASS_KSHIFTLB
XED_ICLASS_KSHIFTLD
XED_ICLASS_KSHIFTLQ
XED_ICLASS_KSHIFTLW
XED_ICLASS_KSHIFTRB
XED_ICLASS_KSHIFTRD
XED_ICLASS_KSHIFTRQ
XED_ICLASS_KSHIFTRW
XED_ICLASS_KTESTB
XED_ICLASS_KTESTD
XED_ICLASS_KTESTQ
XED_ICLASS_KTESTW
XED_ICLASS_KUNPCKBW
XED_ICLASS_KUNPCKDQ
XED_ICLASS_KUNPCKWD
XED_ICLASS_KXNORB
XED_ICLASS_KXNORD
XED_ICLASS_KXNORQ
XED_ICLASS_KXNORW
XED_ICLASS_KXORB
XED_ICLASS_KXORD
XED_ICLASS_KXORQ
XED_ICLASS_KXORW
XED_ICLASS_LAHF
XED_ICLASS_LAR
XED_ICLASS_LAST
XED_ICLASS_LDDQU
XED_ICLASS_LDMXCSR
XED_ICLASS_LDS
XED_ICLASS_LDTILECFG
XED_ICLASS_LEA
XED_ICLASS_LEAVE
XED_ICLASS_LES
XED_ICLASS_LFENCE
XED_ICLASS_LFS
XED_ICLASS_LGDT
XED_ICLASS_LGS
XED_ICLASS_LIDT
XED_ICLASS_LKGS
XED_ICLASS_LLDT
XED_ICLASS_LLWPCB
XED_ICLASS_LMSW
XED_ICLASS_LOADIWKEY
XED_ICLASS_LODSB
XED_ICLASS_LODSD
XED_ICLASS_LODSQ
XED_ICLASS_LODSW
XED_ICLASS_LOOP
XED_ICLASS_LOOPE
XED_ICLASS_LOOPNE
XED_ICLASS_LSL
XED_ICLASS_LSS
XED_ICLASS_LTR
XED_ICLASS_LWPINS
XED_ICLASS_LWPVAL
XED_ICLASS_LZCNT
XED_ICLASS_MASKMOVDQU
XED_ICLASS_MASKMOVQ
XED_ICLASS_MAXPD
XED_ICLASS_MAXPS
XED_ICLASS_MAXSD
XED_ICLASS_MAXSS
XED_ICLASS_MCOMMIT
XED_ICLASS_MFENCE
XED_ICLASS_MINPD
XED_ICLASS_MINPS
XED_ICLASS_MINSD
XED_ICLASS_MINSS
XED_ICLASS_MONITOR
XED_ICLASS_MONITORX
XED_ICLASS_MOV
XED_ICLASS_MOVAPD
XED_ICLASS_MOVAPS
XED_ICLASS_MOVBE
XED_ICLASS_MOVD
XED_ICLASS_MOVDDUP
XED_ICLASS_MOVDIR64B
XED_ICLASS_MOVDIRI
XED_ICLASS_MOVDQ2Q
XED_ICLASS_MOVDQA
XED_ICLASS_MOVDQU
XED_ICLASS_MOVHLPS
XED_ICLASS_MOVHPD
XED_ICLASS_MOVHPS
XED_ICLASS_MOVLHPS
XED_ICLASS_MOVLPD
XED_ICLASS_MOVLPS
XED_ICLASS_MOVMSKPD
XED_ICLASS_MOVMSKPS
XED_ICLASS_MOVNTDQ
XED_ICLASS_MOVNTDQA
XED_ICLASS_MOVNTI
XED_ICLASS_MOVNTPD
XED_ICLASS_MOVNTPS
XED_ICLASS_MOVNTQ
XED_ICLASS_MOVNTSD
XED_ICLASS_MOVNTSS
XED_ICLASS_MOVQ
XED_ICLASS_MOVQ2DQ
XED_ICLASS_MOVSB
XED_ICLASS_MOVSD
XED_ICLASS_MOVSD_XMM
XED_ICLASS_MOVSHDUP
XED_ICLASS_MOVSLDUP
XED_ICLASS_MOVSQ
XED_ICLASS_MOVSS
XED_ICLASS_MOVSW
XED_ICLASS_MOVSX
XED_ICLASS_MOVSXD
XED_ICLASS_MOVUPD
XED_ICLASS_MOVUPS
XED_ICLASS_MOVZX
XED_ICLASS_MOV_CR
XED_ICLASS_MOV_DR
XED_ICLASS_MPSADBW
XED_ICLASS_MUL
XED_ICLASS_MULPD
XED_ICLASS_MULPS
XED_ICLASS_MULSD
XED_ICLASS_MULSS
XED_ICLASS_MULX
XED_ICLASS_MWAIT
XED_ICLASS_MWAITX
XED_ICLASS_NAME_STR_MAX
XED_ICLASS_NEG
XED_ICLASS_NEG_LOCK
XED_ICLASS_NOP
XED_ICLASS_NOP2
XED_ICLASS_NOP3
XED_ICLASS_NOP4
XED_ICLASS_NOP5
XED_ICLASS_NOP6
XED_ICLASS_NOP7
XED_ICLASS_NOP8
XED_ICLASS_NOP9
XED_ICLASS_NOT
XED_ICLASS_NOT_LOCK
XED_ICLASS_OR
XED_ICLASS_ORPD
XED_ICLASS_ORPS
XED_ICLASS_OR_LOCK
XED_ICLASS_OUT
XED_ICLASS_OUTSB
XED_ICLASS_OUTSD
XED_ICLASS_OUTSW
XED_ICLASS_PABSB
XED_ICLASS_PABSD
XED_ICLASS_PABSW
XED_ICLASS_PACKSSDW
XED_ICLASS_PACKSSWB
XED_ICLASS_PACKUSDW
XED_ICLASS_PACKUSWB
XED_ICLASS_PADDB
XED_ICLASS_PADDD
XED_ICLASS_PADDQ
XED_ICLASS_PADDSB
XED_ICLASS_PADDSW
XED_ICLASS_PADDUSB
XED_ICLASS_PADDUSW
XED_ICLASS_PADDW
XED_ICLASS_PALIGNR
XED_ICLASS_PAND
XED_ICLASS_PANDN
XED_ICLASS_PAUSE
XED_ICLASS_PAVGB
XED_ICLASS_PAVGUSB
XED_ICLASS_PAVGW
XED_ICLASS_PBLENDVB
XED_ICLASS_PBLENDW
XED_ICLASS_PBNDKB
XED_ICLASS_PCLMULQDQ
XED_ICLASS_PCMPEQB
XED_ICLASS_PCMPEQD
XED_ICLASS_PCMPEQQ
XED_ICLASS_PCMPEQW
XED_ICLASS_PCMPESTRI
XED_ICLASS_PCMPESTRI64
XED_ICLASS_PCMPESTRM
XED_ICLASS_PCMPESTRM64
XED_ICLASS_PCMPGTB
XED_ICLASS_PCMPGTD
XED_ICLASS_PCMPGTQ
XED_ICLASS_PCMPGTW
XED_ICLASS_PCMPISTRI
XED_ICLASS_PCMPISTRI64
XED_ICLASS_PCMPISTRM
XED_ICLASS_PCONFIG
XED_ICLASS_PDEP
XED_ICLASS_PEXT
XED_ICLASS_PEXTRB
XED_ICLASS_PEXTRD
XED_ICLASS_PEXTRQ
XED_ICLASS_PEXTRW
XED_ICLASS_PEXTRW_SSE4
XED_ICLASS_PF2ID
XED_ICLASS_PF2IW
XED_ICLASS_PFACC
XED_ICLASS_PFADD
XED_ICLASS_PFCMPEQ
XED_ICLASS_PFCMPGE
XED_ICLASS_PFCMPGT
XED_ICLASS_PFMAX
XED_ICLASS_PFMIN
XED_ICLASS_PFMUL
XED_ICLASS_PFNACC
XED_ICLASS_PFPNACC
XED_ICLASS_PFRCP
XED_ICLASS_PFRCPIT1
XED_ICLASS_PFRCPIT2
XED_ICLASS_PFRSQIT1
XED_ICLASS_PFRSQRT
XED_ICLASS_PFSUB
XED_ICLASS_PFSUBR
XED_ICLASS_PHADDD
XED_ICLASS_PHADDSW
XED_ICLASS_PHADDW
XED_ICLASS_PHMINPOSUW
XED_ICLASS_PHSUBD
XED_ICLASS_PHSUBSW
XED_ICLASS_PHSUBW
XED_ICLASS_PI2FD
XED_ICLASS_PI2FW
XED_ICLASS_PINSRB
XED_ICLASS_PINSRD
XED_ICLASS_PINSRQ
XED_ICLASS_PINSRW
XED_ICLASS_PMADDUBSW
XED_ICLASS_PMADDWD
XED_ICLASS_PMAXSB
XED_ICLASS_PMAXSD
XED_ICLASS_PMAXSW
XED_ICLASS_PMAXUB
XED_ICLASS_PMAXUD
XED_ICLASS_PMAXUW
XED_ICLASS_PMINSB
XED_ICLASS_PMINSD
XED_ICLASS_PMINSW
XED_ICLASS_PMINUB
XED_ICLASS_PMINUD
XED_ICLASS_PMINUW
XED_ICLASS_PMOVMSKB
XED_ICLASS_PMOVSXBD
XED_ICLASS_PMOVSXBQ
XED_ICLASS_PMOVSXBW
XED_ICLASS_PMOVSXDQ
XED_ICLASS_PMOVSXWD
XED_ICLASS_PMOVSXWQ
XED_ICLASS_PMOVZXBD
XED_ICLASS_PMOVZXBQ
XED_ICLASS_PMOVZXBW
XED_ICLASS_PMOVZXDQ
XED_ICLASS_PMOVZXWD
XED_ICLASS_PMOVZXWQ
XED_ICLASS_PMULDQ
XED_ICLASS_PMULHRSW
XED_ICLASS_PMULHRW
XED_ICLASS_PMULHUW
XED_ICLASS_PMULHW
XED_ICLASS_PMULLD
XED_ICLASS_PMULLW
XED_ICLASS_PMULUDQ
XED_ICLASS_POP
XED_ICLASS_POP2
XED_ICLASS_POP2P
XED_ICLASS_POPA
XED_ICLASS_POPAD
XED_ICLASS_POPCNT
XED_ICLASS_POPF
XED_ICLASS_POPFD
XED_ICLASS_POPFQ
XED_ICLASS_POPP
XED_ICLASS_POR
XED_ICLASS_PREFETCHIT0
XED_ICLASS_PREFETCHIT1
XED_ICLASS_PREFETCHNTA
XED_ICLASS_PREFETCHT0
XED_ICLASS_PREFETCHT1
XED_ICLASS_PREFETCHT2
XED_ICLASS_PREFETCHW
XED_ICLASS_PREFETCHWT1
XED_ICLASS_PREFETCH_EXCLUSIVE
XED_ICLASS_PREFETCH_RESERVED
XED_ICLASS_PSADBW
XED_ICLASS_PSHUFB
XED_ICLASS_PSHUFD
XED_ICLASS_PSHUFHW
XED_ICLASS_PSHUFLW
XED_ICLASS_PSHUFW
XED_ICLASS_PSIGNB
XED_ICLASS_PSIGND
XED_ICLASS_PSIGNW
XED_ICLASS_PSLLD
XED_ICLASS_PSLLDQ
XED_ICLASS_PSLLQ
XED_ICLASS_PSLLW
XED_ICLASS_PSMASH
XED_ICLASS_PSRAD
XED_ICLASS_PSRAW
XED_ICLASS_PSRLD
XED_ICLASS_PSRLDQ
XED_ICLASS_PSRLQ
XED_ICLASS_PSRLW
XED_ICLASS_PSUBB
XED_ICLASS_PSUBD
XED_ICLASS_PSUBQ
XED_ICLASS_PSUBSB
XED_ICLASS_PSUBSW
XED_ICLASS_PSUBUSB
XED_ICLASS_PSUBUSW
XED_ICLASS_PSUBW
XED_ICLASS_PSWAPD
XED_ICLASS_PTEST
XED_ICLASS_PTWRITE
XED_ICLASS_PUNPCKHBW
XED_ICLASS_PUNPCKHDQ
XED_ICLASS_PUNPCKHQDQ
XED_ICLASS_PUNPCKHWD
XED_ICLASS_PUNPCKLBW
XED_ICLASS_PUNPCKLDQ
XED_ICLASS_PUNPCKLQDQ
XED_ICLASS_PUNPCKLWD
XED_ICLASS_PUSH
XED_ICLASS_PUSH2
XED_ICLASS_PUSH2P
XED_ICLASS_PUSHA
XED_ICLASS_PUSHAD
XED_ICLASS_PUSHF
XED_ICLASS_PUSHFD
XED_ICLASS_PUSHFQ
XED_ICLASS_PUSHP
XED_ICLASS_PVALIDATE
XED_ICLASS_PXOR
XED_ICLASS_RCL
XED_ICLASS_RCPPS
XED_ICLASS_RCPSS
XED_ICLASS_RCR
XED_ICLASS_RDFSBASE
XED_ICLASS_RDGSBASE
XED_ICLASS_RDMSR
XED_ICLASS_RDMSRLIST
XED_ICLASS_RDPID
XED_ICLASS_RDPKRU
XED_ICLASS_RDPMC
XED_ICLASS_RDPRU
XED_ICLASS_RDRAND
XED_ICLASS_RDSEED
XED_ICLASS_RDSSPD
XED_ICLASS_RDSSPQ
XED_ICLASS_RDTSC
XED_ICLASS_RDTSCP
XED_ICLASS_REPE_CMPSB
XED_ICLASS_REPE_CMPSD
XED_ICLASS_REPE_CMPSQ
XED_ICLASS_REPE_CMPSW
XED_ICLASS_REPE_SCASB
XED_ICLASS_REPE_SCASD
XED_ICLASS_REPE_SCASQ
XED_ICLASS_REPE_SCASW
XED_ICLASS_REPNE_CMPSB
XED_ICLASS_REPNE_CMPSD
XED_ICLASS_REPNE_CMPSQ
XED_ICLASS_REPNE_CMPSW
XED_ICLASS_REPNE_SCASB
XED_ICLASS_REPNE_SCASD
XED_ICLASS_REPNE_SCASQ
XED_ICLASS_REPNE_SCASW
XED_ICLASS_REP_INSB
XED_ICLASS_REP_INSD
XED_ICLASS_REP_INSW
XED_ICLASS_REP_LODSB
XED_ICLASS_REP_LODSD
XED_ICLASS_REP_LODSQ
XED_ICLASS_REP_LODSW
XED_ICLASS_REP_MONTMUL
XED_ICLASS_REP_MOVSB
XED_ICLASS_REP_MOVSD
XED_ICLASS_REP_MOVSQ
XED_ICLASS_REP_MOVSW
XED_ICLASS_REP_OUTSB
XED_ICLASS_REP_OUTSD
XED_ICLASS_REP_OUTSW
XED_ICLASS_REP_STOSB
XED_ICLASS_REP_STOSD
XED_ICLASS_REP_STOSQ
XED_ICLASS_REP_STOSW
XED_ICLASS_REP_XCRYPTCBC
XED_ICLASS_REP_XCRYPTCFB
XED_ICLASS_REP_XCRYPTCTR
XED_ICLASS_REP_XCRYPTECB
XED_ICLASS_REP_XCRYPTOFB
XED_ICLASS_REP_XSHA1
XED_ICLASS_REP_XSHA256
XED_ICLASS_REP_XSTORE
XED_ICLASS_RET_FAR
XED_ICLASS_RET_NEAR
XED_ICLASS_RMPADJUST
XED_ICLASS_RMPUPDATE
XED_ICLASS_ROL
XED_ICLASS_ROR
XED_ICLASS_RORX
XED_ICLASS_ROUNDPD
XED_ICLASS_ROUNDPS
XED_ICLASS_ROUNDSD
XED_ICLASS_ROUNDSS
XED_ICLASS_RSM
XED_ICLASS_RSQRTPS
XED_ICLASS_RSQRTSS
XED_ICLASS_RSTORSSP
XED_ICLASS_SAHF
XED_ICLASS_SALC
XED_ICLASS_SAR
XED_ICLASS_SARX
XED_ICLASS_SAVEPREVSSP
XED_ICLASS_SBB
XED_ICLASS_SBB_LOCK
XED_ICLASS_SCASB
XED_ICLASS_SCASD
XED_ICLASS_SCASQ
XED_ICLASS_SCASW
XED_ICLASS_SEAMCALL
XED_ICLASS_SEAMOPS
XED_ICLASS_SEAMRET
XED_ICLASS_SENDUIPI
XED_ICLASS_SERIALIZE
XED_ICLASS_SETB
XED_ICLASS_SETBE
XED_ICLASS_SETL
XED_ICLASS_SETLE
XED_ICLASS_SETNB
XED_ICLASS_SETNBE
XED_ICLASS_SETNL
XED_ICLASS_SETNLE
XED_ICLASS_SETNO
XED_ICLASS_SETNP
XED_ICLASS_SETNS
XED_ICLASS_SETNZ
XED_ICLASS_SETO
XED_ICLASS_SETP
XED_ICLASS_SETS
XED_ICLASS_SETSSBSY
XED_ICLASS_SETZ
XED_ICLASS_SFENCE
XED_ICLASS_SGDT
XED_ICLASS_SHA1MSG1
XED_ICLASS_SHA1MSG2
XED_ICLASS_SHA1NEXTE
XED_ICLASS_SHA1RNDS4
XED_ICLASS_SHA256MSG1
XED_ICLASS_SHA256MSG2
XED_ICLASS_SHA256RNDS2
XED_ICLASS_SHL
XED_ICLASS_SHLD
XED_ICLASS_SHLX
XED_ICLASS_SHR
XED_ICLASS_SHRD
XED_ICLASS_SHRX
XED_ICLASS_SHUFPD
XED_ICLASS_SHUFPS
XED_ICLASS_SIDT
XED_ICLASS_SKINIT
XED_ICLASS_SLDT
XED_ICLASS_SLWPCB
XED_ICLASS_SMSW
XED_ICLASS_SQRTPD
XED_ICLASS_SQRTPS
XED_ICLASS_SQRTSD
XED_ICLASS_SQRTSS
XED_ICLASS_STAC
XED_ICLASS_STC
XED_ICLASS_STD
XED_ICLASS_STGI
XED_ICLASS_STI
XED_ICLASS_STMXCSR
XED_ICLASS_STOSB
XED_ICLASS_STOSD
XED_ICLASS_STOSQ
XED_ICLASS_STOSW
XED_ICLASS_STR
XED_ICLASS_STTILECFG
XED_ICLASS_STUI
XED_ICLASS_SUB
XED_ICLASS_SUBPD
XED_ICLASS_SUBPS
XED_ICLASS_SUBSD
XED_ICLASS_SUBSS
XED_ICLASS_SUB_LOCK
XED_ICLASS_SWAPGS
XED_ICLASS_SYSCALL
XED_ICLASS_SYSCALL_32
XED_ICLASS_SYSENTER
XED_ICLASS_SYSEXIT
XED_ICLASS_SYSRET
XED_ICLASS_SYSRET64
XED_ICLASS_SYSRET_AMD
XED_ICLASS_T1MSKC
XED_ICLASS_TCMMIMFP16PS
XED_ICLASS_TCMMRLFP16PS
XED_ICLASS_TDCALL
XED_ICLASS_TDPBF16PS
XED_ICLASS_TDPBSSD
XED_ICLASS_TDPBSUD
XED_ICLASS_TDPBUSD
XED_ICLASS_TDPBUUD
XED_ICLASS_TDPFP16PS
XED_ICLASS_TEST
XED_ICLASS_TESTUI
XED_ICLASS_TILELOADD
XED_ICLASS_TILELOADDT1
XED_ICLASS_TILERELEASE
XED_ICLASS_TILESTORED
XED_ICLASS_TILEZERO
XED_ICLASS_TLBSYNC
XED_ICLASS_TPAUSE
XED_ICLASS_TZCNT
XED_ICLASS_TZMSK
XED_ICLASS_UCOMISD
XED_ICLASS_UCOMISS
XED_ICLASS_UD0
XED_ICLASS_UD1
XED_ICLASS_UD2
XED_ICLASS_UIRET
XED_ICLASS_UMONITOR
XED_ICLASS_UMWAIT
XED_ICLASS_UNPCKHPD
XED_ICLASS_UNPCKHPS
XED_ICLASS_UNPCKLPD
XED_ICLASS_UNPCKLPS
XED_ICLASS_URDMSR
XED_ICLASS_UWRMSR
XED_ICLASS_V4FMADDPS
XED_ICLASS_V4FMADDSS
XED_ICLASS_V4FNMADDPS
XED_ICLASS_V4FNMADDSS
XED_ICLASS_VADDPD
XED_ICLASS_VADDPH
XED_ICLASS_VADDPS
XED_ICLASS_VADDSD
XED_ICLASS_VADDSH
XED_ICLASS_VADDSS
XED_ICLASS_VADDSUBPD
XED_ICLASS_VADDSUBPS
XED_ICLASS_VAESDEC
XED_ICLASS_VAESDECLAST
XED_ICLASS_VAESENC
XED_ICLASS_VAESENCLAST
XED_ICLASS_VAESIMC
XED_ICLASS_VAESKEYGENASSIST
XED_ICLASS_VALIGND
XED_ICLASS_VALIGNQ
XED_ICLASS_VANDNPD
XED_ICLASS_VANDNPS
XED_ICLASS_VANDPD
XED_ICLASS_VANDPS
XED_ICLASS_VBCSTNEBF162PS
XED_ICLASS_VBCSTNESH2PS
XED_ICLASS_VBLENDMPD
XED_ICLASS_VBLENDMPS
XED_ICLASS_VBLENDPD
XED_ICLASS_VBLENDPS
XED_ICLASS_VBLENDVPD
XED_ICLASS_VBLENDVPS
XED_ICLASS_VBROADCASTF32X2
XED_ICLASS_VBROADCASTF32X4
XED_ICLASS_VBROADCASTF32X8
XED_ICLASS_VBROADCASTF64X2
XED_ICLASS_VBROADCASTF64X4
XED_ICLASS_VBROADCASTF128
XED_ICLASS_VBROADCASTI32X2
XED_ICLASS_VBROADCASTI32X4
XED_ICLASS_VBROADCASTI32X8
XED_ICLASS_VBROADCASTI64X2
XED_ICLASS_VBROADCASTI64X4
XED_ICLASS_VBROADCASTI128
XED_ICLASS_VBROADCASTSD
XED_ICLASS_VBROADCASTSS
XED_ICLASS_VCMPPD
XED_ICLASS_VCMPPH
XED_ICLASS_VCMPPS
XED_ICLASS_VCMPSD
XED_ICLASS_VCMPSH
XED_ICLASS_VCMPSS
XED_ICLASS_VCOMISD
XED_ICLASS_VCOMISH
XED_ICLASS_VCOMISS
XED_ICLASS_VCOMPRESSPD
XED_ICLASS_VCOMPRESSPS
XED_ICLASS_VCVTDQ2PD
XED_ICLASS_VCVTDQ2PH
XED_ICLASS_VCVTDQ2PS
XED_ICLASS_VCVTNE2PS2BF16
XED_ICLASS_VCVTNEEBF162PS
XED_ICLASS_VCVTNEEPH2PS
XED_ICLASS_VCVTNEOBF162PS
XED_ICLASS_VCVTNEOPH2PS
XED_ICLASS_VCVTNEPS2BF16
XED_ICLASS_VCVTPD2DQ
XED_ICLASS_VCVTPD2PH
XED_ICLASS_VCVTPD2PS
XED_ICLASS_VCVTPD2QQ
XED_ICLASS_VCVTPD2UDQ
XED_ICLASS_VCVTPD2UQQ
XED_ICLASS_VCVTPH2DQ
XED_ICLASS_VCVTPH2PD
XED_ICLASS_VCVTPH2PS
XED_ICLASS_VCVTPH2PSX
XED_ICLASS_VCVTPH2QQ
XED_ICLASS_VCVTPH2UDQ
XED_ICLASS_VCVTPH2UQQ
XED_ICLASS_VCVTPH2UW
XED_ICLASS_VCVTPH2W
XED_ICLASS_VCVTPS2DQ
XED_ICLASS_VCVTPS2PD
XED_ICLASS_VCVTPS2PH
XED_ICLASS_VCVTPS2PHX
XED_ICLASS_VCVTPS2QQ
XED_ICLASS_VCVTPS2UDQ
XED_ICLASS_VCVTPS2UQQ
XED_ICLASS_VCVTQQ2PD
XED_ICLASS_VCVTQQ2PH
XED_ICLASS_VCVTQQ2PS
XED_ICLASS_VCVTSD2SH
XED_ICLASS_VCVTSD2SI
XED_ICLASS_VCVTSD2SS
XED_ICLASS_VCVTSD2USI
XED_ICLASS_VCVTSH2SD
XED_ICLASS_VCVTSH2SI
XED_ICLASS_VCVTSH2SS
XED_ICLASS_VCVTSH2USI
XED_ICLASS_VCVTSI2SD
XED_ICLASS_VCVTSI2SH
XED_ICLASS_VCVTSI2SS
XED_ICLASS_VCVTSS2SD
XED_ICLASS_VCVTSS2SH
XED_ICLASS_VCVTSS2SI
XED_ICLASS_VCVTSS2USI
XED_ICLASS_VCVTTPD2DQ
XED_ICLASS_VCVTTPD2QQ
XED_ICLASS_VCVTTPD2UDQ
XED_ICLASS_VCVTTPD2UQQ
XED_ICLASS_VCVTTPH2DQ
XED_ICLASS_VCVTTPH2QQ
XED_ICLASS_VCVTTPH2UDQ
XED_ICLASS_VCVTTPH2UQQ
XED_ICLASS_VCVTTPH2UW
XED_ICLASS_VCVTTPH2W
XED_ICLASS_VCVTTPS2DQ
XED_ICLASS_VCVTTPS2QQ
XED_ICLASS_VCVTTPS2UDQ
XED_ICLASS_VCVTTPS2UQQ
XED_ICLASS_VCVTTSD2SI
XED_ICLASS_VCVTTSD2USI
XED_ICLASS_VCVTTSH2SI
XED_ICLASS_VCVTTSH2USI
XED_ICLASS_VCVTTSS2SI
XED_ICLASS_VCVTTSS2USI
XED_ICLASS_VCVTUDQ2PD
XED_ICLASS_VCVTUDQ2PH
XED_ICLASS_VCVTUDQ2PS
XED_ICLASS_VCVTUQQ2PD
XED_ICLASS_VCVTUQQ2PH
XED_ICLASS_VCVTUQQ2PS
XED_ICLASS_VCVTUSI2SD
XED_ICLASS_VCVTUSI2SH
XED_ICLASS_VCVTUSI2SS
XED_ICLASS_VCVTUW2PH
XED_ICLASS_VCVTW2PH
XED_ICLASS_VDBPSADBW
XED_ICLASS_VDIVPD
XED_ICLASS_VDIVPH
XED_ICLASS_VDIVPS
XED_ICLASS_VDIVSD
XED_ICLASS_VDIVSH
XED_ICLASS_VDIVSS
XED_ICLASS_VDPBF16PS
XED_ICLASS_VDPPD
XED_ICLASS_VDPPS
XED_ICLASS_VERR
XED_ICLASS_VERW
XED_ICLASS_VEXP2PD
XED_ICLASS_VEXP2PS
XED_ICLASS_VEXPANDPD
XED_ICLASS_VEXPANDPS
XED_ICLASS_VEXTRACTF32X4
XED_ICLASS_VEXTRACTF32X8
XED_ICLASS_VEXTRACTF64X2
XED_ICLASS_VEXTRACTF64X4
XED_ICLASS_VEXTRACTF128
XED_ICLASS_VEXTRACTI32X4
XED_ICLASS_VEXTRACTI32X8
XED_ICLASS_VEXTRACTI64X2
XED_ICLASS_VEXTRACTI64X4
XED_ICLASS_VEXTRACTI128
XED_ICLASS_VEXTRACTPS
XED_ICLASS_VFCMADDCPH
XED_ICLASS_VFCMADDCSH
XED_ICLASS_VFCMULCPH
XED_ICLASS_VFCMULCSH
XED_ICLASS_VFIXUPIMMPD
XED_ICLASS_VFIXUPIMMPS
XED_ICLASS_VFIXUPIMMSD
XED_ICLASS_VFIXUPIMMSS
XED_ICLASS_VFMADD132PD
XED_ICLASS_VFMADD132PH
XED_ICLASS_VFMADD132PS
XED_ICLASS_VFMADD132SD
XED_ICLASS_VFMADD132SH
XED_ICLASS_VFMADD132SS
XED_ICLASS_VFMADD213PD
XED_ICLASS_VFMADD213PH
XED_ICLASS_VFMADD213PS
XED_ICLASS_VFMADD213SD
XED_ICLASS_VFMADD213SH
XED_ICLASS_VFMADD213SS
XED_ICLASS_VFMADD231PD
XED_ICLASS_VFMADD231PH
XED_ICLASS_VFMADD231PS
XED_ICLASS_VFMADD231SD
XED_ICLASS_VFMADD231SH
XED_ICLASS_VFMADD231SS
XED_ICLASS_VFMADDCPH
XED_ICLASS_VFMADDCSH
XED_ICLASS_VFMADDPD
XED_ICLASS_VFMADDPS
XED_ICLASS_VFMADDSD
XED_ICLASS_VFMADDSS
XED_ICLASS_VFMADDSUB132PD
XED_ICLASS_VFMADDSUB132PH
XED_ICLASS_VFMADDSUB132PS
XED_ICLASS_VFMADDSUB213PD
XED_ICLASS_VFMADDSUB213PH
XED_ICLASS_VFMADDSUB213PS
XED_ICLASS_VFMADDSUB231PD
XED_ICLASS_VFMADDSUB231PH
XED_ICLASS_VFMADDSUB231PS
XED_ICLASS_VFMADDSUBPD
XED_ICLASS_VFMADDSUBPS
XED_ICLASS_VFMSUB132PD
XED_ICLASS_VFMSUB132PH
XED_ICLASS_VFMSUB132PS
XED_ICLASS_VFMSUB132SD
XED_ICLASS_VFMSUB132SH
XED_ICLASS_VFMSUB132SS
XED_ICLASS_VFMSUB213PD
XED_ICLASS_VFMSUB213PH
XED_ICLASS_VFMSUB213PS
XED_ICLASS_VFMSUB213SD
XED_ICLASS_VFMSUB213SH
XED_ICLASS_VFMSUB213SS
XED_ICLASS_VFMSUB231PD
XED_ICLASS_VFMSUB231PH
XED_ICLASS_VFMSUB231PS
XED_ICLASS_VFMSUB231SD
XED_ICLASS_VFMSUB231SH
XED_ICLASS_VFMSUB231SS
XED_ICLASS_VFMSUBADD132PD
XED_ICLASS_VFMSUBADD132PH
XED_ICLASS_VFMSUBADD132PS
XED_ICLASS_VFMSUBADD213PD
XED_ICLASS_VFMSUBADD213PH
XED_ICLASS_VFMSUBADD213PS
XED_ICLASS_VFMSUBADD231PD
XED_ICLASS_VFMSUBADD231PH
XED_ICLASS_VFMSUBADD231PS
XED_ICLASS_VFMSUBADDPD
XED_ICLASS_VFMSUBADDPS
XED_ICLASS_VFMSUBPD
XED_ICLASS_VFMSUBPS
XED_ICLASS_VFMSUBSD
XED_ICLASS_VFMSUBSS
XED_ICLASS_VFMULCPH
XED_ICLASS_VFMULCSH
XED_ICLASS_VFNMADD132PD
XED_ICLASS_VFNMADD132PH
XED_ICLASS_VFNMADD132PS
XED_ICLASS_VFNMADD132SD
XED_ICLASS_VFNMADD132SH
XED_ICLASS_VFNMADD132SS
XED_ICLASS_VFNMADD213PD
XED_ICLASS_VFNMADD213PH
XED_ICLASS_VFNMADD213PS
XED_ICLASS_VFNMADD213SD
XED_ICLASS_VFNMADD213SH
XED_ICLASS_VFNMADD213SS
XED_ICLASS_VFNMADD231PD
XED_ICLASS_VFNMADD231PH
XED_ICLASS_VFNMADD231PS
XED_ICLASS_VFNMADD231SD
XED_ICLASS_VFNMADD231SH
XED_ICLASS_VFNMADD231SS
XED_ICLASS_VFNMADDPD
XED_ICLASS_VFNMADDPS
XED_ICLASS_VFNMADDSD
XED_ICLASS_VFNMADDSS
XED_ICLASS_VFNMSUB132PD
XED_ICLASS_VFNMSUB132PH
XED_ICLASS_VFNMSUB132PS
XED_ICLASS_VFNMSUB132SD
XED_ICLASS_VFNMSUB132SH
XED_ICLASS_VFNMSUB132SS
XED_ICLASS_VFNMSUB213PD
XED_ICLASS_VFNMSUB213PH
XED_ICLASS_VFNMSUB213PS
XED_ICLASS_VFNMSUB213SD
XED_ICLASS_VFNMSUB213SH
XED_ICLASS_VFNMSUB213SS
XED_ICLASS_VFNMSUB231PD
XED_ICLASS_VFNMSUB231PH
XED_ICLASS_VFNMSUB231PS
XED_ICLASS_VFNMSUB231SD
XED_ICLASS_VFNMSUB231SH
XED_ICLASS_VFNMSUB231SS
XED_ICLASS_VFNMSUBPD
XED_ICLASS_VFNMSUBPS
XED_ICLASS_VFNMSUBSD
XED_ICLASS_VFNMSUBSS
XED_ICLASS_VFPCLASSPD
XED_ICLASS_VFPCLASSPH
XED_ICLASS_VFPCLASSPS
XED_ICLASS_VFPCLASSSD
XED_ICLASS_VFPCLASSSH
XED_ICLASS_VFPCLASSSS
XED_ICLASS_VFRCZPD
XED_ICLASS_VFRCZPS
XED_ICLASS_VFRCZSD
XED_ICLASS_VFRCZSS
XED_ICLASS_VGATHERDPD
XED_ICLASS_VGATHERDPS
XED_ICLASS_VGATHERPF0DPD
XED_ICLASS_VGATHERPF0DPS
XED_ICLASS_VGATHERPF0QPD
XED_ICLASS_VGATHERPF0QPS
XED_ICLASS_VGATHERPF1DPD
XED_ICLASS_VGATHERPF1DPS
XED_ICLASS_VGATHERPF1QPD
XED_ICLASS_VGATHERPF1QPS
XED_ICLASS_VGATHERQPD
XED_ICLASS_VGATHERQPS
XED_ICLASS_VGETEXPPD
XED_ICLASS_VGETEXPPH
XED_ICLASS_VGETEXPPS
XED_ICLASS_VGETEXPSD
XED_ICLASS_VGETEXPSH
XED_ICLASS_VGETEXPSS
XED_ICLASS_VGETMANTPD
XED_ICLASS_VGETMANTPH
XED_ICLASS_VGETMANTPS
XED_ICLASS_VGETMANTSD
XED_ICLASS_VGETMANTSH
XED_ICLASS_VGETMANTSS
XED_ICLASS_VGF2P8AFFINEINVQB
XED_ICLASS_VGF2P8AFFINEQB
XED_ICLASS_VGF2P8MULB
XED_ICLASS_VHADDPD
XED_ICLASS_VHADDPS
XED_ICLASS_VHSUBPD
XED_ICLASS_VHSUBPS
XED_ICLASS_VINSERTF32X4
XED_ICLASS_VINSERTF32X8
XED_ICLASS_VINSERTF64X2
XED_ICLASS_VINSERTF64X4
XED_ICLASS_VINSERTF128
XED_ICLASS_VINSERTI32X4
XED_ICLASS_VINSERTI32X8
XED_ICLASS_VINSERTI64X2
XED_ICLASS_VINSERTI64X4
XED_ICLASS_VINSERTI128
XED_ICLASS_VINSERTPS
XED_ICLASS_VLDDQU
XED_ICLASS_VLDMXCSR
XED_ICLASS_VMASKMOVDQU
XED_ICLASS_VMASKMOVPD
XED_ICLASS_VMASKMOVPS
XED_ICLASS_VMAXPD
XED_ICLASS_VMAXPH
XED_ICLASS_VMAXPS
XED_ICLASS_VMAXSD
XED_ICLASS_VMAXSH
XED_ICLASS_VMAXSS
XED_ICLASS_VMCALL
XED_ICLASS_VMCLEAR
XED_ICLASS_VMFUNC
XED_ICLASS_VMINPD
XED_ICLASS_VMINPH
XED_ICLASS_VMINPS
XED_ICLASS_VMINSD
XED_ICLASS_VMINSH
XED_ICLASS_VMINSS
XED_ICLASS_VMLAUNCH
XED_ICLASS_VMLOAD
XED_ICLASS_VMMCALL
XED_ICLASS_VMOVAPD
XED_ICLASS_VMOVAPS
XED_ICLASS_VMOVD
XED_ICLASS_VMOVDDUP
XED_ICLASS_VMOVDQA
XED_ICLASS_VMOVDQA32
XED_ICLASS_VMOVDQA64
XED_ICLASS_VMOVDQU
XED_ICLASS_VMOVDQU8
XED_ICLASS_VMOVDQU16
XED_ICLASS_VMOVDQU32
XED_ICLASS_VMOVDQU64
XED_ICLASS_VMOVHLPS
XED_ICLASS_VMOVHPD
XED_ICLASS_VMOVHPS
XED_ICLASS_VMOVLHPS
XED_ICLASS_VMOVLPD
XED_ICLASS_VMOVLPS
XED_ICLASS_VMOVMSKPD
XED_ICLASS_VMOVMSKPS
XED_ICLASS_VMOVNTDQ
XED_ICLASS_VMOVNTDQA
XED_ICLASS_VMOVNTPD
XED_ICLASS_VMOVNTPS
XED_ICLASS_VMOVQ
XED_ICLASS_VMOVSD
XED_ICLASS_VMOVSH
XED_ICLASS_VMOVSHDUP
XED_ICLASS_VMOVSLDUP
XED_ICLASS_VMOVSS
XED_ICLASS_VMOVUPD
XED_ICLASS_VMOVUPS
XED_ICLASS_VMOVW
XED_ICLASS_VMPSADBW
XED_ICLASS_VMPTRLD
XED_ICLASS_VMPTRST
XED_ICLASS_VMREAD
XED_ICLASS_VMRESUME
XED_ICLASS_VMRUN
XED_ICLASS_VMSAVE
XED_ICLASS_VMULPD
XED_ICLASS_VMULPH
XED_ICLASS_VMULPS
XED_ICLASS_VMULSD
XED_ICLASS_VMULSH
XED_ICLASS_VMULSS
XED_ICLASS_VMWRITE
XED_ICLASS_VMXOFF
XED_ICLASS_VMXON
XED_ICLASS_VORPD
XED_ICLASS_VORPS
XED_ICLASS_VP2INTERSECTD
XED_ICLASS_VP2INTERSECTQ
XED_ICLASS_VP4DPWSSD
XED_ICLASS_VP4DPWSSDS
XED_ICLASS_VPABSB
XED_ICLASS_VPABSD
XED_ICLASS_VPABSQ
XED_ICLASS_VPABSW
XED_ICLASS_VPACKSSDW
XED_ICLASS_VPACKSSWB
XED_ICLASS_VPACKUSDW
XED_ICLASS_VPACKUSWB
XED_ICLASS_VPADDB
XED_ICLASS_VPADDD
XED_ICLASS_VPADDQ
XED_ICLASS_VPADDSB
XED_ICLASS_VPADDSW
XED_ICLASS_VPADDUSB
XED_ICLASS_VPADDUSW
XED_ICLASS_VPADDW
XED_ICLASS_VPALIGNR
XED_ICLASS_VPAND
XED_ICLASS_VPANDD
XED_ICLASS_VPANDN
XED_ICLASS_VPANDND
XED_ICLASS_VPANDNQ
XED_ICLASS_VPANDQ
XED_ICLASS_VPAVGB
XED_ICLASS_VPAVGW
XED_ICLASS_VPBLENDD
XED_ICLASS_VPBLENDMB
XED_ICLASS_VPBLENDMD
XED_ICLASS_VPBLENDMQ
XED_ICLASS_VPBLENDMW
XED_ICLASS_VPBLENDVB
XED_ICLASS_VPBLENDW
XED_ICLASS_VPBROADCASTB
XED_ICLASS_VPBROADCASTD
XED_ICLASS_VPBROADCASTMB2Q
XED_ICLASS_VPBROADCASTMW2D
XED_ICLASS_VPBROADCASTQ
XED_ICLASS_VPBROADCASTW
XED_ICLASS_VPCLMULQDQ
XED_ICLASS_VPCMOV
XED_ICLASS_VPCMPB
XED_ICLASS_VPCMPD
XED_ICLASS_VPCMPEQB
XED_ICLASS_VPCMPEQD
XED_ICLASS_VPCMPEQQ
XED_ICLASS_VPCMPEQW
XED_ICLASS_VPCMPESTRI
XED_ICLASS_VPCMPESTRI64
XED_ICLASS_VPCMPESTRM
XED_ICLASS_VPCMPESTRM64
XED_ICLASS_VPCMPGTB
XED_ICLASS_VPCMPGTD
XED_ICLASS_VPCMPGTQ
XED_ICLASS_VPCMPGTW
XED_ICLASS_VPCMPISTRI
XED_ICLASS_VPCMPISTRI64
XED_ICLASS_VPCMPISTRM
XED_ICLASS_VPCMPQ
XED_ICLASS_VPCMPUB
XED_ICLASS_VPCMPUD
XED_ICLASS_VPCMPUQ
XED_ICLASS_VPCMPUW
XED_ICLASS_VPCMPW
XED_ICLASS_VPCOMB
XED_ICLASS_VPCOMD
XED_ICLASS_VPCOMPRESSB
XED_ICLASS_VPCOMPRESSD
XED_ICLASS_VPCOMPRESSQ
XED_ICLASS_VPCOMPRESSW
XED_ICLASS_VPCOMQ
XED_ICLASS_VPCOMUB
XED_ICLASS_VPCOMUD
XED_ICLASS_VPCOMUQ
XED_ICLASS_VPCOMUW
XED_ICLASS_VPCOMW
XED_ICLASS_VPCONFLICTD
XED_ICLASS_VPCONFLICTQ
XED_ICLASS_VPDPBSSD
XED_ICLASS_VPDPBSSDS
XED_ICLASS_VPDPBSUD
XED_ICLASS_VPDPBSUDS
XED_ICLASS_VPDPBUSD
XED_ICLASS_VPDPBUSDS
XED_ICLASS_VPDPBUUD
XED_ICLASS_VPDPBUUDS
XED_ICLASS_VPDPWSSD
XED_ICLASS_VPDPWSSDS
XED_ICLASS_VPDPWSUD
XED_ICLASS_VPDPWSUDS
XED_ICLASS_VPDPWUSD
XED_ICLASS_VPDPWUSDS
XED_ICLASS_VPDPWUUD
XED_ICLASS_VPDPWUUDS
XED_ICLASS_VPERM2F128
XED_ICLASS_VPERM2I128
XED_ICLASS_VPERMB
XED_ICLASS_VPERMD
XED_ICLASS_VPERMI2B
XED_ICLASS_VPERMI2D
XED_ICLASS_VPERMI2PD
XED_ICLASS_VPERMI2PS
XED_ICLASS_VPERMI2Q
XED_ICLASS_VPERMI2W
XED_ICLASS_VPERMIL2PD
XED_ICLASS_VPERMIL2PS
XED_ICLASS_VPERMILPD
XED_ICLASS_VPERMILPS
XED_ICLASS_VPERMPD
XED_ICLASS_VPERMPS
XED_ICLASS_VPERMQ
XED_ICLASS_VPERMT2B
XED_ICLASS_VPERMT2D
XED_ICLASS_VPERMT2PD
XED_ICLASS_VPERMT2PS
XED_ICLASS_VPERMT2Q
XED_ICLASS_VPERMT2W
XED_ICLASS_VPERMW
XED_ICLASS_VPEXPANDB
XED_ICLASS_VPEXPANDD
XED_ICLASS_VPEXPANDQ
XED_ICLASS_VPEXPANDW
XED_ICLASS_VPEXTRB
XED_ICLASS_VPEXTRD
XED_ICLASS_VPEXTRQ
XED_ICLASS_VPEXTRW
XED_ICLASS_VPEXTRW_C5
XED_ICLASS_VPGATHERDD
XED_ICLASS_VPGATHERDQ
XED_ICLASS_VPGATHERQD
XED_ICLASS_VPGATHERQQ
XED_ICLASS_VPHADDBD
XED_ICLASS_VPHADDBQ
XED_ICLASS_VPHADDBW
XED_ICLASS_VPHADDD
XED_ICLASS_VPHADDDQ
XED_ICLASS_VPHADDSW
XED_ICLASS_VPHADDUBD
XED_ICLASS_VPHADDUBQ
XED_ICLASS_VPHADDUBW
XED_ICLASS_VPHADDUDQ
XED_ICLASS_VPHADDUWD
XED_ICLASS_VPHADDUWQ
XED_ICLASS_VPHADDW
XED_ICLASS_VPHADDWD
XED_ICLASS_VPHADDWQ
XED_ICLASS_VPHMINPOSUW
XED_ICLASS_VPHSUBBW
XED_ICLASS_VPHSUBD
XED_ICLASS_VPHSUBDQ
XED_ICLASS_VPHSUBSW
XED_ICLASS_VPHSUBW
XED_ICLASS_VPHSUBWD
XED_ICLASS_VPINSRB
XED_ICLASS_VPINSRD
XED_ICLASS_VPINSRQ
XED_ICLASS_VPINSRW
XED_ICLASS_VPLZCNTD
XED_ICLASS_VPLZCNTQ
XED_ICLASS_VPMACSDD
XED_ICLASS_VPMACSDQH
XED_ICLASS_VPMACSDQL
XED_ICLASS_VPMACSSDD
XED_ICLASS_VPMACSSDQH
XED_ICLASS_VPMACSSDQL
XED_ICLASS_VPMACSSWD
XED_ICLASS_VPMACSSWW
XED_ICLASS_VPMACSWD
XED_ICLASS_VPMACSWW
XED_ICLASS_VPMADCSSWD
XED_ICLASS_VPMADCSWD
XED_ICLASS_VPMADD52HUQ
XED_ICLASS_VPMADD52LUQ
XED_ICLASS_VPMADDUBSW
XED_ICLASS_VPMADDWD
XED_ICLASS_VPMASKMOVD
XED_ICLASS_VPMASKMOVQ
XED_ICLASS_VPMAXSB
XED_ICLASS_VPMAXSD
XED_ICLASS_VPMAXSQ
XED_ICLASS_VPMAXSW
XED_ICLASS_VPMAXUB
XED_ICLASS_VPMAXUD
XED_ICLASS_VPMAXUQ
XED_ICLASS_VPMAXUW
XED_ICLASS_VPMINSB
XED_ICLASS_VPMINSD
XED_ICLASS_VPMINSQ
XED_ICLASS_VPMINSW
XED_ICLASS_VPMINUB
XED_ICLASS_VPMINUD
XED_ICLASS_VPMINUQ
XED_ICLASS_VPMINUW
XED_ICLASS_VPMOVB2M
XED_ICLASS_VPMOVD2M
XED_ICLASS_VPMOVDB
XED_ICLASS_VPMOVDW
XED_ICLASS_VPMOVM2B
XED_ICLASS_VPMOVM2D
XED_ICLASS_VPMOVM2Q
XED_ICLASS_VPMOVM2W
XED_ICLASS_VPMOVMSKB
XED_ICLASS_VPMOVQ2M
XED_ICLASS_VPMOVQB
XED_ICLASS_VPMOVQD
XED_ICLASS_VPMOVQW
XED_ICLASS_VPMOVSDB
XED_ICLASS_VPMOVSDW
XED_ICLASS_VPMOVSQB
XED_ICLASS_VPMOVSQD
XED_ICLASS_VPMOVSQW
XED_ICLASS_VPMOVSWB
XED_ICLASS_VPMOVSXBD
XED_ICLASS_VPMOVSXBQ
XED_ICLASS_VPMOVSXBW
XED_ICLASS_VPMOVSXDQ
XED_ICLASS_VPMOVSXWD
XED_ICLASS_VPMOVSXWQ
XED_ICLASS_VPMOVUSDB
XED_ICLASS_VPMOVUSDW
XED_ICLASS_VPMOVUSQB
XED_ICLASS_VPMOVUSQD
XED_ICLASS_VPMOVUSQW
XED_ICLASS_VPMOVUSWB
XED_ICLASS_VPMOVW2M
XED_ICLASS_VPMOVWB
XED_ICLASS_VPMOVZXBD
XED_ICLASS_VPMOVZXBQ
XED_ICLASS_VPMOVZXBW
XED_ICLASS_VPMOVZXDQ
XED_ICLASS_VPMOVZXWD
XED_ICLASS_VPMOVZXWQ
XED_ICLASS_VPMULDQ
XED_ICLASS_VPMULHRSW
XED_ICLASS_VPMULHUW
XED_ICLASS_VPMULHW
XED_ICLASS_VPMULLD
XED_ICLASS_VPMULLQ
XED_ICLASS_VPMULLW
XED_ICLASS_VPMULTISHIFTQB
XED_ICLASS_VPMULUDQ
XED_ICLASS_VPOPCNTB
XED_ICLASS_VPOPCNTD
XED_ICLASS_VPOPCNTQ
XED_ICLASS_VPOPCNTW
XED_ICLASS_VPOR
XED_ICLASS_VPORD
XED_ICLASS_VPORQ
XED_ICLASS_VPPERM
XED_ICLASS_VPROLD
XED_ICLASS_VPROLQ
XED_ICLASS_VPROLVD
XED_ICLASS_VPROLVQ
XED_ICLASS_VPRORD
XED_ICLASS_VPRORQ
XED_ICLASS_VPRORVD
XED_ICLASS_VPRORVQ
XED_ICLASS_VPROTB
XED_ICLASS_VPROTD
XED_ICLASS_VPROTQ
XED_ICLASS_VPROTW
XED_ICLASS_VPSADBW
XED_ICLASS_VPSCATTERDD
XED_ICLASS_VPSCATTERDQ
XED_ICLASS_VPSCATTERQD
XED_ICLASS_VPSCATTERQQ
XED_ICLASS_VPSHAB
XED_ICLASS_VPSHAD
XED_ICLASS_VPSHAQ
XED_ICLASS_VPSHAW
XED_ICLASS_VPSHLB
XED_ICLASS_VPSHLD
XED_ICLASS_VPSHLDD
XED_ICLASS_VPSHLDQ
XED_ICLASS_VPSHLDVD
XED_ICLASS_VPSHLDVQ
XED_ICLASS_VPSHLDVW
XED_ICLASS_VPSHLDW
XED_ICLASS_VPSHLQ
XED_ICLASS_VPSHLW
XED_ICLASS_VPSHRDD
XED_ICLASS_VPSHRDQ
XED_ICLASS_VPSHRDVD
XED_ICLASS_VPSHRDVQ
XED_ICLASS_VPSHRDVW
XED_ICLASS_VPSHRDW
XED_ICLASS_VPSHUFB
XED_ICLASS_VPSHUFBITQMB
XED_ICLASS_VPSHUFD
XED_ICLASS_VPSHUFHW
XED_ICLASS_VPSHUFLW
XED_ICLASS_VPSIGNB
XED_ICLASS_VPSIGND
XED_ICLASS_VPSIGNW
XED_ICLASS_VPSLLD
XED_ICLASS_VPSLLDQ
XED_ICLASS_VPSLLQ
XED_ICLASS_VPSLLVD
XED_ICLASS_VPSLLVQ
XED_ICLASS_VPSLLVW
XED_ICLASS_VPSLLW
XED_ICLASS_VPSRAD
XED_ICLASS_VPSRAQ
XED_ICLASS_VPSRAVD
XED_ICLASS_VPSRAVQ
XED_ICLASS_VPSRAVW
XED_ICLASS_VPSRAW
XED_ICLASS_VPSRLD
XED_ICLASS_VPSRLDQ
XED_ICLASS_VPSRLQ
XED_ICLASS_VPSRLVD
XED_ICLASS_VPSRLVQ
XED_ICLASS_VPSRLVW
XED_ICLASS_VPSRLW
XED_ICLASS_VPSUBB
XED_ICLASS_VPSUBD
XED_ICLASS_VPSUBQ
XED_ICLASS_VPSUBSB
XED_ICLASS_VPSUBSW
XED_ICLASS_VPSUBUSB
XED_ICLASS_VPSUBUSW
XED_ICLASS_VPSUBW
XED_ICLASS_VPTERNLOGD
XED_ICLASS_VPTERNLOGQ
XED_ICLASS_VPTEST
XED_ICLASS_VPTESTMB
XED_ICLASS_VPTESTMD
XED_ICLASS_VPTESTMQ
XED_ICLASS_VPTESTMW
XED_ICLASS_VPTESTNMB
XED_ICLASS_VPTESTNMD
XED_ICLASS_VPTESTNMQ
XED_ICLASS_VPTESTNMW
XED_ICLASS_VPUNPCKHBW
XED_ICLASS_VPUNPCKHDQ
XED_ICLASS_VPUNPCKHQDQ
XED_ICLASS_VPUNPCKHWD
XED_ICLASS_VPUNPCKLBW
XED_ICLASS_VPUNPCKLDQ
XED_ICLASS_VPUNPCKLQDQ
XED_ICLASS_VPUNPCKLWD
XED_ICLASS_VPXOR
XED_ICLASS_VPXORD
XED_ICLASS_VPXORQ
XED_ICLASS_VRANGEPD
XED_ICLASS_VRANGEPS
XED_ICLASS_VRANGESD
XED_ICLASS_VRANGESS
XED_ICLASS_VRCP14PD
XED_ICLASS_VRCP14PS
XED_ICLASS_VRCP14SD
XED_ICLASS_VRCP14SS
XED_ICLASS_VRCP28PD
XED_ICLASS_VRCP28PS
XED_ICLASS_VRCP28SD
XED_ICLASS_VRCP28SS
XED_ICLASS_VRCPPH
XED_ICLASS_VRCPPS
XED_ICLASS_VRCPSH
XED_ICLASS_VRCPSS
XED_ICLASS_VREDUCEPD
XED_ICLASS_VREDUCEPH
XED_ICLASS_VREDUCEPS
XED_ICLASS_VREDUCESD
XED_ICLASS_VREDUCESH
XED_ICLASS_VREDUCESS
XED_ICLASS_VRNDSCALEPD
XED_ICLASS_VRNDSCALEPH
XED_ICLASS_VRNDSCALEPS
XED_ICLASS_VRNDSCALESD
XED_ICLASS_VRNDSCALESH
XED_ICLASS_VRNDSCALESS
XED_ICLASS_VROUNDPD
XED_ICLASS_VROUNDPS
XED_ICLASS_VROUNDSD
XED_ICLASS_VROUNDSS
XED_ICLASS_VRSQRT14PD
XED_ICLASS_VRSQRT14PS
XED_ICLASS_VRSQRT14SD
XED_ICLASS_VRSQRT14SS
XED_ICLASS_VRSQRT28PD
XED_ICLASS_VRSQRT28PS
XED_ICLASS_VRSQRT28SD
XED_ICLASS_VRSQRT28SS
XED_ICLASS_VRSQRTPH
XED_ICLASS_VRSQRTPS
XED_ICLASS_VRSQRTSH
XED_ICLASS_VRSQRTSS
XED_ICLASS_VSCALEFPD
XED_ICLASS_VSCALEFPH
XED_ICLASS_VSCALEFPS
XED_ICLASS_VSCALEFSD
XED_ICLASS_VSCALEFSH
XED_ICLASS_VSCALEFSS
XED_ICLASS_VSCATTERDPD
XED_ICLASS_VSCATTERDPS
XED_ICLASS_VSCATTERPF0DPD
XED_ICLASS_VSCATTERPF0DPS
XED_ICLASS_VSCATTERPF0QPD
XED_ICLASS_VSCATTERPF0QPS
XED_ICLASS_VSCATTERPF1DPD
XED_ICLASS_VSCATTERPF1DPS
XED_ICLASS_VSCATTERPF1QPD
XED_ICLASS_VSCATTERPF1QPS
XED_ICLASS_VSCATTERQPD
XED_ICLASS_VSCATTERQPS
XED_ICLASS_VSHA512MSG1
XED_ICLASS_VSHA512MSG2
XED_ICLASS_VSHA512RNDS2
XED_ICLASS_VSHUFF32X4
XED_ICLASS_VSHUFF64X2
XED_ICLASS_VSHUFI32X4
XED_ICLASS_VSHUFI64X2
XED_ICLASS_VSHUFPD
XED_ICLASS_VSHUFPS
XED_ICLASS_VSM3MSG1
XED_ICLASS_VSM3MSG2
XED_ICLASS_VSM3RNDS2
XED_ICLASS_VSM4KEY4
XED_ICLASS_VSM4RNDS4
XED_ICLASS_VSQRTPD
XED_ICLASS_VSQRTPH
XED_ICLASS_VSQRTPS
XED_ICLASS_VSQRTSD
XED_ICLASS_VSQRTSH
XED_ICLASS_VSQRTSS
XED_ICLASS_VSTMXCSR
XED_ICLASS_VSUBPD
XED_ICLASS_VSUBPH
XED_ICLASS_VSUBPS
XED_ICLASS_VSUBSD
XED_ICLASS_VSUBSH
XED_ICLASS_VSUBSS
XED_ICLASS_VTESTPD
XED_ICLASS_VTESTPS
XED_ICLASS_VUCOMISD
XED_ICLASS_VUCOMISH
XED_ICLASS_VUCOMISS
XED_ICLASS_VUNPCKHPD
XED_ICLASS_VUNPCKHPS
XED_ICLASS_VUNPCKLPD
XED_ICLASS_VUNPCKLPS
XED_ICLASS_VXORPD
XED_ICLASS_VXORPS
XED_ICLASS_VZEROALL
XED_ICLASS_VZEROUPPER
XED_ICLASS_WBINVD
XED_ICLASS_WBNOINVD
XED_ICLASS_WRFSBASE
XED_ICLASS_WRGSBASE
XED_ICLASS_WRMSR
XED_ICLASS_WRMSRLIST
XED_ICLASS_WRMSRNS
XED_ICLASS_WRPKRU
XED_ICLASS_WRSSD
XED_ICLASS_WRSSQ
XED_ICLASS_WRUSSD
XED_ICLASS_WRUSSQ
XED_ICLASS_XABORT
XED_ICLASS_XADD
XED_ICLASS_XADD_LOCK
XED_ICLASS_XBEGIN
XED_ICLASS_XCHG
XED_ICLASS_XEND
XED_ICLASS_XGETBV
XED_ICLASS_XLAT
XED_ICLASS_XOR
XED_ICLASS_XORPD
XED_ICLASS_XORPS
XED_ICLASS_XOR_LOCK
XED_ICLASS_XRESLDTRK
XED_ICLASS_XRSTOR
XED_ICLASS_XRSTOR64
XED_ICLASS_XRSTORS
XED_ICLASS_XRSTORS64
XED_ICLASS_XSAVE
XED_ICLASS_XSAVE64
XED_ICLASS_XSAVEC
XED_ICLASS_XSAVEC64
XED_ICLASS_XSAVEOPT
XED_ICLASS_XSAVEOPT64
XED_ICLASS_XSAVES
XED_ICLASS_XSAVES64
XED_ICLASS_XSETBV
XED_ICLASS_XSTORE
XED_ICLASS_XSUSLDTRK
XED_ICLASS_XTEST
XED_IFORMFL_AAA_FIRST
XED_IFORMFL_AAA_LAST
XED_IFORMFL_AADD_FIRST
XED_IFORMFL_AADD_LAST
XED_IFORMFL_AAD_FIRST
XED_IFORMFL_AAD_LAST
XED_IFORMFL_AAM_FIRST
XED_IFORMFL_AAM_LAST
XED_IFORMFL_AAND_FIRST
XED_IFORMFL_AAND_LAST
XED_IFORMFL_AAS_FIRST
XED_IFORMFL_AAS_LAST
XED_IFORMFL_ADCX_FIRST
XED_IFORMFL_ADCX_LAST
XED_IFORMFL_ADC_FIRST
XED_IFORMFL_ADC_LAST
XED_IFORMFL_ADC_LOCK_FIRST
XED_IFORMFL_ADC_LOCK_LAST
XED_IFORMFL_ADDPD_FIRST
XED_IFORMFL_ADDPD_LAST
XED_IFORMFL_ADDPS_FIRST
XED_IFORMFL_ADDPS_LAST
XED_IFORMFL_ADDSD_FIRST
XED_IFORMFL_ADDSD_LAST
XED_IFORMFL_ADDSS_FIRST
XED_IFORMFL_ADDSS_LAST
XED_IFORMFL_ADDSUBPD_FIRST
XED_IFORMFL_ADDSUBPD_LAST
XED_IFORMFL_ADDSUBPS_FIRST
XED_IFORMFL_ADDSUBPS_LAST
XED_IFORMFL_ADD_FIRST
XED_IFORMFL_ADD_LAST
XED_IFORMFL_ADD_LOCK_FIRST
XED_IFORMFL_ADD_LOCK_LAST
XED_IFORMFL_ADOX_FIRST
XED_IFORMFL_ADOX_LAST
XED_IFORMFL_AESDEC128KL_FIRST
XED_IFORMFL_AESDEC128KL_LAST
XED_IFORMFL_AESDEC256KL_FIRST
XED_IFORMFL_AESDEC256KL_LAST
XED_IFORMFL_AESDECLAST_FIRST
XED_IFORMFL_AESDECLAST_LAST
XED_IFORMFL_AESDECWIDE128KL_FIRST
XED_IFORMFL_AESDECWIDE128KL_LAST
XED_IFORMFL_AESDECWIDE256KL_FIRST
XED_IFORMFL_AESDECWIDE256KL_LAST
XED_IFORMFL_AESDEC_FIRST
XED_IFORMFL_AESDEC_LAST
XED_IFORMFL_AESENC128KL_FIRST
XED_IFORMFL_AESENC128KL_LAST
XED_IFORMFL_AESENC256KL_FIRST
XED_IFORMFL_AESENC256KL_LAST
XED_IFORMFL_AESENCLAST_FIRST
XED_IFORMFL_AESENCLAST_LAST
XED_IFORMFL_AESENCWIDE128KL_FIRST
XED_IFORMFL_AESENCWIDE128KL_LAST
XED_IFORMFL_AESENCWIDE256KL_FIRST
XED_IFORMFL_AESENCWIDE256KL_LAST
XED_IFORMFL_AESENC_FIRST
XED_IFORMFL_AESENC_LAST
XED_IFORMFL_AESIMC_FIRST
XED_IFORMFL_AESIMC_LAST
XED_IFORMFL_AESKEYGENASSIST_FIRST
XED_IFORMFL_AESKEYGENASSIST_LAST
XED_IFORMFL_ANDNPD_FIRST
XED_IFORMFL_ANDNPD_LAST
XED_IFORMFL_ANDNPS_FIRST
XED_IFORMFL_ANDNPS_LAST
XED_IFORMFL_ANDN_FIRST
XED_IFORMFL_ANDN_LAST
XED_IFORMFL_ANDPD_FIRST
XED_IFORMFL_ANDPD_LAST
XED_IFORMFL_ANDPS_FIRST
XED_IFORMFL_ANDPS_LAST
XED_IFORMFL_AND_FIRST
XED_IFORMFL_AND_LAST
XED_IFORMFL_AND_LOCK_FIRST
XED_IFORMFL_AND_LOCK_LAST
XED_IFORMFL_AOR_FIRST
XED_IFORMFL_AOR_LAST
XED_IFORMFL_ARPL_FIRST
XED_IFORMFL_ARPL_LAST
XED_IFORMFL_AXOR_FIRST
XED_IFORMFL_AXOR_LAST
XED_IFORMFL_BEXTR_FIRST
XED_IFORMFL_BEXTR_LAST
XED_IFORMFL_BEXTR_XOP_FIRST
XED_IFORMFL_BEXTR_XOP_LAST
XED_IFORMFL_BLCFILL_FIRST
XED_IFORMFL_BLCFILL_LAST
XED_IFORMFL_BLCIC_FIRST
XED_IFORMFL_BLCIC_LAST
XED_IFORMFL_BLCI_FIRST
XED_IFORMFL_BLCI_LAST
XED_IFORMFL_BLCMSK_FIRST
XED_IFORMFL_BLCMSK_LAST
XED_IFORMFL_BLCS_FIRST
XED_IFORMFL_BLCS_LAST
XED_IFORMFL_BLENDPD_FIRST
XED_IFORMFL_BLENDPD_LAST
XED_IFORMFL_BLENDPS_FIRST
XED_IFORMFL_BLENDPS_LAST
XED_IFORMFL_BLENDVPD_FIRST
XED_IFORMFL_BLENDVPD_LAST
XED_IFORMFL_BLENDVPS_FIRST
XED_IFORMFL_BLENDVPS_LAST
XED_IFORMFL_BLSFILL_FIRST
XED_IFORMFL_BLSFILL_LAST
XED_IFORMFL_BLSIC_FIRST
XED_IFORMFL_BLSIC_LAST
XED_IFORMFL_BLSI_FIRST
XED_IFORMFL_BLSI_LAST
XED_IFORMFL_BLSMSK_FIRST
XED_IFORMFL_BLSMSK_LAST
XED_IFORMFL_BLSR_FIRST
XED_IFORMFL_BLSR_LAST
XED_IFORMFL_BNDCL_FIRST
XED_IFORMFL_BNDCL_LAST
XED_IFORMFL_BNDCN_FIRST
XED_IFORMFL_BNDCN_LAST
XED_IFORMFL_BNDCU_FIRST
XED_IFORMFL_BNDCU_LAST
XED_IFORMFL_BNDLDX_FIRST
XED_IFORMFL_BNDLDX_LAST
XED_IFORMFL_BNDMK_FIRST
XED_IFORMFL_BNDMK_LAST
XED_IFORMFL_BNDMOV_FIRST
XED_IFORMFL_BNDMOV_LAST
XED_IFORMFL_BNDSTX_FIRST
XED_IFORMFL_BNDSTX_LAST
XED_IFORMFL_BOUND_FIRST
XED_IFORMFL_BOUND_LAST
XED_IFORMFL_BSF_FIRST
XED_IFORMFL_BSF_LAST
XED_IFORMFL_BSR_FIRST
XED_IFORMFL_BSR_LAST
XED_IFORMFL_BSWAP_FIRST
XED_IFORMFL_BSWAP_LAST
XED_IFORMFL_BTC_FIRST
XED_IFORMFL_BTC_LAST
XED_IFORMFL_BTC_LOCK_FIRST
XED_IFORMFL_BTC_LOCK_LAST
XED_IFORMFL_BTR_FIRST
XED_IFORMFL_BTR_LAST
XED_IFORMFL_BTR_LOCK_FIRST
XED_IFORMFL_BTR_LOCK_LAST
XED_IFORMFL_BTS_FIRST
XED_IFORMFL_BTS_LAST
XED_IFORMFL_BTS_LOCK_FIRST
XED_IFORMFL_BTS_LOCK_LAST
XED_IFORMFL_BT_FIRST
XED_IFORMFL_BT_LAST
XED_IFORMFL_BZHI_FIRST
XED_IFORMFL_BZHI_LAST
XED_IFORMFL_CALL_FAR_FIRST
XED_IFORMFL_CALL_FAR_LAST
XED_IFORMFL_CALL_NEAR_FIRST
XED_IFORMFL_CALL_NEAR_LAST
XED_IFORMFL_CBW_FIRST
XED_IFORMFL_CBW_LAST
XED_IFORMFL_CCMPBE_FIRST
XED_IFORMFL_CCMPBE_LAST
XED_IFORMFL_CCMPB_FIRST
XED_IFORMFL_CCMPB_LAST
XED_IFORMFL_CCMPF_FIRST
XED_IFORMFL_CCMPF_LAST
XED_IFORMFL_CCMPLE_FIRST
XED_IFORMFL_CCMPLE_LAST
XED_IFORMFL_CCMPL_FIRST
XED_IFORMFL_CCMPL_LAST
XED_IFORMFL_CCMPNBE_FIRST
XED_IFORMFL_CCMPNBE_LAST
XED_IFORMFL_CCMPNB_FIRST
XED_IFORMFL_CCMPNB_LAST
XED_IFORMFL_CCMPNLE_FIRST
XED_IFORMFL_CCMPNLE_LAST
XED_IFORMFL_CCMPNL_FIRST
XED_IFORMFL_CCMPNL_LAST
XED_IFORMFL_CCMPNO_FIRST
XED_IFORMFL_CCMPNO_LAST
XED_IFORMFL_CCMPNS_FIRST
XED_IFORMFL_CCMPNS_LAST
XED_IFORMFL_CCMPNZ_FIRST
XED_IFORMFL_CCMPNZ_LAST
XED_IFORMFL_CCMPO_FIRST
XED_IFORMFL_CCMPO_LAST
XED_IFORMFL_CCMPS_FIRST
XED_IFORMFL_CCMPS_LAST
XED_IFORMFL_CCMPT_FIRST
XED_IFORMFL_CCMPT_LAST
XED_IFORMFL_CCMPZ_FIRST
XED_IFORMFL_CCMPZ_LAST
XED_IFORMFL_CDQE_FIRST
XED_IFORMFL_CDQE_LAST
XED_IFORMFL_CDQ_FIRST
XED_IFORMFL_CDQ_LAST
XED_IFORMFL_CFCMOVBE_FIRST
XED_IFORMFL_CFCMOVBE_LAST
XED_IFORMFL_CFCMOVB_FIRST
XED_IFORMFL_CFCMOVB_LAST
XED_IFORMFL_CFCMOVLE_FIRST
XED_IFORMFL_CFCMOVLE_LAST
XED_IFORMFL_CFCMOVL_FIRST
XED_IFORMFL_CFCMOVL_LAST
XED_IFORMFL_CFCMOVNBE_FIRST
XED_IFORMFL_CFCMOVNBE_LAST
XED_IFORMFL_CFCMOVNB_FIRST
XED_IFORMFL_CFCMOVNB_LAST
XED_IFORMFL_CFCMOVNLE_FIRST
XED_IFORMFL_CFCMOVNLE_LAST
XED_IFORMFL_CFCMOVNL_FIRST
XED_IFORMFL_CFCMOVNL_LAST
XED_IFORMFL_CFCMOVNO_FIRST
XED_IFORMFL_CFCMOVNO_LAST
XED_IFORMFL_CFCMOVNP_FIRST
XED_IFORMFL_CFCMOVNP_LAST
XED_IFORMFL_CFCMOVNS_FIRST
XED_IFORMFL_CFCMOVNS_LAST
XED_IFORMFL_CFCMOVNZ_FIRST
XED_IFORMFL_CFCMOVNZ_LAST
XED_IFORMFL_CFCMOVO_FIRST
XED_IFORMFL_CFCMOVO_LAST
XED_IFORMFL_CFCMOVP_FIRST
XED_IFORMFL_CFCMOVP_LAST
XED_IFORMFL_CFCMOVS_FIRST
XED_IFORMFL_CFCMOVS_LAST
XED_IFORMFL_CFCMOVZ_FIRST
XED_IFORMFL_CFCMOVZ_LAST
XED_IFORMFL_CLAC_FIRST
XED_IFORMFL_CLAC_LAST
XED_IFORMFL_CLC_FIRST
XED_IFORMFL_CLC_LAST
XED_IFORMFL_CLDEMOTE_FIRST
XED_IFORMFL_CLDEMOTE_LAST
XED_IFORMFL_CLD_FIRST
XED_IFORMFL_CLD_LAST
XED_IFORMFL_CLFLUSHOPT_FIRST
XED_IFORMFL_CLFLUSHOPT_LAST
XED_IFORMFL_CLFLUSH_FIRST
XED_IFORMFL_CLFLUSH_LAST
XED_IFORMFL_CLGI_FIRST
XED_IFORMFL_CLGI_LAST
XED_IFORMFL_CLI_FIRST
XED_IFORMFL_CLI_LAST
XED_IFORMFL_CLRSSBSY_FIRST
XED_IFORMFL_CLRSSBSY_LAST
XED_IFORMFL_CLTS_FIRST
XED_IFORMFL_CLTS_LAST
XED_IFORMFL_CLUI_FIRST
XED_IFORMFL_CLUI_LAST
XED_IFORMFL_CLWB_FIRST
XED_IFORMFL_CLWB_LAST
XED_IFORMFL_CLZERO_FIRST
XED_IFORMFL_CLZERO_LAST
XED_IFORMFL_CMC_FIRST
XED_IFORMFL_CMC_LAST
XED_IFORMFL_CMOVBE_FIRST
XED_IFORMFL_CMOVBE_LAST
XED_IFORMFL_CMOVB_FIRST
XED_IFORMFL_CMOVB_LAST
XED_IFORMFL_CMOVLE_FIRST
XED_IFORMFL_CMOVLE_LAST
XED_IFORMFL_CMOVL_FIRST
XED_IFORMFL_CMOVL_LAST
XED_IFORMFL_CMOVNBE_FIRST
XED_IFORMFL_CMOVNBE_LAST
XED_IFORMFL_CMOVNB_FIRST
XED_IFORMFL_CMOVNB_LAST
XED_IFORMFL_CMOVNLE_FIRST
XED_IFORMFL_CMOVNLE_LAST
XED_IFORMFL_CMOVNL_FIRST
XED_IFORMFL_CMOVNL_LAST
XED_IFORMFL_CMOVNO_FIRST
XED_IFORMFL_CMOVNO_LAST
XED_IFORMFL_CMOVNP_FIRST
XED_IFORMFL_CMOVNP_LAST
XED_IFORMFL_CMOVNS_FIRST
XED_IFORMFL_CMOVNS_LAST
XED_IFORMFL_CMOVNZ_FIRST
XED_IFORMFL_CMOVNZ_LAST
XED_IFORMFL_CMOVO_FIRST
XED_IFORMFL_CMOVO_LAST
XED_IFORMFL_CMOVP_FIRST
XED_IFORMFL_CMOVP_LAST
XED_IFORMFL_CMOVS_FIRST
XED_IFORMFL_CMOVS_LAST
XED_IFORMFL_CMOVZ_FIRST
XED_IFORMFL_CMOVZ_LAST
XED_IFORMFL_CMPBEXADD_FIRST
XED_IFORMFL_CMPBEXADD_LAST
XED_IFORMFL_CMPBXADD_FIRST
XED_IFORMFL_CMPBXADD_LAST
XED_IFORMFL_CMPLEXADD_FIRST
XED_IFORMFL_CMPLEXADD_LAST
XED_IFORMFL_CMPLXADD_FIRST
XED_IFORMFL_CMPLXADD_LAST
XED_IFORMFL_CMPNBEXADD_FIRST
XED_IFORMFL_CMPNBEXADD_LAST
XED_IFORMFL_CMPNBXADD_FIRST
XED_IFORMFL_CMPNBXADD_LAST
XED_IFORMFL_CMPNLEXADD_FIRST
XED_IFORMFL_CMPNLEXADD_LAST
XED_IFORMFL_CMPNLXADD_FIRST
XED_IFORMFL_CMPNLXADD_LAST
XED_IFORMFL_CMPNOXADD_FIRST
XED_IFORMFL_CMPNOXADD_LAST
XED_IFORMFL_CMPNPXADD_FIRST
XED_IFORMFL_CMPNPXADD_LAST
XED_IFORMFL_CMPNSXADD_FIRST
XED_IFORMFL_CMPNSXADD_LAST
XED_IFORMFL_CMPNZXADD_FIRST
XED_IFORMFL_CMPNZXADD_LAST
XED_IFORMFL_CMPOXADD_FIRST
XED_IFORMFL_CMPOXADD_LAST
XED_IFORMFL_CMPPD_FIRST
XED_IFORMFL_CMPPD_LAST
XED_IFORMFL_CMPPS_FIRST
XED_IFORMFL_CMPPS_LAST
XED_IFORMFL_CMPPXADD_FIRST
XED_IFORMFL_CMPPXADD_LAST
XED_IFORMFL_CMPSB_FIRST
XED_IFORMFL_CMPSB_LAST
XED_IFORMFL_CMPSD_FIRST
XED_IFORMFL_CMPSD_LAST
XED_IFORMFL_CMPSD_XMM_FIRST
XED_IFORMFL_CMPSD_XMM_LAST
XED_IFORMFL_CMPSQ_FIRST
XED_IFORMFL_CMPSQ_LAST
XED_IFORMFL_CMPSS_FIRST
XED_IFORMFL_CMPSS_LAST
XED_IFORMFL_CMPSW_FIRST
XED_IFORMFL_CMPSW_LAST
XED_IFORMFL_CMPSXADD_FIRST
XED_IFORMFL_CMPSXADD_LAST
XED_IFORMFL_CMPXCHG8B_FIRST
XED_IFORMFL_CMPXCHG8B_LAST
XED_IFORMFL_CMPXCHG8B_LOCK_FIRST
XED_IFORMFL_CMPXCHG8B_LOCK_LAST
XED_IFORMFL_CMPXCHG16B_FIRST
XED_IFORMFL_CMPXCHG16B_LAST
XED_IFORMFL_CMPXCHG16B_LOCK_FIRST
XED_IFORMFL_CMPXCHG16B_LOCK_LAST
XED_IFORMFL_CMPXCHG_FIRST
XED_IFORMFL_CMPXCHG_LAST
XED_IFORMFL_CMPXCHG_LOCK_FIRST
XED_IFORMFL_CMPXCHG_LOCK_LAST
XED_IFORMFL_CMPZXADD_FIRST
XED_IFORMFL_CMPZXADD_LAST
XED_IFORMFL_CMP_FIRST
XED_IFORMFL_CMP_LAST
XED_IFORMFL_COMISD_FIRST
XED_IFORMFL_COMISD_LAST
XED_IFORMFL_COMISS_FIRST
XED_IFORMFL_COMISS_LAST
XED_IFORMFL_CPUID_FIRST
XED_IFORMFL_CPUID_LAST
XED_IFORMFL_CQO_FIRST
XED_IFORMFL_CQO_LAST
XED_IFORMFL_CRC32_FIRST
XED_IFORMFL_CRC32_LAST
XED_IFORMFL_CTESTBE_FIRST
XED_IFORMFL_CTESTBE_LAST
XED_IFORMFL_CTESTB_FIRST
XED_IFORMFL_CTESTB_LAST
XED_IFORMFL_CTESTF_FIRST
XED_IFORMFL_CTESTF_LAST
XED_IFORMFL_CTESTLE_FIRST
XED_IFORMFL_CTESTLE_LAST
XED_IFORMFL_CTESTL_FIRST
XED_IFORMFL_CTESTL_LAST
XED_IFORMFL_CTESTNBE_FIRST
XED_IFORMFL_CTESTNBE_LAST
XED_IFORMFL_CTESTNB_FIRST
XED_IFORMFL_CTESTNB_LAST
XED_IFORMFL_CTESTNLE_FIRST
XED_IFORMFL_CTESTNLE_LAST
XED_IFORMFL_CTESTNL_FIRST
XED_IFORMFL_CTESTNL_LAST
XED_IFORMFL_CTESTNO_FIRST
XED_IFORMFL_CTESTNO_LAST
XED_IFORMFL_CTESTNS_FIRST
XED_IFORMFL_CTESTNS_LAST
XED_IFORMFL_CTESTNZ_FIRST
XED_IFORMFL_CTESTNZ_LAST
XED_IFORMFL_CTESTO_FIRST
XED_IFORMFL_CTESTO_LAST
XED_IFORMFL_CTESTS_FIRST
XED_IFORMFL_CTESTS_LAST
XED_IFORMFL_CTESTT_FIRST
XED_IFORMFL_CTESTT_LAST
XED_IFORMFL_CTESTZ_FIRST
XED_IFORMFL_CTESTZ_LAST
XED_IFORMFL_CVTDQ2PD_FIRST
XED_IFORMFL_CVTDQ2PD_LAST
XED_IFORMFL_CVTDQ2PS_FIRST
XED_IFORMFL_CVTDQ2PS_LAST
XED_IFORMFL_CVTPD2DQ_FIRST
XED_IFORMFL_CVTPD2DQ_LAST
XED_IFORMFL_CVTPD2PI_FIRST
XED_IFORMFL_CVTPD2PI_LAST
XED_IFORMFL_CVTPD2PS_FIRST
XED_IFORMFL_CVTPD2PS_LAST
XED_IFORMFL_CVTPI2PD_FIRST
XED_IFORMFL_CVTPI2PD_LAST
XED_IFORMFL_CVTPI2PS_FIRST
XED_IFORMFL_CVTPI2PS_LAST
XED_IFORMFL_CVTPS2DQ_FIRST
XED_IFORMFL_CVTPS2DQ_LAST
XED_IFORMFL_CVTPS2PD_FIRST
XED_IFORMFL_CVTPS2PD_LAST
XED_IFORMFL_CVTPS2PI_FIRST
XED_IFORMFL_CVTPS2PI_LAST
XED_IFORMFL_CVTSD2SI_FIRST
XED_IFORMFL_CVTSD2SI_LAST
XED_IFORMFL_CVTSD2SS_FIRST
XED_IFORMFL_CVTSD2SS_LAST
XED_IFORMFL_CVTSI2SD_FIRST
XED_IFORMFL_CVTSI2SD_LAST
XED_IFORMFL_CVTSI2SS_FIRST
XED_IFORMFL_CVTSI2SS_LAST
XED_IFORMFL_CVTSS2SD_FIRST
XED_IFORMFL_CVTSS2SD_LAST
XED_IFORMFL_CVTSS2SI_FIRST
XED_IFORMFL_CVTSS2SI_LAST
XED_IFORMFL_CVTTPD2DQ_FIRST
XED_IFORMFL_CVTTPD2DQ_LAST
XED_IFORMFL_CVTTPD2PI_FIRST
XED_IFORMFL_CVTTPD2PI_LAST
XED_IFORMFL_CVTTPS2DQ_FIRST
XED_IFORMFL_CVTTPS2DQ_LAST
XED_IFORMFL_CVTTPS2PI_FIRST
XED_IFORMFL_CVTTPS2PI_LAST
XED_IFORMFL_CVTTSD2SI_FIRST
XED_IFORMFL_CVTTSD2SI_LAST
XED_IFORMFL_CVTTSS2SI_FIRST
XED_IFORMFL_CVTTSS2SI_LAST
XED_IFORMFL_CWDE_FIRST
XED_IFORMFL_CWDE_LAST
XED_IFORMFL_CWD_FIRST
XED_IFORMFL_CWD_LAST
XED_IFORMFL_DAA_FIRST
XED_IFORMFL_DAA_LAST
XED_IFORMFL_DAS_FIRST
XED_IFORMFL_DAS_LAST
XED_IFORMFL_DEC_FIRST
XED_IFORMFL_DEC_LAST
XED_IFORMFL_DEC_LOCK_FIRST
XED_IFORMFL_DEC_LOCK_LAST
XED_IFORMFL_DIVPD_FIRST
XED_IFORMFL_DIVPD_LAST
XED_IFORMFL_DIVPS_FIRST
XED_IFORMFL_DIVPS_LAST
XED_IFORMFL_DIVSD_FIRST
XED_IFORMFL_DIVSD_LAST
XED_IFORMFL_DIVSS_FIRST
XED_IFORMFL_DIVSS_LAST
XED_IFORMFL_DIV_FIRST
XED_IFORMFL_DIV_LAST
XED_IFORMFL_DPPD_FIRST
XED_IFORMFL_DPPD_LAST
XED_IFORMFL_DPPS_FIRST
XED_IFORMFL_DPPS_LAST
XED_IFORMFL_EMMS_FIRST
XED_IFORMFL_EMMS_LAST
XED_IFORMFL_ENCLS_FIRST
XED_IFORMFL_ENCLS_LAST
XED_IFORMFL_ENCLU_FIRST
XED_IFORMFL_ENCLU_LAST
XED_IFORMFL_ENCLV_FIRST
XED_IFORMFL_ENCLV_LAST
XED_IFORMFL_ENCODEKEY128_FIRST
XED_IFORMFL_ENCODEKEY128_LAST
XED_IFORMFL_ENCODEKEY256_FIRST
XED_IFORMFL_ENCODEKEY256_LAST
XED_IFORMFL_ENDBR32_FIRST
XED_IFORMFL_ENDBR32_LAST
XED_IFORMFL_ENDBR64_FIRST
XED_IFORMFL_ENDBR64_LAST
XED_IFORMFL_ENQCMDS_FIRST
XED_IFORMFL_ENQCMDS_LAST
XED_IFORMFL_ENQCMD_FIRST
XED_IFORMFL_ENQCMD_LAST
XED_IFORMFL_ENTER_FIRST
XED_IFORMFL_ENTER_LAST
XED_IFORMFL_ERETS_FIRST
XED_IFORMFL_ERETS_LAST
XED_IFORMFL_ERETU_FIRST
XED_IFORMFL_ERETU_LAST
XED_IFORMFL_EXTRACTPS_FIRST
XED_IFORMFL_EXTRACTPS_LAST
XED_IFORMFL_EXTRQ_FIRST
XED_IFORMFL_EXTRQ_LAST
XED_IFORMFL_F2XM1_FIRST
XED_IFORMFL_F2XM1_LAST
XED_IFORMFL_FABS_FIRST
XED_IFORMFL_FABS_LAST
XED_IFORMFL_FADDP_FIRST
XED_IFORMFL_FADDP_LAST
XED_IFORMFL_FADD_FIRST
XED_IFORMFL_FADD_LAST
XED_IFORMFL_FBLD_FIRST
XED_IFORMFL_FBLD_LAST
XED_IFORMFL_FBSTP_FIRST
XED_IFORMFL_FBSTP_LAST
XED_IFORMFL_FCHS_FIRST
XED_IFORMFL_FCHS_LAST
XED_IFORMFL_FCMOVBE_FIRST
XED_IFORMFL_FCMOVBE_LAST
XED_IFORMFL_FCMOVB_FIRST
XED_IFORMFL_FCMOVB_LAST
XED_IFORMFL_FCMOVE_FIRST
XED_IFORMFL_FCMOVE_LAST
XED_IFORMFL_FCMOVNBE_FIRST
XED_IFORMFL_FCMOVNBE_LAST
XED_IFORMFL_FCMOVNB_FIRST
XED_IFORMFL_FCMOVNB_LAST
XED_IFORMFL_FCMOVNE_FIRST
XED_IFORMFL_FCMOVNE_LAST
XED_IFORMFL_FCMOVNU_FIRST
XED_IFORMFL_FCMOVNU_LAST
XED_IFORMFL_FCMOVU_FIRST
XED_IFORMFL_FCMOVU_LAST
XED_IFORMFL_FCOMIP_FIRST
XED_IFORMFL_FCOMIP_LAST
XED_IFORMFL_FCOMI_FIRST
XED_IFORMFL_FCOMI_LAST
XED_IFORMFL_FCOMPP_FIRST
XED_IFORMFL_FCOMPP_LAST
XED_IFORMFL_FCOMP_FIRST
XED_IFORMFL_FCOMP_LAST
XED_IFORMFL_FCOM_FIRST
XED_IFORMFL_FCOM_LAST
XED_IFORMFL_FCOS_FIRST
XED_IFORMFL_FCOS_LAST
XED_IFORMFL_FDECSTP_FIRST
XED_IFORMFL_FDECSTP_LAST
XED_IFORMFL_FDISI8087_NOP_FIRST
XED_IFORMFL_FDISI8087_NOP_LAST
XED_IFORMFL_FDIVP_FIRST
XED_IFORMFL_FDIVP_LAST
XED_IFORMFL_FDIVRP_FIRST
XED_IFORMFL_FDIVRP_LAST
XED_IFORMFL_FDIVR_FIRST
XED_IFORMFL_FDIVR_LAST
XED_IFORMFL_FDIV_FIRST
XED_IFORMFL_FDIV_LAST
XED_IFORMFL_FEMMS_FIRST
XED_IFORMFL_FEMMS_LAST
XED_IFORMFL_FENI8087_NOP_FIRST
XED_IFORMFL_FENI8087_NOP_LAST
XED_IFORMFL_FFREEP_FIRST
XED_IFORMFL_FFREEP_LAST
XED_IFORMFL_FFREE_FIRST
XED_IFORMFL_FFREE_LAST
XED_IFORMFL_FIADD_FIRST
XED_IFORMFL_FIADD_LAST
XED_IFORMFL_FICOMP_FIRST
XED_IFORMFL_FICOMP_LAST
XED_IFORMFL_FICOM_FIRST
XED_IFORMFL_FICOM_LAST
XED_IFORMFL_FIDIVR_FIRST
XED_IFORMFL_FIDIVR_LAST
XED_IFORMFL_FIDIV_FIRST
XED_IFORMFL_FIDIV_LAST
XED_IFORMFL_FILD_FIRST
XED_IFORMFL_FILD_LAST
XED_IFORMFL_FIMUL_FIRST
XED_IFORMFL_FIMUL_LAST
XED_IFORMFL_FINCSTP_FIRST
XED_IFORMFL_FINCSTP_LAST
XED_IFORMFL_FISTP_FIRST
XED_IFORMFL_FISTP_LAST
XED_IFORMFL_FISTTP_FIRST
XED_IFORMFL_FISTTP_LAST
XED_IFORMFL_FIST_FIRST
XED_IFORMFL_FIST_LAST
XED_IFORMFL_FISUBR_FIRST
XED_IFORMFL_FISUBR_LAST
XED_IFORMFL_FISUB_FIRST
XED_IFORMFL_FISUB_LAST
XED_IFORMFL_FLD1_FIRST
XED_IFORMFL_FLD1_LAST
XED_IFORMFL_FLDCW_FIRST
XED_IFORMFL_FLDCW_LAST
XED_IFORMFL_FLDENV_FIRST
XED_IFORMFL_FLDENV_LAST
XED_IFORMFL_FLDL2E_FIRST
XED_IFORMFL_FLDL2E_LAST
XED_IFORMFL_FLDL2T_FIRST
XED_IFORMFL_FLDL2T_LAST
XED_IFORMFL_FLDLG2_FIRST
XED_IFORMFL_FLDLG2_LAST
XED_IFORMFL_FLDLN2_FIRST
XED_IFORMFL_FLDLN2_LAST
XED_IFORMFL_FLDPI_FIRST
XED_IFORMFL_FLDPI_LAST
XED_IFORMFL_FLDZ_FIRST
XED_IFORMFL_FLDZ_LAST
XED_IFORMFL_FLD_FIRST
XED_IFORMFL_FLD_LAST
XED_IFORMFL_FMULP_FIRST
XED_IFORMFL_FMULP_LAST
XED_IFORMFL_FMUL_FIRST
XED_IFORMFL_FMUL_LAST
XED_IFORMFL_FNCLEX_FIRST
XED_IFORMFL_FNCLEX_LAST
XED_IFORMFL_FNINIT_FIRST
XED_IFORMFL_FNINIT_LAST
XED_IFORMFL_FNOP_FIRST
XED_IFORMFL_FNOP_LAST
XED_IFORMFL_FNSAVE_FIRST
XED_IFORMFL_FNSAVE_LAST
XED_IFORMFL_FNSTCW_FIRST
XED_IFORMFL_FNSTCW_LAST
XED_IFORMFL_FNSTENV_FIRST
XED_IFORMFL_FNSTENV_LAST
XED_IFORMFL_FNSTSW_FIRST
XED_IFORMFL_FNSTSW_LAST
XED_IFORMFL_FPATAN_FIRST
XED_IFORMFL_FPATAN_LAST
XED_IFORMFL_FPREM1_FIRST
XED_IFORMFL_FPREM1_LAST
XED_IFORMFL_FPREM_FIRST
XED_IFORMFL_FPREM_LAST
XED_IFORMFL_FPTAN_FIRST
XED_IFORMFL_FPTAN_LAST
XED_IFORMFL_FRNDINT_FIRST
XED_IFORMFL_FRNDINT_LAST
XED_IFORMFL_FRSTOR_FIRST
XED_IFORMFL_FRSTOR_LAST
XED_IFORMFL_FSCALE_FIRST
XED_IFORMFL_FSCALE_LAST
XED_IFORMFL_FSETPM287_NOP_FIRST
XED_IFORMFL_FSETPM287_NOP_LAST
XED_IFORMFL_FSINCOS_FIRST
XED_IFORMFL_FSINCOS_LAST
XED_IFORMFL_FSIN_FIRST
XED_IFORMFL_FSIN_LAST
XED_IFORMFL_FSQRT_FIRST
XED_IFORMFL_FSQRT_LAST
XED_IFORMFL_FSTPNCE_FIRST
XED_IFORMFL_FSTPNCE_LAST
XED_IFORMFL_FSTP_FIRST
XED_IFORMFL_FSTP_LAST
XED_IFORMFL_FST_FIRST
XED_IFORMFL_FST_LAST
XED_IFORMFL_FSUBP_FIRST
XED_IFORMFL_FSUBP_LAST
XED_IFORMFL_FSUBRP_FIRST
XED_IFORMFL_FSUBRP_LAST
XED_IFORMFL_FSUBR_FIRST
XED_IFORMFL_FSUBR_LAST
XED_IFORMFL_FSUB_FIRST
XED_IFORMFL_FSUB_LAST
XED_IFORMFL_FTST_FIRST
XED_IFORMFL_FTST_LAST
XED_IFORMFL_FUCOMIP_FIRST
XED_IFORMFL_FUCOMIP_LAST
XED_IFORMFL_FUCOMI_FIRST
XED_IFORMFL_FUCOMI_LAST
XED_IFORMFL_FUCOMPP_FIRST
XED_IFORMFL_FUCOMPP_LAST
XED_IFORMFL_FUCOMP_FIRST
XED_IFORMFL_FUCOMP_LAST
XED_IFORMFL_FUCOM_FIRST
XED_IFORMFL_FUCOM_LAST
XED_IFORMFL_FWAIT_FIRST
XED_IFORMFL_FWAIT_LAST
XED_IFORMFL_FXAM_FIRST
XED_IFORMFL_FXAM_LAST
XED_IFORMFL_FXCH_FIRST
XED_IFORMFL_FXCH_LAST
XED_IFORMFL_FXRSTOR64_FIRST
XED_IFORMFL_FXRSTOR64_LAST
XED_IFORMFL_FXRSTOR_FIRST
XED_IFORMFL_FXRSTOR_LAST
XED_IFORMFL_FXSAVE64_FIRST
XED_IFORMFL_FXSAVE64_LAST
XED_IFORMFL_FXSAVE_FIRST
XED_IFORMFL_FXSAVE_LAST
XED_IFORMFL_FXTRACT_FIRST
XED_IFORMFL_FXTRACT_LAST
XED_IFORMFL_FYL2XP1_FIRST
XED_IFORMFL_FYL2XP1_LAST
XED_IFORMFL_FYL2X_FIRST
XED_IFORMFL_FYL2X_LAST
XED_IFORMFL_GETSEC_FIRST
XED_IFORMFL_GETSEC_LAST
XED_IFORMFL_GF2P8AFFINEINVQB_FIRST
XED_IFORMFL_GF2P8AFFINEINVQB_LAST
XED_IFORMFL_GF2P8AFFINEQB_FIRST
XED_IFORMFL_GF2P8AFFINEQB_LAST
XED_IFORMFL_GF2P8MULB_FIRST
XED_IFORMFL_GF2P8MULB_LAST
XED_IFORMFL_HADDPD_FIRST
XED_IFORMFL_HADDPD_LAST
XED_IFORMFL_HADDPS_FIRST
XED_IFORMFL_HADDPS_LAST
XED_IFORMFL_HLT_FIRST
XED_IFORMFL_HLT_LAST
XED_IFORMFL_HRESET_FIRST
XED_IFORMFL_HRESET_LAST
XED_IFORMFL_HSUBPD_FIRST
XED_IFORMFL_HSUBPD_LAST
XED_IFORMFL_HSUBPS_FIRST
XED_IFORMFL_HSUBPS_LAST
XED_IFORMFL_IDIV_FIRST
XED_IFORMFL_IDIV_LAST
XED_IFORMFL_IMUL_FIRST
XED_IFORMFL_IMUL_LAST
XED_IFORMFL_INCSSPD_FIRST
XED_IFORMFL_INCSSPD_LAST
XED_IFORMFL_INCSSPQ_FIRST
XED_IFORMFL_INCSSPQ_LAST
XED_IFORMFL_INC_FIRST
XED_IFORMFL_INC_LAST
XED_IFORMFL_INC_LOCK_FIRST
XED_IFORMFL_INC_LOCK_LAST
XED_IFORMFL_INSB_FIRST
XED_IFORMFL_INSB_LAST
XED_IFORMFL_INSD_FIRST
XED_IFORMFL_INSD_LAST
XED_IFORMFL_INSERTPS_FIRST
XED_IFORMFL_INSERTPS_LAST
XED_IFORMFL_INSERTQ_FIRST
XED_IFORMFL_INSERTQ_LAST
XED_IFORMFL_INSW_FIRST
XED_IFORMFL_INSW_LAST
XED_IFORMFL_INT1_FIRST
XED_IFORMFL_INT1_LAST
XED_IFORMFL_INT3_FIRST
XED_IFORMFL_INT3_LAST
XED_IFORMFL_INTO_FIRST
XED_IFORMFL_INTO_LAST
XED_IFORMFL_INT_FIRST
XED_IFORMFL_INT_LAST
XED_IFORMFL_INVD_FIRST
XED_IFORMFL_INVD_LAST
XED_IFORMFL_INVEPT_FIRST
XED_IFORMFL_INVEPT_LAST
XED_IFORMFL_INVLPGA_FIRST
XED_IFORMFL_INVLPGA_LAST
XED_IFORMFL_INVLPGB_FIRST
XED_IFORMFL_INVLPGB_LAST
XED_IFORMFL_INVLPG_FIRST
XED_IFORMFL_INVLPG_LAST
XED_IFORMFL_INVPCID_FIRST
XED_IFORMFL_INVPCID_LAST
XED_IFORMFL_INVVPID_FIRST
XED_IFORMFL_INVVPID_LAST
XED_IFORMFL_IN_FIRST
XED_IFORMFL_IN_LAST
XED_IFORMFL_IRETD_FIRST
XED_IFORMFL_IRETD_LAST
XED_IFORMFL_IRETQ_FIRST
XED_IFORMFL_IRETQ_LAST
XED_IFORMFL_IRET_FIRST
XED_IFORMFL_IRET_LAST
XED_IFORMFL_JBE_FIRST
XED_IFORMFL_JBE_LAST
XED_IFORMFL_JB_FIRST
XED_IFORMFL_JB_LAST
XED_IFORMFL_JCXZ_FIRST
XED_IFORMFL_JCXZ_LAST
XED_IFORMFL_JECXZ_FIRST
XED_IFORMFL_JECXZ_LAST
XED_IFORMFL_JLE_FIRST
XED_IFORMFL_JLE_LAST
XED_IFORMFL_JL_FIRST
XED_IFORMFL_JL_LAST
XED_IFORMFL_JMPABS_FIRST
XED_IFORMFL_JMPABS_LAST
XED_IFORMFL_JMP_FAR_FIRST
XED_IFORMFL_JMP_FAR_LAST
XED_IFORMFL_JMP_FIRST
XED_IFORMFL_JMP_LAST
XED_IFORMFL_JNBE_FIRST
XED_IFORMFL_JNBE_LAST
XED_IFORMFL_JNB_FIRST
XED_IFORMFL_JNB_LAST
XED_IFORMFL_JNLE_FIRST
XED_IFORMFL_JNLE_LAST
XED_IFORMFL_JNL_FIRST
XED_IFORMFL_JNL_LAST
XED_IFORMFL_JNO_FIRST
XED_IFORMFL_JNO_LAST
XED_IFORMFL_JNP_FIRST
XED_IFORMFL_JNP_LAST
XED_IFORMFL_JNS_FIRST
XED_IFORMFL_JNS_LAST
XED_IFORMFL_JNZ_FIRST
XED_IFORMFL_JNZ_LAST
XED_IFORMFL_JO_FIRST
XED_IFORMFL_JO_LAST
XED_IFORMFL_JP_FIRST
XED_IFORMFL_JP_LAST
XED_IFORMFL_JRCXZ_FIRST
XED_IFORMFL_JRCXZ_LAST
XED_IFORMFL_JS_FIRST
XED_IFORMFL_JS_LAST
XED_IFORMFL_JZ_FIRST
XED_IFORMFL_JZ_LAST
XED_IFORMFL_KADDB_FIRST
XED_IFORMFL_KADDB_LAST
XED_IFORMFL_KADDD_FIRST
XED_IFORMFL_KADDD_LAST
XED_IFORMFL_KADDQ_FIRST
XED_IFORMFL_KADDQ_LAST
XED_IFORMFL_KADDW_FIRST
XED_IFORMFL_KADDW_LAST
XED_IFORMFL_KANDB_FIRST
XED_IFORMFL_KANDB_LAST
XED_IFORMFL_KANDD_FIRST
XED_IFORMFL_KANDD_LAST
XED_IFORMFL_KANDNB_FIRST
XED_IFORMFL_KANDNB_LAST
XED_IFORMFL_KANDND_FIRST
XED_IFORMFL_KANDND_LAST
XED_IFORMFL_KANDNQ_FIRST
XED_IFORMFL_KANDNQ_LAST
XED_IFORMFL_KANDNW_FIRST
XED_IFORMFL_KANDNW_LAST
XED_IFORMFL_KANDQ_FIRST
XED_IFORMFL_KANDQ_LAST
XED_IFORMFL_KANDW_FIRST
XED_IFORMFL_KANDW_LAST
XED_IFORMFL_KMOVB_FIRST
XED_IFORMFL_KMOVB_LAST
XED_IFORMFL_KMOVD_FIRST
XED_IFORMFL_KMOVD_LAST
XED_IFORMFL_KMOVQ_FIRST
XED_IFORMFL_KMOVQ_LAST
XED_IFORMFL_KMOVW_FIRST
XED_IFORMFL_KMOVW_LAST
XED_IFORMFL_KNOTB_FIRST
XED_IFORMFL_KNOTB_LAST
XED_IFORMFL_KNOTD_FIRST
XED_IFORMFL_KNOTD_LAST
XED_IFORMFL_KNOTQ_FIRST
XED_IFORMFL_KNOTQ_LAST
XED_IFORMFL_KNOTW_FIRST
XED_IFORMFL_KNOTW_LAST
XED_IFORMFL_KORB_FIRST
XED_IFORMFL_KORB_LAST
XED_IFORMFL_KORD_FIRST
XED_IFORMFL_KORD_LAST
XED_IFORMFL_KORQ_FIRST
XED_IFORMFL_KORQ_LAST
XED_IFORMFL_KORTESTB_FIRST
XED_IFORMFL_KORTESTB_LAST
XED_IFORMFL_KORTESTD_FIRST
XED_IFORMFL_KORTESTD_LAST
XED_IFORMFL_KORTESTQ_FIRST
XED_IFORMFL_KORTESTQ_LAST
XED_IFORMFL_KORTESTW_FIRST
XED_IFORMFL_KORTESTW_LAST
XED_IFORMFL_KORW_FIRST
XED_IFORMFL_KORW_LAST
XED_IFORMFL_KSHIFTLB_FIRST
XED_IFORMFL_KSHIFTLB_LAST
XED_IFORMFL_KSHIFTLD_FIRST
XED_IFORMFL_KSHIFTLD_LAST
XED_IFORMFL_KSHIFTLQ_FIRST
XED_IFORMFL_KSHIFTLQ_LAST
XED_IFORMFL_KSHIFTLW_FIRST
XED_IFORMFL_KSHIFTLW_LAST
XED_IFORMFL_KSHIFTRB_FIRST
XED_IFORMFL_KSHIFTRB_LAST
XED_IFORMFL_KSHIFTRD_FIRST
XED_IFORMFL_KSHIFTRD_LAST
XED_IFORMFL_KSHIFTRQ_FIRST
XED_IFORMFL_KSHIFTRQ_LAST
XED_IFORMFL_KSHIFTRW_FIRST
XED_IFORMFL_KSHIFTRW_LAST
XED_IFORMFL_KTESTB_FIRST
XED_IFORMFL_KTESTB_LAST
XED_IFORMFL_KTESTD_FIRST
XED_IFORMFL_KTESTD_LAST
XED_IFORMFL_KTESTQ_FIRST
XED_IFORMFL_KTESTQ_LAST
XED_IFORMFL_KTESTW_FIRST
XED_IFORMFL_KTESTW_LAST
XED_IFORMFL_KUNPCKBW_FIRST
XED_IFORMFL_KUNPCKBW_LAST
XED_IFORMFL_KUNPCKDQ_FIRST
XED_IFORMFL_KUNPCKDQ_LAST
XED_IFORMFL_KUNPCKWD_FIRST
XED_IFORMFL_KUNPCKWD_LAST
XED_IFORMFL_KXNORB_FIRST
XED_IFORMFL_KXNORB_LAST
XED_IFORMFL_KXNORD_FIRST
XED_IFORMFL_KXNORD_LAST
XED_IFORMFL_KXNORQ_FIRST
XED_IFORMFL_KXNORQ_LAST
XED_IFORMFL_KXNORW_FIRST
XED_IFORMFL_KXNORW_LAST
XED_IFORMFL_KXORB_FIRST
XED_IFORMFL_KXORB_LAST
XED_IFORMFL_KXORD_FIRST
XED_IFORMFL_KXORD_LAST
XED_IFORMFL_KXORQ_FIRST
XED_IFORMFL_KXORQ_LAST
XED_IFORMFL_KXORW_FIRST
XED_IFORMFL_KXORW_LAST
XED_IFORMFL_LAHF_FIRST
XED_IFORMFL_LAHF_LAST
XED_IFORMFL_LAR_FIRST
XED_IFORMFL_LAR_LAST
XED_IFORMFL_LAST
XED_IFORMFL_LDDQU_FIRST
XED_IFORMFL_LDDQU_LAST
XED_IFORMFL_LDMXCSR_FIRST
XED_IFORMFL_LDMXCSR_LAST
XED_IFORMFL_LDS_FIRST
XED_IFORMFL_LDS_LAST
XED_IFORMFL_LDTILECFG_FIRST
XED_IFORMFL_LDTILECFG_LAST
XED_IFORMFL_LEAVE_FIRST
XED_IFORMFL_LEAVE_LAST
XED_IFORMFL_LEA_FIRST
XED_IFORMFL_LEA_LAST
XED_IFORMFL_LES_FIRST
XED_IFORMFL_LES_LAST
XED_IFORMFL_LFENCE_FIRST
XED_IFORMFL_LFENCE_LAST
XED_IFORMFL_LFS_FIRST
XED_IFORMFL_LFS_LAST
XED_IFORMFL_LGDT_FIRST
XED_IFORMFL_LGDT_LAST
XED_IFORMFL_LGS_FIRST
XED_IFORMFL_LGS_LAST
XED_IFORMFL_LIDT_FIRST
XED_IFORMFL_LIDT_LAST
XED_IFORMFL_LKGS_FIRST
XED_IFORMFL_LKGS_LAST
XED_IFORMFL_LLDT_FIRST
XED_IFORMFL_LLDT_LAST
XED_IFORMFL_LLWPCB_FIRST
XED_IFORMFL_LLWPCB_LAST
XED_IFORMFL_LMSW_FIRST
XED_IFORMFL_LMSW_LAST
XED_IFORMFL_LOADIWKEY_FIRST
XED_IFORMFL_LOADIWKEY_LAST
XED_IFORMFL_LODSB_FIRST
XED_IFORMFL_LODSB_LAST
XED_IFORMFL_LODSD_FIRST
XED_IFORMFL_LODSD_LAST
XED_IFORMFL_LODSQ_FIRST
XED_IFORMFL_LODSQ_LAST
XED_IFORMFL_LODSW_FIRST
XED_IFORMFL_LODSW_LAST
XED_IFORMFL_LOOPE_FIRST
XED_IFORMFL_LOOPE_LAST
XED_IFORMFL_LOOPNE_FIRST
XED_IFORMFL_LOOPNE_LAST
XED_IFORMFL_LOOP_FIRST
XED_IFORMFL_LOOP_LAST
XED_IFORMFL_LSL_FIRST
XED_IFORMFL_LSL_LAST
XED_IFORMFL_LSS_FIRST
XED_IFORMFL_LSS_LAST
XED_IFORMFL_LTR_FIRST
XED_IFORMFL_LTR_LAST
XED_IFORMFL_LWPINS_FIRST
XED_IFORMFL_LWPINS_LAST
XED_IFORMFL_LWPVAL_FIRST
XED_IFORMFL_LWPVAL_LAST
XED_IFORMFL_LZCNT_FIRST
XED_IFORMFL_LZCNT_LAST
XED_IFORMFL_MASKMOVDQU_FIRST
XED_IFORMFL_MASKMOVDQU_LAST
XED_IFORMFL_MASKMOVQ_FIRST
XED_IFORMFL_MASKMOVQ_LAST
XED_IFORMFL_MAXPD_FIRST
XED_IFORMFL_MAXPD_LAST
XED_IFORMFL_MAXPS_FIRST
XED_IFORMFL_MAXPS_LAST
XED_IFORMFL_MAXSD_FIRST
XED_IFORMFL_MAXSD_LAST
XED_IFORMFL_MAXSS_FIRST
XED_IFORMFL_MAXSS_LAST
XED_IFORMFL_MCOMMIT_FIRST
XED_IFORMFL_MCOMMIT_LAST
XED_IFORMFL_MFENCE_FIRST
XED_IFORMFL_MFENCE_LAST
XED_IFORMFL_MINPD_FIRST
XED_IFORMFL_MINPD_LAST
XED_IFORMFL_MINPS_FIRST
XED_IFORMFL_MINPS_LAST
XED_IFORMFL_MINSD_FIRST
XED_IFORMFL_MINSD_LAST
XED_IFORMFL_MINSS_FIRST
XED_IFORMFL_MINSS_LAST
XED_IFORMFL_MONITORX_FIRST
XED_IFORMFL_MONITORX_LAST
XED_IFORMFL_MONITOR_FIRST
XED_IFORMFL_MONITOR_LAST
XED_IFORMFL_MOVAPD_FIRST
XED_IFORMFL_MOVAPD_LAST
XED_IFORMFL_MOVAPS_FIRST
XED_IFORMFL_MOVAPS_LAST
XED_IFORMFL_MOVBE_FIRST
XED_IFORMFL_MOVBE_LAST
XED_IFORMFL_MOVDDUP_FIRST
XED_IFORMFL_MOVDDUP_LAST
XED_IFORMFL_MOVDIR64B_FIRST
XED_IFORMFL_MOVDIR64B_LAST
XED_IFORMFL_MOVDIRI_FIRST
XED_IFORMFL_MOVDIRI_LAST
XED_IFORMFL_MOVDQ2Q_FIRST
XED_IFORMFL_MOVDQ2Q_LAST
XED_IFORMFL_MOVDQA_FIRST
XED_IFORMFL_MOVDQA_LAST
XED_IFORMFL_MOVDQU_FIRST
XED_IFORMFL_MOVDQU_LAST
XED_IFORMFL_MOVD_FIRST
XED_IFORMFL_MOVD_LAST
XED_IFORMFL_MOVHLPS_FIRST
XED_IFORMFL_MOVHLPS_LAST
XED_IFORMFL_MOVHPD_FIRST
XED_IFORMFL_MOVHPD_LAST
XED_IFORMFL_MOVHPS_FIRST
XED_IFORMFL_MOVHPS_LAST
XED_IFORMFL_MOVLHPS_FIRST
XED_IFORMFL_MOVLHPS_LAST
XED_IFORMFL_MOVLPD_FIRST
XED_IFORMFL_MOVLPD_LAST
XED_IFORMFL_MOVLPS_FIRST
XED_IFORMFL_MOVLPS_LAST
XED_IFORMFL_MOVMSKPD_FIRST
XED_IFORMFL_MOVMSKPD_LAST
XED_IFORMFL_MOVMSKPS_FIRST
XED_IFORMFL_MOVMSKPS_LAST
XED_IFORMFL_MOVNTDQA_FIRST
XED_IFORMFL_MOVNTDQA_LAST
XED_IFORMFL_MOVNTDQ_FIRST
XED_IFORMFL_MOVNTDQ_LAST
XED_IFORMFL_MOVNTI_FIRST
XED_IFORMFL_MOVNTI_LAST
XED_IFORMFL_MOVNTPD_FIRST
XED_IFORMFL_MOVNTPD_LAST
XED_IFORMFL_MOVNTPS_FIRST
XED_IFORMFL_MOVNTPS_LAST
XED_IFORMFL_MOVNTQ_FIRST
XED_IFORMFL_MOVNTQ_LAST
XED_IFORMFL_MOVNTSD_FIRST
XED_IFORMFL_MOVNTSD_LAST
XED_IFORMFL_MOVNTSS_FIRST
XED_IFORMFL_MOVNTSS_LAST
XED_IFORMFL_MOVQ2DQ_FIRST
XED_IFORMFL_MOVQ2DQ_LAST
XED_IFORMFL_MOVQ_FIRST
XED_IFORMFL_MOVQ_LAST
XED_IFORMFL_MOVSB_FIRST
XED_IFORMFL_MOVSB_LAST
XED_IFORMFL_MOVSD_FIRST
XED_IFORMFL_MOVSD_LAST
XED_IFORMFL_MOVSD_XMM_FIRST
XED_IFORMFL_MOVSD_XMM_LAST
XED_IFORMFL_MOVSHDUP_FIRST
XED_IFORMFL_MOVSHDUP_LAST
XED_IFORMFL_MOVSLDUP_FIRST
XED_IFORMFL_MOVSLDUP_LAST
XED_IFORMFL_MOVSQ_FIRST
XED_IFORMFL_MOVSQ_LAST
XED_IFORMFL_MOVSS_FIRST
XED_IFORMFL_MOVSS_LAST
XED_IFORMFL_MOVSW_FIRST
XED_IFORMFL_MOVSW_LAST
XED_IFORMFL_MOVSXD_FIRST
XED_IFORMFL_MOVSXD_LAST
XED_IFORMFL_MOVSX_FIRST
XED_IFORMFL_MOVSX_LAST
XED_IFORMFL_MOVUPD_FIRST
XED_IFORMFL_MOVUPD_LAST
XED_IFORMFL_MOVUPS_FIRST
XED_IFORMFL_MOVUPS_LAST
XED_IFORMFL_MOVZX_FIRST
XED_IFORMFL_MOVZX_LAST
XED_IFORMFL_MOV_CR_FIRST
XED_IFORMFL_MOV_CR_LAST
XED_IFORMFL_MOV_DR_FIRST
XED_IFORMFL_MOV_DR_LAST
XED_IFORMFL_MOV_FIRST
XED_IFORMFL_MOV_LAST
XED_IFORMFL_MPSADBW_FIRST
XED_IFORMFL_MPSADBW_LAST
XED_IFORMFL_MULPD_FIRST
XED_IFORMFL_MULPD_LAST
XED_IFORMFL_MULPS_FIRST
XED_IFORMFL_MULPS_LAST
XED_IFORMFL_MULSD_FIRST
XED_IFORMFL_MULSD_LAST
XED_IFORMFL_MULSS_FIRST
XED_IFORMFL_MULSS_LAST
XED_IFORMFL_MULX_FIRST
XED_IFORMFL_MULX_LAST
XED_IFORMFL_MUL_FIRST
XED_IFORMFL_MUL_LAST
XED_IFORMFL_MWAITX_FIRST
XED_IFORMFL_MWAITX_LAST
XED_IFORMFL_MWAIT_FIRST
XED_IFORMFL_MWAIT_LAST
XED_IFORMFL_NEG_FIRST
XED_IFORMFL_NEG_LAST
XED_IFORMFL_NEG_LOCK_FIRST
XED_IFORMFL_NEG_LOCK_LAST
XED_IFORMFL_NOP_FIRST
XED_IFORMFL_NOP_LAST
XED_IFORMFL_NOT_FIRST
XED_IFORMFL_NOT_LAST
XED_IFORMFL_NOT_LOCK_FIRST
XED_IFORMFL_NOT_LOCK_LAST
XED_IFORMFL_ORPD_FIRST
XED_IFORMFL_ORPD_LAST
XED_IFORMFL_ORPS_FIRST
XED_IFORMFL_ORPS_LAST
XED_IFORMFL_OR_FIRST
XED_IFORMFL_OR_LAST
XED_IFORMFL_OR_LOCK_FIRST
XED_IFORMFL_OR_LOCK_LAST
XED_IFORMFL_OUTSB_FIRST
XED_IFORMFL_OUTSB_LAST
XED_IFORMFL_OUTSD_FIRST
XED_IFORMFL_OUTSD_LAST
XED_IFORMFL_OUTSW_FIRST
XED_IFORMFL_OUTSW_LAST
XED_IFORMFL_OUT_FIRST
XED_IFORMFL_OUT_LAST
XED_IFORMFL_PABSB_FIRST
XED_IFORMFL_PABSB_LAST
XED_IFORMFL_PABSD_FIRST
XED_IFORMFL_PABSD_LAST
XED_IFORMFL_PABSW_FIRST
XED_IFORMFL_PABSW_LAST
XED_IFORMFL_PACKSSDW_FIRST
XED_IFORMFL_PACKSSDW_LAST
XED_IFORMFL_PACKSSWB_FIRST
XED_IFORMFL_PACKSSWB_LAST
XED_IFORMFL_PACKUSDW_FIRST
XED_IFORMFL_PACKUSDW_LAST
XED_IFORMFL_PACKUSWB_FIRST
XED_IFORMFL_PACKUSWB_LAST
XED_IFORMFL_PADDB_FIRST
XED_IFORMFL_PADDB_LAST
XED_IFORMFL_PADDD_FIRST
XED_IFORMFL_PADDD_LAST
XED_IFORMFL_PADDQ_FIRST
XED_IFORMFL_PADDQ_LAST
XED_IFORMFL_PADDSB_FIRST
XED_IFORMFL_PADDSB_LAST
XED_IFORMFL_PADDSW_FIRST
XED_IFORMFL_PADDSW_LAST
XED_IFORMFL_PADDUSB_FIRST
XED_IFORMFL_PADDUSB_LAST
XED_IFORMFL_PADDUSW_FIRST
XED_IFORMFL_PADDUSW_LAST
XED_IFORMFL_PADDW_FIRST
XED_IFORMFL_PADDW_LAST
XED_IFORMFL_PALIGNR_FIRST
XED_IFORMFL_PALIGNR_LAST
XED_IFORMFL_PANDN_FIRST
XED_IFORMFL_PANDN_LAST
XED_IFORMFL_PAND_FIRST
XED_IFORMFL_PAND_LAST
XED_IFORMFL_PAUSE_FIRST
XED_IFORMFL_PAUSE_LAST
XED_IFORMFL_PAVGB_FIRST
XED_IFORMFL_PAVGB_LAST
XED_IFORMFL_PAVGUSB_FIRST
XED_IFORMFL_PAVGUSB_LAST
XED_IFORMFL_PAVGW_FIRST
XED_IFORMFL_PAVGW_LAST
XED_IFORMFL_PBLENDVB_FIRST
XED_IFORMFL_PBLENDVB_LAST
XED_IFORMFL_PBLENDW_FIRST
XED_IFORMFL_PBLENDW_LAST
XED_IFORMFL_PBNDKB_FIRST
XED_IFORMFL_PBNDKB_LAST
XED_IFORMFL_PCLMULQDQ_FIRST
XED_IFORMFL_PCLMULQDQ_LAST
XED_IFORMFL_PCMPEQB_FIRST
XED_IFORMFL_PCMPEQB_LAST
XED_IFORMFL_PCMPEQD_FIRST
XED_IFORMFL_PCMPEQD_LAST
XED_IFORMFL_PCMPEQQ_FIRST
XED_IFORMFL_PCMPEQQ_LAST
XED_IFORMFL_PCMPEQW_FIRST
XED_IFORMFL_PCMPEQW_LAST
XED_IFORMFL_PCMPESTRI64_FIRST
XED_IFORMFL_PCMPESTRI64_LAST
XED_IFORMFL_PCMPESTRI_FIRST
XED_IFORMFL_PCMPESTRI_LAST
XED_IFORMFL_PCMPESTRM64_FIRST
XED_IFORMFL_PCMPESTRM64_LAST
XED_IFORMFL_PCMPESTRM_FIRST
XED_IFORMFL_PCMPESTRM_LAST
XED_IFORMFL_PCMPGTB_FIRST
XED_IFORMFL_PCMPGTB_LAST
XED_IFORMFL_PCMPGTD_FIRST
XED_IFORMFL_PCMPGTD_LAST
XED_IFORMFL_PCMPGTQ_FIRST
XED_IFORMFL_PCMPGTQ_LAST
XED_IFORMFL_PCMPGTW_FIRST
XED_IFORMFL_PCMPGTW_LAST
XED_IFORMFL_PCMPISTRI64_FIRST
XED_IFORMFL_PCMPISTRI64_LAST
XED_IFORMFL_PCMPISTRI_FIRST
XED_IFORMFL_PCMPISTRI_LAST
XED_IFORMFL_PCMPISTRM_FIRST
XED_IFORMFL_PCMPISTRM_LAST
XED_IFORMFL_PCONFIG_FIRST
XED_IFORMFL_PCONFIG_LAST
XED_IFORMFL_PDEP_FIRST
XED_IFORMFL_PDEP_LAST
XED_IFORMFL_PEXTRB_FIRST
XED_IFORMFL_PEXTRB_LAST
XED_IFORMFL_PEXTRD_FIRST
XED_IFORMFL_PEXTRD_LAST
XED_IFORMFL_PEXTRQ_FIRST
XED_IFORMFL_PEXTRQ_LAST
XED_IFORMFL_PEXTRW_FIRST
XED_IFORMFL_PEXTRW_LAST
XED_IFORMFL_PEXTRW_SSE4_FIRST
XED_IFORMFL_PEXTRW_SSE4_LAST
XED_IFORMFL_PEXT_FIRST
XED_IFORMFL_PEXT_LAST
XED_IFORMFL_PF2ID_FIRST
XED_IFORMFL_PF2ID_LAST
XED_IFORMFL_PF2IW_FIRST
XED_IFORMFL_PF2IW_LAST
XED_IFORMFL_PFACC_FIRST
XED_IFORMFL_PFACC_LAST
XED_IFORMFL_PFADD_FIRST
XED_IFORMFL_PFADD_LAST
XED_IFORMFL_PFCMPEQ_FIRST
XED_IFORMFL_PFCMPEQ_LAST
XED_IFORMFL_PFCMPGE_FIRST
XED_IFORMFL_PFCMPGE_LAST
XED_IFORMFL_PFCMPGT_FIRST
XED_IFORMFL_PFCMPGT_LAST
XED_IFORMFL_PFMAX_FIRST
XED_IFORMFL_PFMAX_LAST
XED_IFORMFL_PFMIN_FIRST
XED_IFORMFL_PFMIN_LAST
XED_IFORMFL_PFMUL_FIRST
XED_IFORMFL_PFMUL_LAST
XED_IFORMFL_PFNACC_FIRST
XED_IFORMFL_PFNACC_LAST
XED_IFORMFL_PFPNACC_FIRST
XED_IFORMFL_PFPNACC_LAST
XED_IFORMFL_PFRCPIT1_FIRST
XED_IFORMFL_PFRCPIT1_LAST
XED_IFORMFL_PFRCPIT2_FIRST
XED_IFORMFL_PFRCPIT2_LAST
XED_IFORMFL_PFRCP_FIRST
XED_IFORMFL_PFRCP_LAST
XED_IFORMFL_PFRSQIT1_FIRST
XED_IFORMFL_PFRSQIT1_LAST
XED_IFORMFL_PFRSQRT_FIRST
XED_IFORMFL_PFRSQRT_LAST
XED_IFORMFL_PFSUBR_FIRST
XED_IFORMFL_PFSUBR_LAST
XED_IFORMFL_PFSUB_FIRST
XED_IFORMFL_PFSUB_LAST
XED_IFORMFL_PHADDD_FIRST
XED_IFORMFL_PHADDD_LAST
XED_IFORMFL_PHADDSW_FIRST
XED_IFORMFL_PHADDSW_LAST
XED_IFORMFL_PHADDW_FIRST
XED_IFORMFL_PHADDW_LAST
XED_IFORMFL_PHMINPOSUW_FIRST
XED_IFORMFL_PHMINPOSUW_LAST
XED_IFORMFL_PHSUBD_FIRST
XED_IFORMFL_PHSUBD_LAST
XED_IFORMFL_PHSUBSW_FIRST
XED_IFORMFL_PHSUBSW_LAST
XED_IFORMFL_PHSUBW_FIRST
XED_IFORMFL_PHSUBW_LAST
XED_IFORMFL_PI2FD_FIRST
XED_IFORMFL_PI2FD_LAST
XED_IFORMFL_PI2FW_FIRST
XED_IFORMFL_PI2FW_LAST
XED_IFORMFL_PINSRB_FIRST
XED_IFORMFL_PINSRB_LAST
XED_IFORMFL_PINSRD_FIRST
XED_IFORMFL_PINSRD_LAST
XED_IFORMFL_PINSRQ_FIRST
XED_IFORMFL_PINSRQ_LAST
XED_IFORMFL_PINSRW_FIRST
XED_IFORMFL_PINSRW_LAST
XED_IFORMFL_PMADDUBSW_FIRST
XED_IFORMFL_PMADDUBSW_LAST
XED_IFORMFL_PMADDWD_FIRST
XED_IFORMFL_PMADDWD_LAST
XED_IFORMFL_PMAXSB_FIRST
XED_IFORMFL_PMAXSB_LAST
XED_IFORMFL_PMAXSD_FIRST
XED_IFORMFL_PMAXSD_LAST
XED_IFORMFL_PMAXSW_FIRST
XED_IFORMFL_PMAXSW_LAST
XED_IFORMFL_PMAXUB_FIRST
XED_IFORMFL_PMAXUB_LAST
XED_IFORMFL_PMAXUD_FIRST
XED_IFORMFL_PMAXUD_LAST
XED_IFORMFL_PMAXUW_FIRST
XED_IFORMFL_PMAXUW_LAST
XED_IFORMFL_PMINSB_FIRST
XED_IFORMFL_PMINSB_LAST
XED_IFORMFL_PMINSD_FIRST
XED_IFORMFL_PMINSD_LAST
XED_IFORMFL_PMINSW_FIRST
XED_IFORMFL_PMINSW_LAST
XED_IFORMFL_PMINUB_FIRST
XED_IFORMFL_PMINUB_LAST
XED_IFORMFL_PMINUD_FIRST
XED_IFORMFL_PMINUD_LAST
XED_IFORMFL_PMINUW_FIRST
XED_IFORMFL_PMINUW_LAST
XED_IFORMFL_PMOVMSKB_FIRST
XED_IFORMFL_PMOVMSKB_LAST
XED_IFORMFL_PMOVSXBD_FIRST
XED_IFORMFL_PMOVSXBD_LAST
XED_IFORMFL_PMOVSXBQ_FIRST
XED_IFORMFL_PMOVSXBQ_LAST
XED_IFORMFL_PMOVSXBW_FIRST
XED_IFORMFL_PMOVSXBW_LAST
XED_IFORMFL_PMOVSXDQ_FIRST
XED_IFORMFL_PMOVSXDQ_LAST
XED_IFORMFL_PMOVSXWD_FIRST
XED_IFORMFL_PMOVSXWD_LAST
XED_IFORMFL_PMOVSXWQ_FIRST
XED_IFORMFL_PMOVSXWQ_LAST
XED_IFORMFL_PMOVZXBD_FIRST
XED_IFORMFL_PMOVZXBD_LAST
XED_IFORMFL_PMOVZXBQ_FIRST
XED_IFORMFL_PMOVZXBQ_LAST
XED_IFORMFL_PMOVZXBW_FIRST
XED_IFORMFL_PMOVZXBW_LAST
XED_IFORMFL_PMOVZXDQ_FIRST
XED_IFORMFL_PMOVZXDQ_LAST
XED_IFORMFL_PMOVZXWD_FIRST
XED_IFORMFL_PMOVZXWD_LAST
XED_IFORMFL_PMOVZXWQ_FIRST
XED_IFORMFL_PMOVZXWQ_LAST
XED_IFORMFL_PMULDQ_FIRST
XED_IFORMFL_PMULDQ_LAST
XED_IFORMFL_PMULHRSW_FIRST
XED_IFORMFL_PMULHRSW_LAST
XED_IFORMFL_PMULHRW_FIRST
XED_IFORMFL_PMULHRW_LAST
XED_IFORMFL_PMULHUW_FIRST
XED_IFORMFL_PMULHUW_LAST
XED_IFORMFL_PMULHW_FIRST
XED_IFORMFL_PMULHW_LAST
XED_IFORMFL_PMULLD_FIRST
XED_IFORMFL_PMULLD_LAST
XED_IFORMFL_PMULLW_FIRST
XED_IFORMFL_PMULLW_LAST
XED_IFORMFL_PMULUDQ_FIRST
XED_IFORMFL_PMULUDQ_LAST
XED_IFORMFL_POP2P_FIRST
XED_IFORMFL_POP2P_LAST
XED_IFORMFL_POP2_FIRST
XED_IFORMFL_POP2_LAST
XED_IFORMFL_POPAD_FIRST
XED_IFORMFL_POPAD_LAST
XED_IFORMFL_POPA_FIRST
XED_IFORMFL_POPA_LAST
XED_IFORMFL_POPCNT_FIRST
XED_IFORMFL_POPCNT_LAST
XED_IFORMFL_POPFD_FIRST
XED_IFORMFL_POPFD_LAST
XED_IFORMFL_POPFQ_FIRST
XED_IFORMFL_POPFQ_LAST
XED_IFORMFL_POPF_FIRST
XED_IFORMFL_POPF_LAST
XED_IFORMFL_POPP_FIRST
XED_IFORMFL_POPP_LAST
XED_IFORMFL_POP_FIRST
XED_IFORMFL_POP_LAST
XED_IFORMFL_POR_FIRST
XED_IFORMFL_POR_LAST
XED_IFORMFL_PREFETCHIT0_FIRST
XED_IFORMFL_PREFETCHIT0_LAST
XED_IFORMFL_PREFETCHIT1_FIRST
XED_IFORMFL_PREFETCHIT1_LAST
XED_IFORMFL_PREFETCHNTA_FIRST
XED_IFORMFL_PREFETCHNTA_LAST
XED_IFORMFL_PREFETCHT0_FIRST
XED_IFORMFL_PREFETCHT0_LAST
XED_IFORMFL_PREFETCHT1_FIRST
XED_IFORMFL_PREFETCHT1_LAST
XED_IFORMFL_PREFETCHT2_FIRST
XED_IFORMFL_PREFETCHT2_LAST
XED_IFORMFL_PREFETCHWT1_FIRST
XED_IFORMFL_PREFETCHWT1_LAST
XED_IFORMFL_PREFETCHW_FIRST
XED_IFORMFL_PREFETCHW_LAST
XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST
XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST
XED_IFORMFL_PREFETCH_RESERVED_FIRST
XED_IFORMFL_PREFETCH_RESERVED_LAST
XED_IFORMFL_PSADBW_FIRST
XED_IFORMFL_PSADBW_LAST
XED_IFORMFL_PSHUFB_FIRST
XED_IFORMFL_PSHUFB_LAST
XED_IFORMFL_PSHUFD_FIRST
XED_IFORMFL_PSHUFD_LAST
XED_IFORMFL_PSHUFHW_FIRST
XED_IFORMFL_PSHUFHW_LAST
XED_IFORMFL_PSHUFLW_FIRST
XED_IFORMFL_PSHUFLW_LAST
XED_IFORMFL_PSHUFW_FIRST
XED_IFORMFL_PSHUFW_LAST
XED_IFORMFL_PSIGNB_FIRST
XED_IFORMFL_PSIGNB_LAST
XED_IFORMFL_PSIGND_FIRST
XED_IFORMFL_PSIGND_LAST
XED_IFORMFL_PSIGNW_FIRST
XED_IFORMFL_PSIGNW_LAST
XED_IFORMFL_PSLLDQ_FIRST
XED_IFORMFL_PSLLDQ_LAST
XED_IFORMFL_PSLLD_FIRST
XED_IFORMFL_PSLLD_LAST
XED_IFORMFL_PSLLQ_FIRST
XED_IFORMFL_PSLLQ_LAST
XED_IFORMFL_PSLLW_FIRST
XED_IFORMFL_PSLLW_LAST
XED_IFORMFL_PSMASH_FIRST
XED_IFORMFL_PSMASH_LAST
XED_IFORMFL_PSRAD_FIRST
XED_IFORMFL_PSRAD_LAST
XED_IFORMFL_PSRAW_FIRST
XED_IFORMFL_PSRAW_LAST
XED_IFORMFL_PSRLDQ_FIRST
XED_IFORMFL_PSRLDQ_LAST
XED_IFORMFL_PSRLD_FIRST
XED_IFORMFL_PSRLD_LAST
XED_IFORMFL_PSRLQ_FIRST
XED_IFORMFL_PSRLQ_LAST
XED_IFORMFL_PSRLW_FIRST
XED_IFORMFL_PSRLW_LAST
XED_IFORMFL_PSUBB_FIRST
XED_IFORMFL_PSUBB_LAST
XED_IFORMFL_PSUBD_FIRST
XED_IFORMFL_PSUBD_LAST
XED_IFORMFL_PSUBQ_FIRST
XED_IFORMFL_PSUBQ_LAST
XED_IFORMFL_PSUBSB_FIRST
XED_IFORMFL_PSUBSB_LAST
XED_IFORMFL_PSUBSW_FIRST
XED_IFORMFL_PSUBSW_LAST
XED_IFORMFL_PSUBUSB_FIRST
XED_IFORMFL_PSUBUSB_LAST
XED_IFORMFL_PSUBUSW_FIRST
XED_IFORMFL_PSUBUSW_LAST
XED_IFORMFL_PSUBW_FIRST
XED_IFORMFL_PSUBW_LAST
XED_IFORMFL_PSWAPD_FIRST
XED_IFORMFL_PSWAPD_LAST
XED_IFORMFL_PTEST_FIRST
XED_IFORMFL_PTEST_LAST
XED_IFORMFL_PTWRITE_FIRST
XED_IFORMFL_PTWRITE_LAST
XED_IFORMFL_PUNPCKHBW_FIRST
XED_IFORMFL_PUNPCKHBW_LAST
XED_IFORMFL_PUNPCKHDQ_FIRST
XED_IFORMFL_PUNPCKHDQ_LAST
XED_IFORMFL_PUNPCKHQDQ_FIRST
XED_IFORMFL_PUNPCKHQDQ_LAST
XED_IFORMFL_PUNPCKHWD_FIRST
XED_IFORMFL_PUNPCKHWD_LAST
XED_IFORMFL_PUNPCKLBW_FIRST
XED_IFORMFL_PUNPCKLBW_LAST
XED_IFORMFL_PUNPCKLDQ_FIRST
XED_IFORMFL_PUNPCKLDQ_LAST
XED_IFORMFL_PUNPCKLQDQ_FIRST
XED_IFORMFL_PUNPCKLQDQ_LAST
XED_IFORMFL_PUNPCKLWD_FIRST
XED_IFORMFL_PUNPCKLWD_LAST
XED_IFORMFL_PUSH2P_FIRST
XED_IFORMFL_PUSH2P_LAST
XED_IFORMFL_PUSH2_FIRST
XED_IFORMFL_PUSH2_LAST
XED_IFORMFL_PUSHAD_FIRST
XED_IFORMFL_PUSHAD_LAST
XED_IFORMFL_PUSHA_FIRST
XED_IFORMFL_PUSHA_LAST
XED_IFORMFL_PUSHFD_FIRST
XED_IFORMFL_PUSHFD_LAST
XED_IFORMFL_PUSHFQ_FIRST
XED_IFORMFL_PUSHFQ_LAST
XED_IFORMFL_PUSHF_FIRST
XED_IFORMFL_PUSHF_LAST
XED_IFORMFL_PUSHP_FIRST
XED_IFORMFL_PUSHP_LAST
XED_IFORMFL_PUSH_FIRST
XED_IFORMFL_PUSH_LAST
XED_IFORMFL_PVALIDATE_FIRST
XED_IFORMFL_PVALIDATE_LAST
XED_IFORMFL_PXOR_FIRST
XED_IFORMFL_PXOR_LAST
XED_IFORMFL_RCL_FIRST
XED_IFORMFL_RCL_LAST
XED_IFORMFL_RCPPS_FIRST
XED_IFORMFL_RCPPS_LAST
XED_IFORMFL_RCPSS_FIRST
XED_IFORMFL_RCPSS_LAST
XED_IFORMFL_RCR_FIRST
XED_IFORMFL_RCR_LAST
XED_IFORMFL_RDFSBASE_FIRST
XED_IFORMFL_RDFSBASE_LAST
XED_IFORMFL_RDGSBASE_FIRST
XED_IFORMFL_RDGSBASE_LAST
XED_IFORMFL_RDMSRLIST_FIRST
XED_IFORMFL_RDMSRLIST_LAST
XED_IFORMFL_RDMSR_FIRST
XED_IFORMFL_RDMSR_LAST
XED_IFORMFL_RDPID_FIRST
XED_IFORMFL_RDPID_LAST
XED_IFORMFL_RDPKRU_FIRST
XED_IFORMFL_RDPKRU_LAST
XED_IFORMFL_RDPMC_FIRST
XED_IFORMFL_RDPMC_LAST
XED_IFORMFL_RDPRU_FIRST
XED_IFORMFL_RDPRU_LAST
XED_IFORMFL_RDRAND_FIRST
XED_IFORMFL_RDRAND_LAST
XED_IFORMFL_RDSEED_FIRST
XED_IFORMFL_RDSEED_LAST
XED_IFORMFL_RDSSPD_FIRST
XED_IFORMFL_RDSSPD_LAST
XED_IFORMFL_RDSSPQ_FIRST
XED_IFORMFL_RDSSPQ_LAST
XED_IFORMFL_RDTSCP_FIRST
XED_IFORMFL_RDTSCP_LAST
XED_IFORMFL_RDTSC_FIRST
XED_IFORMFL_RDTSC_LAST
XED_IFORMFL_REPE_CMPSB_FIRST
XED_IFORMFL_REPE_CMPSB_LAST
XED_IFORMFL_REPE_CMPSD_FIRST
XED_IFORMFL_REPE_CMPSD_LAST
XED_IFORMFL_REPE_CMPSQ_FIRST
XED_IFORMFL_REPE_CMPSQ_LAST
XED_IFORMFL_REPE_CMPSW_FIRST
XED_IFORMFL_REPE_CMPSW_LAST
XED_IFORMFL_REPE_SCASB_FIRST
XED_IFORMFL_REPE_SCASB_LAST
XED_IFORMFL_REPE_SCASD_FIRST
XED_IFORMFL_REPE_SCASD_LAST
XED_IFORMFL_REPE_SCASQ_FIRST
XED_IFORMFL_REPE_SCASQ_LAST
XED_IFORMFL_REPE_SCASW_FIRST
XED_IFORMFL_REPE_SCASW_LAST
XED_IFORMFL_REPNE_CMPSB_FIRST
XED_IFORMFL_REPNE_CMPSB_LAST
XED_IFORMFL_REPNE_CMPSD_FIRST
XED_IFORMFL_REPNE_CMPSD_LAST
XED_IFORMFL_REPNE_CMPSQ_FIRST
XED_IFORMFL_REPNE_CMPSQ_LAST
XED_IFORMFL_REPNE_CMPSW_FIRST
XED_IFORMFL_REPNE_CMPSW_LAST
XED_IFORMFL_REPNE_SCASB_FIRST
XED_IFORMFL_REPNE_SCASB_LAST
XED_IFORMFL_REPNE_SCASD_FIRST
XED_IFORMFL_REPNE_SCASD_LAST
XED_IFORMFL_REPNE_SCASQ_FIRST
XED_IFORMFL_REPNE_SCASQ_LAST
XED_IFORMFL_REPNE_SCASW_FIRST
XED_IFORMFL_REPNE_SCASW_LAST
XED_IFORMFL_REP_INSB_FIRST
XED_IFORMFL_REP_INSB_LAST
XED_IFORMFL_REP_INSD_FIRST
XED_IFORMFL_REP_INSD_LAST
XED_IFORMFL_REP_INSW_FIRST
XED_IFORMFL_REP_INSW_LAST
XED_IFORMFL_REP_LODSB_FIRST
XED_IFORMFL_REP_LODSB_LAST
XED_IFORMFL_REP_LODSD_FIRST
XED_IFORMFL_REP_LODSD_LAST
XED_IFORMFL_REP_LODSQ_FIRST
XED_IFORMFL_REP_LODSQ_LAST
XED_IFORMFL_REP_LODSW_FIRST
XED_IFORMFL_REP_LODSW_LAST
XED_IFORMFL_REP_MONTMUL_FIRST
XED_IFORMFL_REP_MONTMUL_LAST
XED_IFORMFL_REP_MOVSB_FIRST
XED_IFORMFL_REP_MOVSB_LAST
XED_IFORMFL_REP_MOVSD_FIRST
XED_IFORMFL_REP_MOVSD_LAST
XED_IFORMFL_REP_MOVSQ_FIRST
XED_IFORMFL_REP_MOVSQ_LAST
XED_IFORMFL_REP_MOVSW_FIRST
XED_IFORMFL_REP_MOVSW_LAST
XED_IFORMFL_REP_OUTSB_FIRST
XED_IFORMFL_REP_OUTSB_LAST
XED_IFORMFL_REP_OUTSD_FIRST
XED_IFORMFL_REP_OUTSD_LAST
XED_IFORMFL_REP_OUTSW_FIRST
XED_IFORMFL_REP_OUTSW_LAST
XED_IFORMFL_REP_STOSB_FIRST
XED_IFORMFL_REP_STOSB_LAST
XED_IFORMFL_REP_STOSD_FIRST
XED_IFORMFL_REP_STOSD_LAST
XED_IFORMFL_REP_STOSQ_FIRST
XED_IFORMFL_REP_STOSQ_LAST
XED_IFORMFL_REP_STOSW_FIRST
XED_IFORMFL_REP_STOSW_LAST
XED_IFORMFL_REP_XCRYPTCBC_FIRST
XED_IFORMFL_REP_XCRYPTCBC_LAST
XED_IFORMFL_REP_XCRYPTCFB_FIRST
XED_IFORMFL_REP_XCRYPTCFB_LAST
XED_IFORMFL_REP_XCRYPTCTR_FIRST
XED_IFORMFL_REP_XCRYPTCTR_LAST
XED_IFORMFL_REP_XCRYPTECB_FIRST
XED_IFORMFL_REP_XCRYPTECB_LAST
XED_IFORMFL_REP_XCRYPTOFB_FIRST
XED_IFORMFL_REP_XCRYPTOFB_LAST
XED_IFORMFL_REP_XSHA1_FIRST
XED_IFORMFL_REP_XSHA1_LAST
XED_IFORMFL_REP_XSHA256_FIRST
XED_IFORMFL_REP_XSHA256_LAST
XED_IFORMFL_REP_XSTORE_FIRST
XED_IFORMFL_REP_XSTORE_LAST
XED_IFORMFL_RET_FAR_FIRST
XED_IFORMFL_RET_FAR_LAST
XED_IFORMFL_RET_NEAR_FIRST
XED_IFORMFL_RET_NEAR_LAST
XED_IFORMFL_RMPADJUST_FIRST
XED_IFORMFL_RMPADJUST_LAST
XED_IFORMFL_RMPUPDATE_FIRST
XED_IFORMFL_RMPUPDATE_LAST
XED_IFORMFL_ROL_FIRST
XED_IFORMFL_ROL_LAST
XED_IFORMFL_RORX_FIRST
XED_IFORMFL_RORX_LAST
XED_IFORMFL_ROR_FIRST
XED_IFORMFL_ROR_LAST
XED_IFORMFL_ROUNDPD_FIRST
XED_IFORMFL_ROUNDPD_LAST
XED_IFORMFL_ROUNDPS_FIRST
XED_IFORMFL_ROUNDPS_LAST
XED_IFORMFL_ROUNDSD_FIRST
XED_IFORMFL_ROUNDSD_LAST
XED_IFORMFL_ROUNDSS_FIRST
XED_IFORMFL_ROUNDSS_LAST
XED_IFORMFL_RSM_FIRST
XED_IFORMFL_RSM_LAST
XED_IFORMFL_RSQRTPS_FIRST
XED_IFORMFL_RSQRTPS_LAST
XED_IFORMFL_RSQRTSS_FIRST
XED_IFORMFL_RSQRTSS_LAST
XED_IFORMFL_RSTORSSP_FIRST
XED_IFORMFL_RSTORSSP_LAST
XED_IFORMFL_SAHF_FIRST
XED_IFORMFL_SAHF_LAST
XED_IFORMFL_SALC_FIRST
XED_IFORMFL_SALC_LAST
XED_IFORMFL_SARX_FIRST
XED_IFORMFL_SARX_LAST
XED_IFORMFL_SAR_FIRST
XED_IFORMFL_SAR_LAST
XED_IFORMFL_SAVEPREVSSP_FIRST
XED_IFORMFL_SAVEPREVSSP_LAST
XED_IFORMFL_SBB_FIRST
XED_IFORMFL_SBB_LAST
XED_IFORMFL_SBB_LOCK_FIRST
XED_IFORMFL_SBB_LOCK_LAST
XED_IFORMFL_SCASB_FIRST
XED_IFORMFL_SCASB_LAST
XED_IFORMFL_SCASD_FIRST
XED_IFORMFL_SCASD_LAST
XED_IFORMFL_SCASQ_FIRST
XED_IFORMFL_SCASQ_LAST
XED_IFORMFL_SCASW_FIRST
XED_IFORMFL_SCASW_LAST
XED_IFORMFL_SEAMCALL_FIRST
XED_IFORMFL_SEAMCALL_LAST
XED_IFORMFL_SEAMOPS_FIRST
XED_IFORMFL_SEAMOPS_LAST
XED_IFORMFL_SEAMRET_FIRST
XED_IFORMFL_SEAMRET_LAST
XED_IFORMFL_SENDUIPI_FIRST
XED_IFORMFL_SENDUIPI_LAST
XED_IFORMFL_SERIALIZE_FIRST
XED_IFORMFL_SERIALIZE_LAST
XED_IFORMFL_SETBE_FIRST
XED_IFORMFL_SETBE_LAST
XED_IFORMFL_SETB_FIRST
XED_IFORMFL_SETB_LAST
XED_IFORMFL_SETLE_FIRST
XED_IFORMFL_SETLE_LAST
XED_IFORMFL_SETL_FIRST
XED_IFORMFL_SETL_LAST
XED_IFORMFL_SETNBE_FIRST
XED_IFORMFL_SETNBE_LAST
XED_IFORMFL_SETNB_FIRST
XED_IFORMFL_SETNB_LAST
XED_IFORMFL_SETNLE_FIRST
XED_IFORMFL_SETNLE_LAST
XED_IFORMFL_SETNL_FIRST
XED_IFORMFL_SETNL_LAST
XED_IFORMFL_SETNO_FIRST
XED_IFORMFL_SETNO_LAST
XED_IFORMFL_SETNP_FIRST
XED_IFORMFL_SETNP_LAST
XED_IFORMFL_SETNS_FIRST
XED_IFORMFL_SETNS_LAST
XED_IFORMFL_SETNZ_FIRST
XED_IFORMFL_SETNZ_LAST
XED_IFORMFL_SETO_FIRST
XED_IFORMFL_SETO_LAST
XED_IFORMFL_SETP_FIRST
XED_IFORMFL_SETP_LAST
XED_IFORMFL_SETSSBSY_FIRST
XED_IFORMFL_SETSSBSY_LAST
XED_IFORMFL_SETS_FIRST
XED_IFORMFL_SETS_LAST
XED_IFORMFL_SETZ_FIRST
XED_IFORMFL_SETZ_LAST
XED_IFORMFL_SFENCE_FIRST
XED_IFORMFL_SFENCE_LAST
XED_IFORMFL_SGDT_FIRST
XED_IFORMFL_SGDT_LAST
XED_IFORMFL_SHA1MSG1_FIRST
XED_IFORMFL_SHA1MSG1_LAST
XED_IFORMFL_SHA1MSG2_FIRST
XED_IFORMFL_SHA1MSG2_LAST
XED_IFORMFL_SHA1NEXTE_FIRST
XED_IFORMFL_SHA1NEXTE_LAST
XED_IFORMFL_SHA1RNDS4_FIRST
XED_IFORMFL_SHA1RNDS4_LAST
XED_IFORMFL_SHA256MSG1_FIRST
XED_IFORMFL_SHA256MSG1_LAST
XED_IFORMFL_SHA256MSG2_FIRST
XED_IFORMFL_SHA256MSG2_LAST
XED_IFORMFL_SHA256RNDS2_FIRST
XED_IFORMFL_SHA256RNDS2_LAST
XED_IFORMFL_SHLD_FIRST
XED_IFORMFL_SHLD_LAST
XED_IFORMFL_SHLX_FIRST
XED_IFORMFL_SHLX_LAST
XED_IFORMFL_SHL_FIRST
XED_IFORMFL_SHL_LAST
XED_IFORMFL_SHRD_FIRST
XED_IFORMFL_SHRD_LAST
XED_IFORMFL_SHRX_FIRST
XED_IFORMFL_SHRX_LAST
XED_IFORMFL_SHR_FIRST
XED_IFORMFL_SHR_LAST
XED_IFORMFL_SHUFPD_FIRST
XED_IFORMFL_SHUFPD_LAST
XED_IFORMFL_SHUFPS_FIRST
XED_IFORMFL_SHUFPS_LAST
XED_IFORMFL_SIDT_FIRST
XED_IFORMFL_SIDT_LAST
XED_IFORMFL_SKINIT_FIRST
XED_IFORMFL_SKINIT_LAST
XED_IFORMFL_SLDT_FIRST
XED_IFORMFL_SLDT_LAST
XED_IFORMFL_SLWPCB_FIRST
XED_IFORMFL_SLWPCB_LAST
XED_IFORMFL_SMSW_FIRST
XED_IFORMFL_SMSW_LAST
XED_IFORMFL_SQRTPD_FIRST
XED_IFORMFL_SQRTPD_LAST
XED_IFORMFL_SQRTPS_FIRST
XED_IFORMFL_SQRTPS_LAST
XED_IFORMFL_SQRTSD_FIRST
XED_IFORMFL_SQRTSD_LAST
XED_IFORMFL_SQRTSS_FIRST
XED_IFORMFL_SQRTSS_LAST
XED_IFORMFL_STAC_FIRST
XED_IFORMFL_STAC_LAST
XED_IFORMFL_STC_FIRST
XED_IFORMFL_STC_LAST
XED_IFORMFL_STD_FIRST
XED_IFORMFL_STD_LAST
XED_IFORMFL_STGI_FIRST
XED_IFORMFL_STGI_LAST
XED_IFORMFL_STI_FIRST
XED_IFORMFL_STI_LAST
XED_IFORMFL_STMXCSR_FIRST
XED_IFORMFL_STMXCSR_LAST
XED_IFORMFL_STOSB_FIRST
XED_IFORMFL_STOSB_LAST
XED_IFORMFL_STOSD_FIRST
XED_IFORMFL_STOSD_LAST
XED_IFORMFL_STOSQ_FIRST
XED_IFORMFL_STOSQ_LAST
XED_IFORMFL_STOSW_FIRST
XED_IFORMFL_STOSW_LAST
XED_IFORMFL_STR_FIRST
XED_IFORMFL_STR_LAST
XED_IFORMFL_STTILECFG_FIRST
XED_IFORMFL_STTILECFG_LAST
XED_IFORMFL_STUI_FIRST
XED_IFORMFL_STUI_LAST
XED_IFORMFL_SUBPD_FIRST
XED_IFORMFL_SUBPD_LAST
XED_IFORMFL_SUBPS_FIRST
XED_IFORMFL_SUBPS_LAST
XED_IFORMFL_SUBSD_FIRST
XED_IFORMFL_SUBSD_LAST
XED_IFORMFL_SUBSS_FIRST
XED_IFORMFL_SUBSS_LAST
XED_IFORMFL_SUB_FIRST
XED_IFORMFL_SUB_LAST
XED_IFORMFL_SUB_LOCK_FIRST
XED_IFORMFL_SUB_LOCK_LAST
XED_IFORMFL_SWAPGS_FIRST
XED_IFORMFL_SWAPGS_LAST
XED_IFORMFL_SYSCALL_32_FIRST
XED_IFORMFL_SYSCALL_32_LAST
XED_IFORMFL_SYSCALL_FIRST
XED_IFORMFL_SYSCALL_LAST
XED_IFORMFL_SYSENTER_FIRST
XED_IFORMFL_SYSENTER_LAST
XED_IFORMFL_SYSEXIT_FIRST
XED_IFORMFL_SYSEXIT_LAST
XED_IFORMFL_SYSRET64_FIRST
XED_IFORMFL_SYSRET64_LAST
XED_IFORMFL_SYSRET_AMD_FIRST
XED_IFORMFL_SYSRET_AMD_LAST
XED_IFORMFL_SYSRET_FIRST
XED_IFORMFL_SYSRET_LAST
XED_IFORMFL_T1MSKC_FIRST
XED_IFORMFL_T1MSKC_LAST
XED_IFORMFL_TCMMIMFP16PS_FIRST
XED_IFORMFL_TCMMIMFP16PS_LAST
XED_IFORMFL_TCMMRLFP16PS_FIRST
XED_IFORMFL_TCMMRLFP16PS_LAST
XED_IFORMFL_TDCALL_FIRST
XED_IFORMFL_TDCALL_LAST
XED_IFORMFL_TDPBF16PS_FIRST
XED_IFORMFL_TDPBF16PS_LAST
XED_IFORMFL_TDPBSSD_FIRST
XED_IFORMFL_TDPBSSD_LAST
XED_IFORMFL_TDPBSUD_FIRST
XED_IFORMFL_TDPBSUD_LAST
XED_IFORMFL_TDPBUSD_FIRST
XED_IFORMFL_TDPBUSD_LAST
XED_IFORMFL_TDPBUUD_FIRST
XED_IFORMFL_TDPBUUD_LAST
XED_IFORMFL_TDPFP16PS_FIRST
XED_IFORMFL_TDPFP16PS_LAST
XED_IFORMFL_TESTUI_FIRST
XED_IFORMFL_TESTUI_LAST
XED_IFORMFL_TEST_FIRST
XED_IFORMFL_TEST_LAST
XED_IFORMFL_TILELOADDT1_FIRST
XED_IFORMFL_TILELOADDT1_LAST
XED_IFORMFL_TILELOADD_FIRST
XED_IFORMFL_TILELOADD_LAST
XED_IFORMFL_TILERELEASE_FIRST
XED_IFORMFL_TILERELEASE_LAST
XED_IFORMFL_TILESTORED_FIRST
XED_IFORMFL_TILESTORED_LAST
XED_IFORMFL_TILEZERO_FIRST
XED_IFORMFL_TILEZERO_LAST
XED_IFORMFL_TLBSYNC_FIRST
XED_IFORMFL_TLBSYNC_LAST
XED_IFORMFL_TPAUSE_FIRST
XED_IFORMFL_TPAUSE_LAST
XED_IFORMFL_TZCNT_FIRST
XED_IFORMFL_TZCNT_LAST
XED_IFORMFL_TZMSK_FIRST
XED_IFORMFL_TZMSK_LAST
XED_IFORMFL_UCOMISD_FIRST
XED_IFORMFL_UCOMISD_LAST
XED_IFORMFL_UCOMISS_FIRST
XED_IFORMFL_UCOMISS_LAST
XED_IFORMFL_UD0_FIRST
XED_IFORMFL_UD0_LAST
XED_IFORMFL_UD1_FIRST
XED_IFORMFL_UD1_LAST
XED_IFORMFL_UD2_FIRST
XED_IFORMFL_UD2_LAST
XED_IFORMFL_UIRET_FIRST
XED_IFORMFL_UIRET_LAST
XED_IFORMFL_UMONITOR_FIRST
XED_IFORMFL_UMONITOR_LAST
XED_IFORMFL_UMWAIT_FIRST
XED_IFORMFL_UMWAIT_LAST
XED_IFORMFL_UNPCKHPD_FIRST
XED_IFORMFL_UNPCKHPD_LAST
XED_IFORMFL_UNPCKHPS_FIRST
XED_IFORMFL_UNPCKHPS_LAST
XED_IFORMFL_UNPCKLPD_FIRST
XED_IFORMFL_UNPCKLPD_LAST
XED_IFORMFL_UNPCKLPS_FIRST
XED_IFORMFL_UNPCKLPS_LAST
XED_IFORMFL_URDMSR_FIRST
XED_IFORMFL_URDMSR_LAST
XED_IFORMFL_UWRMSR_FIRST
XED_IFORMFL_UWRMSR_LAST
XED_IFORMFL_V4FMADDPS_FIRST
XED_IFORMFL_V4FMADDPS_LAST
XED_IFORMFL_V4FMADDSS_FIRST
XED_IFORMFL_V4FMADDSS_LAST
XED_IFORMFL_V4FNMADDPS_FIRST
XED_IFORMFL_V4FNMADDPS_LAST
XED_IFORMFL_V4FNMADDSS_FIRST
XED_IFORMFL_V4FNMADDSS_LAST
XED_IFORMFL_VADDPD_FIRST
XED_IFORMFL_VADDPD_LAST
XED_IFORMFL_VADDPH_FIRST
XED_IFORMFL_VADDPH_LAST
XED_IFORMFL_VADDPS_FIRST
XED_IFORMFL_VADDPS_LAST
XED_IFORMFL_VADDSD_FIRST
XED_IFORMFL_VADDSD_LAST
XED_IFORMFL_VADDSH_FIRST
XED_IFORMFL_VADDSH_LAST
XED_IFORMFL_VADDSS_FIRST
XED_IFORMFL_VADDSS_LAST
XED_IFORMFL_VADDSUBPD_FIRST
XED_IFORMFL_VADDSUBPD_LAST
XED_IFORMFL_VADDSUBPS_FIRST
XED_IFORMFL_VADDSUBPS_LAST
XED_IFORMFL_VAESDECLAST_FIRST
XED_IFORMFL_VAESDECLAST_LAST
XED_IFORMFL_VAESDEC_FIRST
XED_IFORMFL_VAESDEC_LAST
XED_IFORMFL_VAESENCLAST_FIRST
XED_IFORMFL_VAESENCLAST_LAST
XED_IFORMFL_VAESENC_FIRST
XED_IFORMFL_VAESENC_LAST
XED_IFORMFL_VAESIMC_FIRST
XED_IFORMFL_VAESIMC_LAST
XED_IFORMFL_VAESKEYGENASSIST_FIRST
XED_IFORMFL_VAESKEYGENASSIST_LAST
XED_IFORMFL_VALIGND_FIRST
XED_IFORMFL_VALIGND_LAST
XED_IFORMFL_VALIGNQ_FIRST
XED_IFORMFL_VALIGNQ_LAST
XED_IFORMFL_VANDNPD_FIRST
XED_IFORMFL_VANDNPD_LAST
XED_IFORMFL_VANDNPS_FIRST
XED_IFORMFL_VANDNPS_LAST
XED_IFORMFL_VANDPD_FIRST
XED_IFORMFL_VANDPD_LAST
XED_IFORMFL_VANDPS_FIRST
XED_IFORMFL_VANDPS_LAST
XED_IFORMFL_VBCSTNEBF162PS_FIRST
XED_IFORMFL_VBCSTNEBF162PS_LAST
XED_IFORMFL_VBCSTNESH2PS_FIRST
XED_IFORMFL_VBCSTNESH2PS_LAST
XED_IFORMFL_VBLENDMPD_FIRST
XED_IFORMFL_VBLENDMPD_LAST
XED_IFORMFL_VBLENDMPS_FIRST
XED_IFORMFL_VBLENDMPS_LAST
XED_IFORMFL_VBLENDPD_FIRST
XED_IFORMFL_VBLENDPD_LAST
XED_IFORMFL_VBLENDPS_FIRST
XED_IFORMFL_VBLENDPS_LAST
XED_IFORMFL_VBLENDVPD_FIRST
XED_IFORMFL_VBLENDVPD_LAST
XED_IFORMFL_VBLENDVPS_FIRST
XED_IFORMFL_VBLENDVPS_LAST
XED_IFORMFL_VBROADCASTF32X2_FIRST
XED_IFORMFL_VBROADCASTF32X2_LAST
XED_IFORMFL_VBROADCASTF32X4_FIRST
XED_IFORMFL_VBROADCASTF32X4_LAST
XED_IFORMFL_VBROADCASTF32X8_FIRST
XED_IFORMFL_VBROADCASTF32X8_LAST
XED_IFORMFL_VBROADCASTF64X2_FIRST
XED_IFORMFL_VBROADCASTF64X2_LAST
XED_IFORMFL_VBROADCASTF64X4_FIRST
XED_IFORMFL_VBROADCASTF64X4_LAST
XED_IFORMFL_VBROADCASTF128_FIRST
XED_IFORMFL_VBROADCASTF128_LAST
XED_IFORMFL_VBROADCASTI32X2_FIRST
XED_IFORMFL_VBROADCASTI32X2_LAST
XED_IFORMFL_VBROADCASTI32X4_FIRST
XED_IFORMFL_VBROADCASTI32X4_LAST
XED_IFORMFL_VBROADCASTI32X8_FIRST
XED_IFORMFL_VBROADCASTI32X8_LAST
XED_IFORMFL_VBROADCASTI64X2_FIRST
XED_IFORMFL_VBROADCASTI64X2_LAST
XED_IFORMFL_VBROADCASTI64X4_FIRST
XED_IFORMFL_VBROADCASTI64X4_LAST
XED_IFORMFL_VBROADCASTI128_FIRST
XED_IFORMFL_VBROADCASTI128_LAST
XED_IFORMFL_VBROADCASTSD_FIRST
XED_IFORMFL_VBROADCASTSD_LAST
XED_IFORMFL_VBROADCASTSS_FIRST
XED_IFORMFL_VBROADCASTSS_LAST
XED_IFORMFL_VCMPPD_FIRST
XED_IFORMFL_VCMPPD_LAST
XED_IFORMFL_VCMPPH_FIRST
XED_IFORMFL_VCMPPH_LAST
XED_IFORMFL_VCMPPS_FIRST
XED_IFORMFL_VCMPPS_LAST
XED_IFORMFL_VCMPSD_FIRST
XED_IFORMFL_VCMPSD_LAST
XED_IFORMFL_VCMPSH_FIRST
XED_IFORMFL_VCMPSH_LAST
XED_IFORMFL_VCMPSS_FIRST
XED_IFORMFL_VCMPSS_LAST
XED_IFORMFL_VCOMISD_FIRST
XED_IFORMFL_VCOMISD_LAST
XED_IFORMFL_VCOMISH_FIRST
XED_IFORMFL_VCOMISH_LAST
XED_IFORMFL_VCOMISS_FIRST
XED_IFORMFL_VCOMISS_LAST
XED_IFORMFL_VCOMPRESSPD_FIRST
XED_IFORMFL_VCOMPRESSPD_LAST
XED_IFORMFL_VCOMPRESSPS_FIRST
XED_IFORMFL_VCOMPRESSPS_LAST
XED_IFORMFL_VCVTDQ2PD_FIRST
XED_IFORMFL_VCVTDQ2PD_LAST
XED_IFORMFL_VCVTDQ2PH_FIRST
XED_IFORMFL_VCVTDQ2PH_LAST
XED_IFORMFL_VCVTDQ2PS_FIRST
XED_IFORMFL_VCVTDQ2PS_LAST
XED_IFORMFL_VCVTNE2PS2BF16_FIRST
XED_IFORMFL_VCVTNE2PS2BF16_LAST
XED_IFORMFL_VCVTNEEBF162PS_FIRST
XED_IFORMFL_VCVTNEEBF162PS_LAST
XED_IFORMFL_VCVTNEEPH2PS_FIRST
XED_IFORMFL_VCVTNEEPH2PS_LAST
XED_IFORMFL_VCVTNEOBF162PS_FIRST
XED_IFORMFL_VCVTNEOBF162PS_LAST
XED_IFORMFL_VCVTNEOPH2PS_FIRST
XED_IFORMFL_VCVTNEOPH2PS_LAST
XED_IFORMFL_VCVTNEPS2BF16_FIRST
XED_IFORMFL_VCVTNEPS2BF16_LAST
XED_IFORMFL_VCVTPD2DQ_FIRST
XED_IFORMFL_VCVTPD2DQ_LAST
XED_IFORMFL_VCVTPD2PH_FIRST
XED_IFORMFL_VCVTPD2PH_LAST
XED_IFORMFL_VCVTPD2PS_FIRST
XED_IFORMFL_VCVTPD2PS_LAST
XED_IFORMFL_VCVTPD2QQ_FIRST
XED_IFORMFL_VCVTPD2QQ_LAST
XED_IFORMFL_VCVTPD2UDQ_FIRST
XED_IFORMFL_VCVTPD2UDQ_LAST
XED_IFORMFL_VCVTPD2UQQ_FIRST
XED_IFORMFL_VCVTPD2UQQ_LAST
XED_IFORMFL_VCVTPH2DQ_FIRST
XED_IFORMFL_VCVTPH2DQ_LAST
XED_IFORMFL_VCVTPH2PD_FIRST
XED_IFORMFL_VCVTPH2PD_LAST
XED_IFORMFL_VCVTPH2PSX_FIRST
XED_IFORMFL_VCVTPH2PSX_LAST
XED_IFORMFL_VCVTPH2PS_FIRST
XED_IFORMFL_VCVTPH2PS_LAST
XED_IFORMFL_VCVTPH2QQ_FIRST
XED_IFORMFL_VCVTPH2QQ_LAST
XED_IFORMFL_VCVTPH2UDQ_FIRST
XED_IFORMFL_VCVTPH2UDQ_LAST
XED_IFORMFL_VCVTPH2UQQ_FIRST
XED_IFORMFL_VCVTPH2UQQ_LAST
XED_IFORMFL_VCVTPH2UW_FIRST
XED_IFORMFL_VCVTPH2UW_LAST
XED_IFORMFL_VCVTPH2W_FIRST
XED_IFORMFL_VCVTPH2W_LAST
XED_IFORMFL_VCVTPS2DQ_FIRST
XED_IFORMFL_VCVTPS2DQ_LAST
XED_IFORMFL_VCVTPS2PD_FIRST
XED_IFORMFL_VCVTPS2PD_LAST
XED_IFORMFL_VCVTPS2PHX_FIRST
XED_IFORMFL_VCVTPS2PHX_LAST
XED_IFORMFL_VCVTPS2PH_FIRST
XED_IFORMFL_VCVTPS2PH_LAST
XED_IFORMFL_VCVTPS2QQ_FIRST
XED_IFORMFL_VCVTPS2QQ_LAST
XED_IFORMFL_VCVTPS2UDQ_FIRST
XED_IFORMFL_VCVTPS2UDQ_LAST
XED_IFORMFL_VCVTPS2UQQ_FIRST
XED_IFORMFL_VCVTPS2UQQ_LAST
XED_IFORMFL_VCVTQQ2PD_FIRST
XED_IFORMFL_VCVTQQ2PD_LAST
XED_IFORMFL_VCVTQQ2PH_FIRST
XED_IFORMFL_VCVTQQ2PH_LAST
XED_IFORMFL_VCVTQQ2PS_FIRST
XED_IFORMFL_VCVTQQ2PS_LAST
XED_IFORMFL_VCVTSD2SH_FIRST
XED_IFORMFL_VCVTSD2SH_LAST
XED_IFORMFL_VCVTSD2SI_FIRST
XED_IFORMFL_VCVTSD2SI_LAST
XED_IFORMFL_VCVTSD2SS_FIRST
XED_IFORMFL_VCVTSD2SS_LAST
XED_IFORMFL_VCVTSD2USI_FIRST
XED_IFORMFL_VCVTSD2USI_LAST
XED_IFORMFL_VCVTSH2SD_FIRST
XED_IFORMFL_VCVTSH2SD_LAST
XED_IFORMFL_VCVTSH2SI_FIRST
XED_IFORMFL_VCVTSH2SI_LAST
XED_IFORMFL_VCVTSH2SS_FIRST
XED_IFORMFL_VCVTSH2SS_LAST
XED_IFORMFL_VCVTSH2USI_FIRST
XED_IFORMFL_VCVTSH2USI_LAST
XED_IFORMFL_VCVTSI2SD_FIRST
XED_IFORMFL_VCVTSI2SD_LAST
XED_IFORMFL_VCVTSI2SH_FIRST
XED_IFORMFL_VCVTSI2SH_LAST
XED_IFORMFL_VCVTSI2SS_FIRST
XED_IFORMFL_VCVTSI2SS_LAST
XED_IFORMFL_VCVTSS2SD_FIRST
XED_IFORMFL_VCVTSS2SD_LAST
XED_IFORMFL_VCVTSS2SH_FIRST
XED_IFORMFL_VCVTSS2SH_LAST
XED_IFORMFL_VCVTSS2SI_FIRST
XED_IFORMFL_VCVTSS2SI_LAST
XED_IFORMFL_VCVTSS2USI_FIRST
XED_IFORMFL_VCVTSS2USI_LAST
XED_IFORMFL_VCVTTPD2DQ_FIRST
XED_IFORMFL_VCVTTPD2DQ_LAST
XED_IFORMFL_VCVTTPD2QQ_FIRST
XED_IFORMFL_VCVTTPD2QQ_LAST
XED_IFORMFL_VCVTTPD2UDQ_FIRST
XED_IFORMFL_VCVTTPD2UDQ_LAST
XED_IFORMFL_VCVTTPD2UQQ_FIRST
XED_IFORMFL_VCVTTPD2UQQ_LAST
XED_IFORMFL_VCVTTPH2DQ_FIRST
XED_IFORMFL_VCVTTPH2DQ_LAST
XED_IFORMFL_VCVTTPH2QQ_FIRST
XED_IFORMFL_VCVTTPH2QQ_LAST
XED_IFORMFL_VCVTTPH2UDQ_FIRST
XED_IFORMFL_VCVTTPH2UDQ_LAST
XED_IFORMFL_VCVTTPH2UQQ_FIRST
XED_IFORMFL_VCVTTPH2UQQ_LAST
XED_IFORMFL_VCVTTPH2UW_FIRST
XED_IFORMFL_VCVTTPH2UW_LAST
XED_IFORMFL_VCVTTPH2W_FIRST
XED_IFORMFL_VCVTTPH2W_LAST
XED_IFORMFL_VCVTTPS2DQ_FIRST
XED_IFORMFL_VCVTTPS2DQ_LAST
XED_IFORMFL_VCVTTPS2QQ_FIRST
XED_IFORMFL_VCVTTPS2QQ_LAST
XED_IFORMFL_VCVTTPS2UDQ_FIRST
XED_IFORMFL_VCVTTPS2UDQ_LAST
XED_IFORMFL_VCVTTPS2UQQ_FIRST
XED_IFORMFL_VCVTTPS2UQQ_LAST
XED_IFORMFL_VCVTTSD2SI_FIRST
XED_IFORMFL_VCVTTSD2SI_LAST
XED_IFORMFL_VCVTTSD2USI_FIRST
XED_IFORMFL_VCVTTSD2USI_LAST
XED_IFORMFL_VCVTTSH2SI_FIRST
XED_IFORMFL_VCVTTSH2SI_LAST
XED_IFORMFL_VCVTTSH2USI_FIRST
XED_IFORMFL_VCVTTSH2USI_LAST
XED_IFORMFL_VCVTTSS2SI_FIRST
XED_IFORMFL_VCVTTSS2SI_LAST
XED_IFORMFL_VCVTTSS2USI_FIRST
XED_IFORMFL_VCVTTSS2USI_LAST
XED_IFORMFL_VCVTUDQ2PD_FIRST
XED_IFORMFL_VCVTUDQ2PD_LAST
XED_IFORMFL_VCVTUDQ2PH_FIRST
XED_IFORMFL_VCVTUDQ2PH_LAST
XED_IFORMFL_VCVTUDQ2PS_FIRST
XED_IFORMFL_VCVTUDQ2PS_LAST
XED_IFORMFL_VCVTUQQ2PD_FIRST
XED_IFORMFL_VCVTUQQ2PD_LAST
XED_IFORMFL_VCVTUQQ2PH_FIRST
XED_IFORMFL_VCVTUQQ2PH_LAST
XED_IFORMFL_VCVTUQQ2PS_FIRST
XED_IFORMFL_VCVTUQQ2PS_LAST
XED_IFORMFL_VCVTUSI2SD_FIRST
XED_IFORMFL_VCVTUSI2SD_LAST
XED_IFORMFL_VCVTUSI2SH_FIRST
XED_IFORMFL_VCVTUSI2SH_LAST
XED_IFORMFL_VCVTUSI2SS_FIRST
XED_IFORMFL_VCVTUSI2SS_LAST
XED_IFORMFL_VCVTUW2PH_FIRST
XED_IFORMFL_VCVTUW2PH_LAST
XED_IFORMFL_VCVTW2PH_FIRST
XED_IFORMFL_VCVTW2PH_LAST
XED_IFORMFL_VDBPSADBW_FIRST
XED_IFORMFL_VDBPSADBW_LAST
XED_IFORMFL_VDIVPD_FIRST
XED_IFORMFL_VDIVPD_LAST
XED_IFORMFL_VDIVPH_FIRST
XED_IFORMFL_VDIVPH_LAST
XED_IFORMFL_VDIVPS_FIRST
XED_IFORMFL_VDIVPS_LAST
XED_IFORMFL_VDIVSD_FIRST
XED_IFORMFL_VDIVSD_LAST
XED_IFORMFL_VDIVSH_FIRST
XED_IFORMFL_VDIVSH_LAST
XED_IFORMFL_VDIVSS_FIRST
XED_IFORMFL_VDIVSS_LAST
XED_IFORMFL_VDPBF16PS_FIRST
XED_IFORMFL_VDPBF16PS_LAST
XED_IFORMFL_VDPPD_FIRST
XED_IFORMFL_VDPPD_LAST
XED_IFORMFL_VDPPS_FIRST
XED_IFORMFL_VDPPS_LAST
XED_IFORMFL_VERR_FIRST
XED_IFORMFL_VERR_LAST
XED_IFORMFL_VERW_FIRST
XED_IFORMFL_VERW_LAST
XED_IFORMFL_VEXP2PD_FIRST
XED_IFORMFL_VEXP2PD_LAST
XED_IFORMFL_VEXP2PS_FIRST
XED_IFORMFL_VEXP2PS_LAST
XED_IFORMFL_VEXPANDPD_FIRST
XED_IFORMFL_VEXPANDPD_LAST
XED_IFORMFL_VEXPANDPS_FIRST
XED_IFORMFL_VEXPANDPS_LAST
XED_IFORMFL_VEXTRACTF32X4_FIRST
XED_IFORMFL_VEXTRACTF32X4_LAST
XED_IFORMFL_VEXTRACTF32X8_FIRST
XED_IFORMFL_VEXTRACTF32X8_LAST
XED_IFORMFL_VEXTRACTF64X2_FIRST
XED_IFORMFL_VEXTRACTF64X2_LAST
XED_IFORMFL_VEXTRACTF64X4_FIRST
XED_IFORMFL_VEXTRACTF64X4_LAST
XED_IFORMFL_VEXTRACTF128_FIRST
XED_IFORMFL_VEXTRACTF128_LAST
XED_IFORMFL_VEXTRACTI32X4_FIRST
XED_IFORMFL_VEXTRACTI32X4_LAST
XED_IFORMFL_VEXTRACTI32X8_FIRST
XED_IFORMFL_VEXTRACTI32X8_LAST
XED_IFORMFL_VEXTRACTI64X2_FIRST
XED_IFORMFL_VEXTRACTI64X2_LAST
XED_IFORMFL_VEXTRACTI64X4_FIRST
XED_IFORMFL_VEXTRACTI64X4_LAST
XED_IFORMFL_VEXTRACTI128_FIRST
XED_IFORMFL_VEXTRACTI128_LAST
XED_IFORMFL_VEXTRACTPS_FIRST
XED_IFORMFL_VEXTRACTPS_LAST
XED_IFORMFL_VFCMADDCPH_FIRST
XED_IFORMFL_VFCMADDCPH_LAST
XED_IFORMFL_VFCMADDCSH_FIRST
XED_IFORMFL_VFCMADDCSH_LAST
XED_IFORMFL_VFCMULCPH_FIRST
XED_IFORMFL_VFCMULCPH_LAST
XED_IFORMFL_VFCMULCSH_FIRST
XED_IFORMFL_VFCMULCSH_LAST
XED_IFORMFL_VFIXUPIMMPD_FIRST
XED_IFORMFL_VFIXUPIMMPD_LAST
XED_IFORMFL_VFIXUPIMMPS_FIRST
XED_IFORMFL_VFIXUPIMMPS_LAST
XED_IFORMFL_VFIXUPIMMSD_FIRST
XED_IFORMFL_VFIXUPIMMSD_LAST
XED_IFORMFL_VFIXUPIMMSS_FIRST
XED_IFORMFL_VFIXUPIMMSS_LAST
XED_IFORMFL_VFMADD132PD_FIRST
XED_IFORMFL_VFMADD132PD_LAST
XED_IFORMFL_VFMADD132PH_FIRST
XED_IFORMFL_VFMADD132PH_LAST
XED_IFORMFL_VFMADD132PS_FIRST
XED_IFORMFL_VFMADD132PS_LAST
XED_IFORMFL_VFMADD132SD_FIRST
XED_IFORMFL_VFMADD132SD_LAST
XED_IFORMFL_VFMADD132SH_FIRST
XED_IFORMFL_VFMADD132SH_LAST
XED_IFORMFL_VFMADD132SS_FIRST
XED_IFORMFL_VFMADD132SS_LAST
XED_IFORMFL_VFMADD213PD_FIRST
XED_IFORMFL_VFMADD213PD_LAST
XED_IFORMFL_VFMADD213PH_FIRST
XED_IFORMFL_VFMADD213PH_LAST
XED_IFORMFL_VFMADD213PS_FIRST
XED_IFORMFL_VFMADD213PS_LAST
XED_IFORMFL_VFMADD213SD_FIRST
XED_IFORMFL_VFMADD213SD_LAST
XED_IFORMFL_VFMADD213SH_FIRST
XED_IFORMFL_VFMADD213SH_LAST
XED_IFORMFL_VFMADD213SS_FIRST
XED_IFORMFL_VFMADD213SS_LAST
XED_IFORMFL_VFMADD231PD_FIRST
XED_IFORMFL_VFMADD231PD_LAST
XED_IFORMFL_VFMADD231PH_FIRST
XED_IFORMFL_VFMADD231PH_LAST
XED_IFORMFL_VFMADD231PS_FIRST
XED_IFORMFL_VFMADD231PS_LAST
XED_IFORMFL_VFMADD231SD_FIRST
XED_IFORMFL_VFMADD231SD_LAST
XED_IFORMFL_VFMADD231SH_FIRST
XED_IFORMFL_VFMADD231SH_LAST
XED_IFORMFL_VFMADD231SS_FIRST
XED_IFORMFL_VFMADD231SS_LAST
XED_IFORMFL_VFMADDCPH_FIRST
XED_IFORMFL_VFMADDCPH_LAST
XED_IFORMFL_VFMADDCSH_FIRST
XED_IFORMFL_VFMADDCSH_LAST
XED_IFORMFL_VFMADDPD_FIRST
XED_IFORMFL_VFMADDPD_LAST
XED_IFORMFL_VFMADDPS_FIRST
XED_IFORMFL_VFMADDPS_LAST
XED_IFORMFL_VFMADDSD_FIRST
XED_IFORMFL_VFMADDSD_LAST
XED_IFORMFL_VFMADDSS_FIRST
XED_IFORMFL_VFMADDSS_LAST
XED_IFORMFL_VFMADDSUB132PD_FIRST
XED_IFORMFL_VFMADDSUB132PD_LAST
XED_IFORMFL_VFMADDSUB132PH_FIRST
XED_IFORMFL_VFMADDSUB132PH_LAST
XED_IFORMFL_VFMADDSUB132PS_FIRST
XED_IFORMFL_VFMADDSUB132PS_LAST
XED_IFORMFL_VFMADDSUB213PD_FIRST
XED_IFORMFL_VFMADDSUB213PD_LAST
XED_IFORMFL_VFMADDSUB213PH_FIRST
XED_IFORMFL_VFMADDSUB213PH_LAST
XED_IFORMFL_VFMADDSUB213PS_FIRST
XED_IFORMFL_VFMADDSUB213PS_LAST
XED_IFORMFL_VFMADDSUB231PD_FIRST
XED_IFORMFL_VFMADDSUB231PD_LAST
XED_IFORMFL_VFMADDSUB231PH_FIRST
XED_IFORMFL_VFMADDSUB231PH_LAST
XED_IFORMFL_VFMADDSUB231PS_FIRST
XED_IFORMFL_VFMADDSUB231PS_LAST
XED_IFORMFL_VFMADDSUBPD_FIRST
XED_IFORMFL_VFMADDSUBPD_LAST
XED_IFORMFL_VFMADDSUBPS_FIRST
XED_IFORMFL_VFMADDSUBPS_LAST
XED_IFORMFL_VFMSUB132PD_FIRST
XED_IFORMFL_VFMSUB132PD_LAST
XED_IFORMFL_VFMSUB132PH_FIRST
XED_IFORMFL_VFMSUB132PH_LAST
XED_IFORMFL_VFMSUB132PS_FIRST
XED_IFORMFL_VFMSUB132PS_LAST
XED_IFORMFL_VFMSUB132SD_FIRST
XED_IFORMFL_VFMSUB132SD_LAST
XED_IFORMFL_VFMSUB132SH_FIRST
XED_IFORMFL_VFMSUB132SH_LAST
XED_IFORMFL_VFMSUB132SS_FIRST
XED_IFORMFL_VFMSUB132SS_LAST
XED_IFORMFL_VFMSUB213PD_FIRST
XED_IFORMFL_VFMSUB213PD_LAST
XED_IFORMFL_VFMSUB213PH_FIRST
XED_IFORMFL_VFMSUB213PH_LAST
XED_IFORMFL_VFMSUB213PS_FIRST
XED_IFORMFL_VFMSUB213PS_LAST
XED_IFORMFL_VFMSUB213SD_FIRST
XED_IFORMFL_VFMSUB213SD_LAST
XED_IFORMFL_VFMSUB213SH_FIRST
XED_IFORMFL_VFMSUB213SH_LAST
XED_IFORMFL_VFMSUB213SS_FIRST
XED_IFORMFL_VFMSUB213SS_LAST
XED_IFORMFL_VFMSUB231PD_FIRST
XED_IFORMFL_VFMSUB231PD_LAST
XED_IFORMFL_VFMSUB231PH_FIRST
XED_IFORMFL_VFMSUB231PH_LAST
XED_IFORMFL_VFMSUB231PS_FIRST
XED_IFORMFL_VFMSUB231PS_LAST
XED_IFORMFL_VFMSUB231SD_FIRST
XED_IFORMFL_VFMSUB231SD_LAST
XED_IFORMFL_VFMSUB231SH_FIRST
XED_IFORMFL_VFMSUB231SH_LAST
XED_IFORMFL_VFMSUB231SS_FIRST
XED_IFORMFL_VFMSUB231SS_LAST
XED_IFORMFL_VFMSUBADD132PD_FIRST
XED_IFORMFL_VFMSUBADD132PD_LAST
XED_IFORMFL_VFMSUBADD132PH_FIRST
XED_IFORMFL_VFMSUBADD132PH_LAST
XED_IFORMFL_VFMSUBADD132PS_FIRST
XED_IFORMFL_VFMSUBADD132PS_LAST
XED_IFORMFL_VFMSUBADD213PD_FIRST
XED_IFORMFL_VFMSUBADD213PD_LAST
XED_IFORMFL_VFMSUBADD213PH_FIRST
XED_IFORMFL_VFMSUBADD213PH_LAST
XED_IFORMFL_VFMSUBADD213PS_FIRST
XED_IFORMFL_VFMSUBADD213PS_LAST
XED_IFORMFL_VFMSUBADD231PD_FIRST
XED_IFORMFL_VFMSUBADD231PD_LAST
XED_IFORMFL_VFMSUBADD231PH_FIRST
XED_IFORMFL_VFMSUBADD231PH_LAST
XED_IFORMFL_VFMSUBADD231PS_FIRST
XED_IFORMFL_VFMSUBADD231PS_LAST
XED_IFORMFL_VFMSUBADDPD_FIRST
XED_IFORMFL_VFMSUBADDPD_LAST
XED_IFORMFL_VFMSUBADDPS_FIRST
XED_IFORMFL_VFMSUBADDPS_LAST
XED_IFORMFL_VFMSUBPD_FIRST
XED_IFORMFL_VFMSUBPD_LAST
XED_IFORMFL_VFMSUBPS_FIRST
XED_IFORMFL_VFMSUBPS_LAST
XED_IFORMFL_VFMSUBSD_FIRST
XED_IFORMFL_VFMSUBSD_LAST
XED_IFORMFL_VFMSUBSS_FIRST
XED_IFORMFL_VFMSUBSS_LAST
XED_IFORMFL_VFMULCPH_FIRST
XED_IFORMFL_VFMULCPH_LAST
XED_IFORMFL_VFMULCSH_FIRST
XED_IFORMFL_VFMULCSH_LAST
XED_IFORMFL_VFNMADD132PD_FIRST
XED_IFORMFL_VFNMADD132PD_LAST
XED_IFORMFL_VFNMADD132PH_FIRST
XED_IFORMFL_VFNMADD132PH_LAST
XED_IFORMFL_VFNMADD132PS_FIRST
XED_IFORMFL_VFNMADD132PS_LAST
XED_IFORMFL_VFNMADD132SD_FIRST
XED_IFORMFL_VFNMADD132SD_LAST
XED_IFORMFL_VFNMADD132SH_FIRST
XED_IFORMFL_VFNMADD132SH_LAST
XED_IFORMFL_VFNMADD132SS_FIRST
XED_IFORMFL_VFNMADD132SS_LAST
XED_IFORMFL_VFNMADD213PD_FIRST
XED_IFORMFL_VFNMADD213PD_LAST
XED_IFORMFL_VFNMADD213PH_FIRST
XED_IFORMFL_VFNMADD213PH_LAST
XED_IFORMFL_VFNMADD213PS_FIRST
XED_IFORMFL_VFNMADD213PS_LAST
XED_IFORMFL_VFNMADD213SD_FIRST
XED_IFORMFL_VFNMADD213SD_LAST
XED_IFORMFL_VFNMADD213SH_FIRST
XED_IFORMFL_VFNMADD213SH_LAST
XED_IFORMFL_VFNMADD213SS_FIRST
XED_IFORMFL_VFNMADD213SS_LAST
XED_IFORMFL_VFNMADD231PD_FIRST
XED_IFORMFL_VFNMADD231PD_LAST
XED_IFORMFL_VFNMADD231PH_FIRST
XED_IFORMFL_VFNMADD231PH_LAST
XED_IFORMFL_VFNMADD231PS_FIRST
XED_IFORMFL_VFNMADD231PS_LAST
XED_IFORMFL_VFNMADD231SD_FIRST
XED_IFORMFL_VFNMADD231SD_LAST
XED_IFORMFL_VFNMADD231SH_FIRST
XED_IFORMFL_VFNMADD231SH_LAST
XED_IFORMFL_VFNMADD231SS_FIRST
XED_IFORMFL_VFNMADD231SS_LAST
XED_IFORMFL_VFNMADDPD_FIRST
XED_IFORMFL_VFNMADDPD_LAST
XED_IFORMFL_VFNMADDPS_FIRST
XED_IFORMFL_VFNMADDPS_LAST
XED_IFORMFL_VFNMADDSD_FIRST
XED_IFORMFL_VFNMADDSD_LAST
XED_IFORMFL_VFNMADDSS_FIRST
XED_IFORMFL_VFNMADDSS_LAST
XED_IFORMFL_VFNMSUB132PD_FIRST
XED_IFORMFL_VFNMSUB132PD_LAST
XED_IFORMFL_VFNMSUB132PH_FIRST
XED_IFORMFL_VFNMSUB132PH_LAST
XED_IFORMFL_VFNMSUB132PS_FIRST
XED_IFORMFL_VFNMSUB132PS_LAST
XED_IFORMFL_VFNMSUB132SD_FIRST
XED_IFORMFL_VFNMSUB132SD_LAST
XED_IFORMFL_VFNMSUB132SH_FIRST
XED_IFORMFL_VFNMSUB132SH_LAST
XED_IFORMFL_VFNMSUB132SS_FIRST
XED_IFORMFL_VFNMSUB132SS_LAST
XED_IFORMFL_VFNMSUB213PD_FIRST
XED_IFORMFL_VFNMSUB213PD_LAST
XED_IFORMFL_VFNMSUB213PH_FIRST
XED_IFORMFL_VFNMSUB213PH_LAST
XED_IFORMFL_VFNMSUB213PS_FIRST
XED_IFORMFL_VFNMSUB213PS_LAST
XED_IFORMFL_VFNMSUB213SD_FIRST
XED_IFORMFL_VFNMSUB213SD_LAST
XED_IFORMFL_VFNMSUB213SH_FIRST
XED_IFORMFL_VFNMSUB213SH_LAST
XED_IFORMFL_VFNMSUB213SS_FIRST
XED_IFORMFL_VFNMSUB213SS_LAST
XED_IFORMFL_VFNMSUB231PD_FIRST
XED_IFORMFL_VFNMSUB231PD_LAST
XED_IFORMFL_VFNMSUB231PH_FIRST
XED_IFORMFL_VFNMSUB231PH_LAST
XED_IFORMFL_VFNMSUB231PS_FIRST
XED_IFORMFL_VFNMSUB231PS_LAST
XED_IFORMFL_VFNMSUB231SD_FIRST
XED_IFORMFL_VFNMSUB231SD_LAST
XED_IFORMFL_VFNMSUB231SH_FIRST
XED_IFORMFL_VFNMSUB231SH_LAST
XED_IFORMFL_VFNMSUB231SS_FIRST
XED_IFORMFL_VFNMSUB231SS_LAST
XED_IFORMFL_VFNMSUBPD_FIRST
XED_IFORMFL_VFNMSUBPD_LAST
XED_IFORMFL_VFNMSUBPS_FIRST
XED_IFORMFL_VFNMSUBPS_LAST
XED_IFORMFL_VFNMSUBSD_FIRST
XED_IFORMFL_VFNMSUBSD_LAST
XED_IFORMFL_VFNMSUBSS_FIRST
XED_IFORMFL_VFNMSUBSS_LAST
XED_IFORMFL_VFPCLASSPD_FIRST
XED_IFORMFL_VFPCLASSPD_LAST
XED_IFORMFL_VFPCLASSPH_FIRST
XED_IFORMFL_VFPCLASSPH_LAST
XED_IFORMFL_VFPCLASSPS_FIRST
XED_IFORMFL_VFPCLASSPS_LAST
XED_IFORMFL_VFPCLASSSD_FIRST
XED_IFORMFL_VFPCLASSSD_LAST
XED_IFORMFL_VFPCLASSSH_FIRST
XED_IFORMFL_VFPCLASSSH_LAST
XED_IFORMFL_VFPCLASSSS_FIRST
XED_IFORMFL_VFPCLASSSS_LAST
XED_IFORMFL_VFRCZPD_FIRST
XED_IFORMFL_VFRCZPD_LAST
XED_IFORMFL_VFRCZPS_FIRST
XED_IFORMFL_VFRCZPS_LAST
XED_IFORMFL_VFRCZSD_FIRST
XED_IFORMFL_VFRCZSD_LAST
XED_IFORMFL_VFRCZSS_FIRST
XED_IFORMFL_VFRCZSS_LAST
XED_IFORMFL_VGATHERDPD_FIRST
XED_IFORMFL_VGATHERDPD_LAST
XED_IFORMFL_VGATHERDPS_FIRST
XED_IFORMFL_VGATHERDPS_LAST
XED_IFORMFL_VGATHERPF0DPD_FIRST
XED_IFORMFL_VGATHERPF0DPD_LAST
XED_IFORMFL_VGATHERPF0DPS_FIRST
XED_IFORMFL_VGATHERPF0DPS_LAST
XED_IFORMFL_VGATHERPF0QPD_FIRST
XED_IFORMFL_VGATHERPF0QPD_LAST
XED_IFORMFL_VGATHERPF0QPS_FIRST
XED_IFORMFL_VGATHERPF0QPS_LAST
XED_IFORMFL_VGATHERPF1DPD_FIRST
XED_IFORMFL_VGATHERPF1DPD_LAST
XED_IFORMFL_VGATHERPF1DPS_FIRST
XED_IFORMFL_VGATHERPF1DPS_LAST
XED_IFORMFL_VGATHERPF1QPD_FIRST
XED_IFORMFL_VGATHERPF1QPD_LAST
XED_IFORMFL_VGATHERPF1QPS_FIRST
XED_IFORMFL_VGATHERPF1QPS_LAST
XED_IFORMFL_VGATHERQPD_FIRST
XED_IFORMFL_VGATHERQPD_LAST
XED_IFORMFL_VGATHERQPS_FIRST
XED_IFORMFL_VGATHERQPS_LAST
XED_IFORMFL_VGETEXPPD_FIRST
XED_IFORMFL_VGETEXPPD_LAST
XED_IFORMFL_VGETEXPPH_FIRST
XED_IFORMFL_VGETEXPPH_LAST
XED_IFORMFL_VGETEXPPS_FIRST
XED_IFORMFL_VGETEXPPS_LAST
XED_IFORMFL_VGETEXPSD_FIRST
XED_IFORMFL_VGETEXPSD_LAST
XED_IFORMFL_VGETEXPSH_FIRST
XED_IFORMFL_VGETEXPSH_LAST
XED_IFORMFL_VGETEXPSS_FIRST
XED_IFORMFL_VGETEXPSS_LAST
XED_IFORMFL_VGETMANTPD_FIRST
XED_IFORMFL_VGETMANTPD_LAST
XED_IFORMFL_VGETMANTPH_FIRST
XED_IFORMFL_VGETMANTPH_LAST
XED_IFORMFL_VGETMANTPS_FIRST
XED_IFORMFL_VGETMANTPS_LAST
XED_IFORMFL_VGETMANTSD_FIRST
XED_IFORMFL_VGETMANTSD_LAST
XED_IFORMFL_VGETMANTSH_FIRST
XED_IFORMFL_VGETMANTSH_LAST
XED_IFORMFL_VGETMANTSS_FIRST
XED_IFORMFL_VGETMANTSS_LAST
XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST
XED_IFORMFL_VGF2P8AFFINEINVQB_LAST
XED_IFORMFL_VGF2P8AFFINEQB_FIRST
XED_IFORMFL_VGF2P8AFFINEQB_LAST
XED_IFORMFL_VGF2P8MULB_FIRST
XED_IFORMFL_VGF2P8MULB_LAST
XED_IFORMFL_VHADDPD_FIRST
XED_IFORMFL_VHADDPD_LAST
XED_IFORMFL_VHADDPS_FIRST
XED_IFORMFL_VHADDPS_LAST
XED_IFORMFL_VHSUBPD_FIRST
XED_IFORMFL_VHSUBPD_LAST
XED_IFORMFL_VHSUBPS_FIRST
XED_IFORMFL_VHSUBPS_LAST
XED_IFORMFL_VINSERTF32X4_FIRST
XED_IFORMFL_VINSERTF32X4_LAST
XED_IFORMFL_VINSERTF32X8_FIRST
XED_IFORMFL_VINSERTF32X8_LAST
XED_IFORMFL_VINSERTF64X2_FIRST
XED_IFORMFL_VINSERTF64X2_LAST
XED_IFORMFL_VINSERTF64X4_FIRST
XED_IFORMFL_VINSERTF64X4_LAST
XED_IFORMFL_VINSERTF128_FIRST
XED_IFORMFL_VINSERTF128_LAST
XED_IFORMFL_VINSERTI32X4_FIRST
XED_IFORMFL_VINSERTI32X4_LAST
XED_IFORMFL_VINSERTI32X8_FIRST
XED_IFORMFL_VINSERTI32X8_LAST
XED_IFORMFL_VINSERTI64X2_FIRST
XED_IFORMFL_VINSERTI64X2_LAST
XED_IFORMFL_VINSERTI64X4_FIRST
XED_IFORMFL_VINSERTI64X4_LAST
XED_IFORMFL_VINSERTI128_FIRST
XED_IFORMFL_VINSERTI128_LAST
XED_IFORMFL_VINSERTPS_FIRST
XED_IFORMFL_VINSERTPS_LAST
XED_IFORMFL_VLDDQU_FIRST
XED_IFORMFL_VLDDQU_LAST
XED_IFORMFL_VLDMXCSR_FIRST
XED_IFORMFL_VLDMXCSR_LAST
XED_IFORMFL_VMASKMOVDQU_FIRST
XED_IFORMFL_VMASKMOVDQU_LAST
XED_IFORMFL_VMASKMOVPD_FIRST
XED_IFORMFL_VMASKMOVPD_LAST
XED_IFORMFL_VMASKMOVPS_FIRST
XED_IFORMFL_VMASKMOVPS_LAST
XED_IFORMFL_VMAXPD_FIRST
XED_IFORMFL_VMAXPD_LAST
XED_IFORMFL_VMAXPH_FIRST
XED_IFORMFL_VMAXPH_LAST
XED_IFORMFL_VMAXPS_FIRST
XED_IFORMFL_VMAXPS_LAST
XED_IFORMFL_VMAXSD_FIRST
XED_IFORMFL_VMAXSD_LAST
XED_IFORMFL_VMAXSH_FIRST
XED_IFORMFL_VMAXSH_LAST
XED_IFORMFL_VMAXSS_FIRST
XED_IFORMFL_VMAXSS_LAST
XED_IFORMFL_VMCALL_FIRST
XED_IFORMFL_VMCALL_LAST
XED_IFORMFL_VMCLEAR_FIRST
XED_IFORMFL_VMCLEAR_LAST
XED_IFORMFL_VMFUNC_FIRST
XED_IFORMFL_VMFUNC_LAST
XED_IFORMFL_VMINPD_FIRST
XED_IFORMFL_VMINPD_LAST
XED_IFORMFL_VMINPH_FIRST
XED_IFORMFL_VMINPH_LAST
XED_IFORMFL_VMINPS_FIRST
XED_IFORMFL_VMINPS_LAST
XED_IFORMFL_VMINSD_FIRST
XED_IFORMFL_VMINSD_LAST
XED_IFORMFL_VMINSH_FIRST
XED_IFORMFL_VMINSH_LAST
XED_IFORMFL_VMINSS_FIRST
XED_IFORMFL_VMINSS_LAST
XED_IFORMFL_VMLAUNCH_FIRST
XED_IFORMFL_VMLAUNCH_LAST
XED_IFORMFL_VMLOAD_FIRST
XED_IFORMFL_VMLOAD_LAST
XED_IFORMFL_VMMCALL_FIRST
XED_IFORMFL_VMMCALL_LAST
XED_IFORMFL_VMOVAPD_FIRST
XED_IFORMFL_VMOVAPD_LAST
XED_IFORMFL_VMOVAPS_FIRST
XED_IFORMFL_VMOVAPS_LAST
XED_IFORMFL_VMOVDDUP_FIRST
XED_IFORMFL_VMOVDDUP_LAST
XED_IFORMFL_VMOVDQA32_FIRST
XED_IFORMFL_VMOVDQA32_LAST
XED_IFORMFL_VMOVDQA64_FIRST
XED_IFORMFL_VMOVDQA64_LAST
XED_IFORMFL_VMOVDQA_FIRST
XED_IFORMFL_VMOVDQA_LAST
XED_IFORMFL_VMOVDQU8_FIRST
XED_IFORMFL_VMOVDQU8_LAST
XED_IFORMFL_VMOVDQU16_FIRST
XED_IFORMFL_VMOVDQU16_LAST
XED_IFORMFL_VMOVDQU32_FIRST
XED_IFORMFL_VMOVDQU32_LAST
XED_IFORMFL_VMOVDQU64_FIRST
XED_IFORMFL_VMOVDQU64_LAST
XED_IFORMFL_VMOVDQU_FIRST
XED_IFORMFL_VMOVDQU_LAST
XED_IFORMFL_VMOVD_FIRST
XED_IFORMFL_VMOVD_LAST
XED_IFORMFL_VMOVHLPS_FIRST
XED_IFORMFL_VMOVHLPS_LAST
XED_IFORMFL_VMOVHPD_FIRST
XED_IFORMFL_VMOVHPD_LAST
XED_IFORMFL_VMOVHPS_FIRST
XED_IFORMFL_VMOVHPS_LAST
XED_IFORMFL_VMOVLHPS_FIRST
XED_IFORMFL_VMOVLHPS_LAST
XED_IFORMFL_VMOVLPD_FIRST
XED_IFORMFL_VMOVLPD_LAST
XED_IFORMFL_VMOVLPS_FIRST
XED_IFORMFL_VMOVLPS_LAST
XED_IFORMFL_VMOVMSKPD_FIRST
XED_IFORMFL_VMOVMSKPD_LAST
XED_IFORMFL_VMOVMSKPS_FIRST
XED_IFORMFL_VMOVMSKPS_LAST
XED_IFORMFL_VMOVNTDQA_FIRST
XED_IFORMFL_VMOVNTDQA_LAST
XED_IFORMFL_VMOVNTDQ_FIRST
XED_IFORMFL_VMOVNTDQ_LAST
XED_IFORMFL_VMOVNTPD_FIRST
XED_IFORMFL_VMOVNTPD_LAST
XED_IFORMFL_VMOVNTPS_FIRST
XED_IFORMFL_VMOVNTPS_LAST
XED_IFORMFL_VMOVQ_FIRST
XED_IFORMFL_VMOVQ_LAST
XED_IFORMFL_VMOVSD_FIRST
XED_IFORMFL_VMOVSD_LAST
XED_IFORMFL_VMOVSHDUP_FIRST
XED_IFORMFL_VMOVSHDUP_LAST
XED_IFORMFL_VMOVSH_FIRST
XED_IFORMFL_VMOVSH_LAST
XED_IFORMFL_VMOVSLDUP_FIRST
XED_IFORMFL_VMOVSLDUP_LAST
XED_IFORMFL_VMOVSS_FIRST
XED_IFORMFL_VMOVSS_LAST
XED_IFORMFL_VMOVUPD_FIRST
XED_IFORMFL_VMOVUPD_LAST
XED_IFORMFL_VMOVUPS_FIRST
XED_IFORMFL_VMOVUPS_LAST
XED_IFORMFL_VMOVW_FIRST
XED_IFORMFL_VMOVW_LAST
XED_IFORMFL_VMPSADBW_FIRST
XED_IFORMFL_VMPSADBW_LAST
XED_IFORMFL_VMPTRLD_FIRST
XED_IFORMFL_VMPTRLD_LAST
XED_IFORMFL_VMPTRST_FIRST
XED_IFORMFL_VMPTRST_LAST
XED_IFORMFL_VMREAD_FIRST
XED_IFORMFL_VMREAD_LAST
XED_IFORMFL_VMRESUME_FIRST
XED_IFORMFL_VMRESUME_LAST
XED_IFORMFL_VMRUN_FIRST
XED_IFORMFL_VMRUN_LAST
XED_IFORMFL_VMSAVE_FIRST
XED_IFORMFL_VMSAVE_LAST
XED_IFORMFL_VMULPD_FIRST
XED_IFORMFL_VMULPD_LAST
XED_IFORMFL_VMULPH_FIRST
XED_IFORMFL_VMULPH_LAST
XED_IFORMFL_VMULPS_FIRST
XED_IFORMFL_VMULPS_LAST
XED_IFORMFL_VMULSD_FIRST
XED_IFORMFL_VMULSD_LAST
XED_IFORMFL_VMULSH_FIRST
XED_IFORMFL_VMULSH_LAST
XED_IFORMFL_VMULSS_FIRST
XED_IFORMFL_VMULSS_LAST
XED_IFORMFL_VMWRITE_FIRST
XED_IFORMFL_VMWRITE_LAST
XED_IFORMFL_VMXOFF_FIRST
XED_IFORMFL_VMXOFF_LAST
XED_IFORMFL_VMXON_FIRST
XED_IFORMFL_VMXON_LAST
XED_IFORMFL_VORPD_FIRST
XED_IFORMFL_VORPD_LAST
XED_IFORMFL_VORPS_FIRST
XED_IFORMFL_VORPS_LAST
XED_IFORMFL_VP2INTERSECTD_FIRST
XED_IFORMFL_VP2INTERSECTD_LAST
XED_IFORMFL_VP2INTERSECTQ_FIRST
XED_IFORMFL_VP2INTERSECTQ_LAST
XED_IFORMFL_VP4DPWSSDS_FIRST
XED_IFORMFL_VP4DPWSSDS_LAST
XED_IFORMFL_VP4DPWSSD_FIRST
XED_IFORMFL_VP4DPWSSD_LAST
XED_IFORMFL_VPABSB_FIRST
XED_IFORMFL_VPABSB_LAST
XED_IFORMFL_VPABSD_FIRST
XED_IFORMFL_VPABSD_LAST
XED_IFORMFL_VPABSQ_FIRST
XED_IFORMFL_VPABSQ_LAST
XED_IFORMFL_VPABSW_FIRST
XED_IFORMFL_VPABSW_LAST
XED_IFORMFL_VPACKSSDW_FIRST
XED_IFORMFL_VPACKSSDW_LAST
XED_IFORMFL_VPACKSSWB_FIRST
XED_IFORMFL_VPACKSSWB_LAST
XED_IFORMFL_VPACKUSDW_FIRST
XED_IFORMFL_VPACKUSDW_LAST
XED_IFORMFL_VPACKUSWB_FIRST
XED_IFORMFL_VPACKUSWB_LAST
XED_IFORMFL_VPADDB_FIRST
XED_IFORMFL_VPADDB_LAST
XED_IFORMFL_VPADDD_FIRST
XED_IFORMFL_VPADDD_LAST
XED_IFORMFL_VPADDQ_FIRST
XED_IFORMFL_VPADDQ_LAST
XED_IFORMFL_VPADDSB_FIRST
XED_IFORMFL_VPADDSB_LAST
XED_IFORMFL_VPADDSW_FIRST
XED_IFORMFL_VPADDSW_LAST
XED_IFORMFL_VPADDUSB_FIRST
XED_IFORMFL_VPADDUSB_LAST
XED_IFORMFL_VPADDUSW_FIRST
XED_IFORMFL_VPADDUSW_LAST
XED_IFORMFL_VPADDW_FIRST
XED_IFORMFL_VPADDW_LAST
XED_IFORMFL_VPALIGNR_FIRST
XED_IFORMFL_VPALIGNR_LAST
XED_IFORMFL_VPANDD_FIRST
XED_IFORMFL_VPANDD_LAST
XED_IFORMFL_VPANDND_FIRST
XED_IFORMFL_VPANDND_LAST
XED_IFORMFL_VPANDNQ_FIRST
XED_IFORMFL_VPANDNQ_LAST
XED_IFORMFL_VPANDN_FIRST
XED_IFORMFL_VPANDN_LAST
XED_IFORMFL_VPANDQ_FIRST
XED_IFORMFL_VPANDQ_LAST
XED_IFORMFL_VPAND_FIRST
XED_IFORMFL_VPAND_LAST
XED_IFORMFL_VPAVGB_FIRST
XED_IFORMFL_VPAVGB_LAST
XED_IFORMFL_VPAVGW_FIRST
XED_IFORMFL_VPAVGW_LAST
XED_IFORMFL_VPBLENDD_FIRST
XED_IFORMFL_VPBLENDD_LAST
XED_IFORMFL_VPBLENDMB_FIRST
XED_IFORMFL_VPBLENDMB_LAST
XED_IFORMFL_VPBLENDMD_FIRST
XED_IFORMFL_VPBLENDMD_LAST
XED_IFORMFL_VPBLENDMQ_FIRST
XED_IFORMFL_VPBLENDMQ_LAST
XED_IFORMFL_VPBLENDMW_FIRST
XED_IFORMFL_VPBLENDMW_LAST
XED_IFORMFL_VPBLENDVB_FIRST
XED_IFORMFL_VPBLENDVB_LAST
XED_IFORMFL_VPBLENDW_FIRST
XED_IFORMFL_VPBLENDW_LAST
XED_IFORMFL_VPBROADCASTB_FIRST
XED_IFORMFL_VPBROADCASTB_LAST
XED_IFORMFL_VPBROADCASTD_FIRST
XED_IFORMFL_VPBROADCASTD_LAST
XED_IFORMFL_VPBROADCASTMB2Q_FIRST
XED_IFORMFL_VPBROADCASTMB2Q_LAST
XED_IFORMFL_VPBROADCASTMW2D_FIRST
XED_IFORMFL_VPBROADCASTMW2D_LAST
XED_IFORMFL_VPBROADCASTQ_FIRST
XED_IFORMFL_VPBROADCASTQ_LAST
XED_IFORMFL_VPBROADCASTW_FIRST
XED_IFORMFL_VPBROADCASTW_LAST
XED_IFORMFL_VPCLMULQDQ_FIRST
XED_IFORMFL_VPCLMULQDQ_LAST
XED_IFORMFL_VPCMOV_FIRST
XED_IFORMFL_VPCMOV_LAST
XED_IFORMFL_VPCMPB_FIRST
XED_IFORMFL_VPCMPB_LAST
XED_IFORMFL_VPCMPD_FIRST
XED_IFORMFL_VPCMPD_LAST
XED_IFORMFL_VPCMPEQB_FIRST
XED_IFORMFL_VPCMPEQB_LAST
XED_IFORMFL_VPCMPEQD_FIRST
XED_IFORMFL_VPCMPEQD_LAST
XED_IFORMFL_VPCMPEQQ_FIRST
XED_IFORMFL_VPCMPEQQ_LAST
XED_IFORMFL_VPCMPEQW_FIRST
XED_IFORMFL_VPCMPEQW_LAST
XED_IFORMFL_VPCMPESTRI64_FIRST
XED_IFORMFL_VPCMPESTRI64_LAST
XED_IFORMFL_VPCMPESTRI_FIRST
XED_IFORMFL_VPCMPESTRI_LAST
XED_IFORMFL_VPCMPESTRM64_FIRST
XED_IFORMFL_VPCMPESTRM64_LAST
XED_IFORMFL_VPCMPESTRM_FIRST
XED_IFORMFL_VPCMPESTRM_LAST
XED_IFORMFL_VPCMPGTB_FIRST
XED_IFORMFL_VPCMPGTB_LAST
XED_IFORMFL_VPCMPGTD_FIRST
XED_IFORMFL_VPCMPGTD_LAST
XED_IFORMFL_VPCMPGTQ_FIRST
XED_IFORMFL_VPCMPGTQ_LAST
XED_IFORMFL_VPCMPGTW_FIRST
XED_IFORMFL_VPCMPGTW_LAST
XED_IFORMFL_VPCMPISTRI64_FIRST
XED_IFORMFL_VPCMPISTRI64_LAST
XED_IFORMFL_VPCMPISTRI_FIRST
XED_IFORMFL_VPCMPISTRI_LAST
XED_IFORMFL_VPCMPISTRM_FIRST
XED_IFORMFL_VPCMPISTRM_LAST
XED_IFORMFL_VPCMPQ_FIRST
XED_IFORMFL_VPCMPQ_LAST
XED_IFORMFL_VPCMPUB_FIRST
XED_IFORMFL_VPCMPUB_LAST
XED_IFORMFL_VPCMPUD_FIRST
XED_IFORMFL_VPCMPUD_LAST
XED_IFORMFL_VPCMPUQ_FIRST
XED_IFORMFL_VPCMPUQ_LAST
XED_IFORMFL_VPCMPUW_FIRST
XED_IFORMFL_VPCMPUW_LAST
XED_IFORMFL_VPCMPW_FIRST
XED_IFORMFL_VPCMPW_LAST
XED_IFORMFL_VPCOMB_FIRST
XED_IFORMFL_VPCOMB_LAST
XED_IFORMFL_VPCOMD_FIRST
XED_IFORMFL_VPCOMD_LAST
XED_IFORMFL_VPCOMPRESSB_FIRST
XED_IFORMFL_VPCOMPRESSB_LAST
XED_IFORMFL_VPCOMPRESSD_FIRST
XED_IFORMFL_VPCOMPRESSD_LAST
XED_IFORMFL_VPCOMPRESSQ_FIRST
XED_IFORMFL_VPCOMPRESSQ_LAST
XED_IFORMFL_VPCOMPRESSW_FIRST
XED_IFORMFL_VPCOMPRESSW_LAST
XED_IFORMFL_VPCOMQ_FIRST
XED_IFORMFL_VPCOMQ_LAST
XED_IFORMFL_VPCOMUB_FIRST
XED_IFORMFL_VPCOMUB_LAST
XED_IFORMFL_VPCOMUD_FIRST
XED_IFORMFL_VPCOMUD_LAST
XED_IFORMFL_VPCOMUQ_FIRST
XED_IFORMFL_VPCOMUQ_LAST
XED_IFORMFL_VPCOMUW_FIRST
XED_IFORMFL_VPCOMUW_LAST
XED_IFORMFL_VPCOMW_FIRST
XED_IFORMFL_VPCOMW_LAST
XED_IFORMFL_VPCONFLICTD_FIRST
XED_IFORMFL_VPCONFLICTD_LAST
XED_IFORMFL_VPCONFLICTQ_FIRST
XED_IFORMFL_VPCONFLICTQ_LAST
XED_IFORMFL_VPDPBSSDS_FIRST
XED_IFORMFL_VPDPBSSDS_LAST
XED_IFORMFL_VPDPBSSD_FIRST
XED_IFORMFL_VPDPBSSD_LAST
XED_IFORMFL_VPDPBSUDS_FIRST
XED_IFORMFL_VPDPBSUDS_LAST
XED_IFORMFL_VPDPBSUD_FIRST
XED_IFORMFL_VPDPBSUD_LAST
XED_IFORMFL_VPDPBUSDS_FIRST
XED_IFORMFL_VPDPBUSDS_LAST
XED_IFORMFL_VPDPBUSD_FIRST
XED_IFORMFL_VPDPBUSD_LAST
XED_IFORMFL_VPDPBUUDS_FIRST
XED_IFORMFL_VPDPBUUDS_LAST
XED_IFORMFL_VPDPBUUD_FIRST
XED_IFORMFL_VPDPBUUD_LAST
XED_IFORMFL_VPDPWSSDS_FIRST
XED_IFORMFL_VPDPWSSDS_LAST
XED_IFORMFL_VPDPWSSD_FIRST
XED_IFORMFL_VPDPWSSD_LAST
XED_IFORMFL_VPDPWSUDS_FIRST
XED_IFORMFL_VPDPWSUDS_LAST
XED_IFORMFL_VPDPWSUD_FIRST
XED_IFORMFL_VPDPWSUD_LAST
XED_IFORMFL_VPDPWUSDS_FIRST
XED_IFORMFL_VPDPWUSDS_LAST
XED_IFORMFL_VPDPWUSD_FIRST
XED_IFORMFL_VPDPWUSD_LAST
XED_IFORMFL_VPDPWUUDS_FIRST
XED_IFORMFL_VPDPWUUDS_LAST
XED_IFORMFL_VPDPWUUD_FIRST
XED_IFORMFL_VPDPWUUD_LAST
XED_IFORMFL_VPERM2F128_FIRST
XED_IFORMFL_VPERM2F128_LAST
XED_IFORMFL_VPERM2I128_FIRST
XED_IFORMFL_VPERM2I128_LAST
XED_IFORMFL_VPERMB_FIRST
XED_IFORMFL_VPERMB_LAST
XED_IFORMFL_VPERMD_FIRST
XED_IFORMFL_VPERMD_LAST
XED_IFORMFL_VPERMI2B_FIRST
XED_IFORMFL_VPERMI2B_LAST
XED_IFORMFL_VPERMI2D_FIRST
XED_IFORMFL_VPERMI2D_LAST
XED_IFORMFL_VPERMI2PD_FIRST
XED_IFORMFL_VPERMI2PD_LAST
XED_IFORMFL_VPERMI2PS_FIRST
XED_IFORMFL_VPERMI2PS_LAST
XED_IFORMFL_VPERMI2Q_FIRST
XED_IFORMFL_VPERMI2Q_LAST
XED_IFORMFL_VPERMI2W_FIRST
XED_IFORMFL_VPERMI2W_LAST
XED_IFORMFL_VPERMIL2PD_FIRST
XED_IFORMFL_VPERMIL2PD_LAST
XED_IFORMFL_VPERMIL2PS_FIRST
XED_IFORMFL_VPERMIL2PS_LAST
XED_IFORMFL_VPERMILPD_FIRST
XED_IFORMFL_VPERMILPD_LAST
XED_IFORMFL_VPERMILPS_FIRST
XED_IFORMFL_VPERMILPS_LAST
XED_IFORMFL_VPERMPD_FIRST
XED_IFORMFL_VPERMPD_LAST
XED_IFORMFL_VPERMPS_FIRST
XED_IFORMFL_VPERMPS_LAST
XED_IFORMFL_VPERMQ_FIRST
XED_IFORMFL_VPERMQ_LAST
XED_IFORMFL_VPERMT2B_FIRST
XED_IFORMFL_VPERMT2B_LAST
XED_IFORMFL_VPERMT2D_FIRST
XED_IFORMFL_VPERMT2D_LAST
XED_IFORMFL_VPERMT2PD_FIRST
XED_IFORMFL_VPERMT2PD_LAST
XED_IFORMFL_VPERMT2PS_FIRST
XED_IFORMFL_VPERMT2PS_LAST
XED_IFORMFL_VPERMT2Q_FIRST
XED_IFORMFL_VPERMT2Q_LAST
XED_IFORMFL_VPERMT2W_FIRST
XED_IFORMFL_VPERMT2W_LAST
XED_IFORMFL_VPERMW_FIRST
XED_IFORMFL_VPERMW_LAST
XED_IFORMFL_VPEXPANDB_FIRST
XED_IFORMFL_VPEXPANDB_LAST
XED_IFORMFL_VPEXPANDD_FIRST
XED_IFORMFL_VPEXPANDD_LAST
XED_IFORMFL_VPEXPANDQ_FIRST
XED_IFORMFL_VPEXPANDQ_LAST
XED_IFORMFL_VPEXPANDW_FIRST
XED_IFORMFL_VPEXPANDW_LAST
XED_IFORMFL_VPEXTRB_FIRST
XED_IFORMFL_VPEXTRB_LAST
XED_IFORMFL_VPEXTRD_FIRST
XED_IFORMFL_VPEXTRD_LAST
XED_IFORMFL_VPEXTRQ_FIRST
XED_IFORMFL_VPEXTRQ_LAST
XED_IFORMFL_VPEXTRW_C5_FIRST
XED_IFORMFL_VPEXTRW_C5_LAST
XED_IFORMFL_VPEXTRW_FIRST
XED_IFORMFL_VPEXTRW_LAST
XED_IFORMFL_VPGATHERDD_FIRST
XED_IFORMFL_VPGATHERDD_LAST
XED_IFORMFL_VPGATHERDQ_FIRST
XED_IFORMFL_VPGATHERDQ_LAST
XED_IFORMFL_VPGATHERQD_FIRST
XED_IFORMFL_VPGATHERQD_LAST
XED_IFORMFL_VPGATHERQQ_FIRST
XED_IFORMFL_VPGATHERQQ_LAST
XED_IFORMFL_VPHADDBD_FIRST
XED_IFORMFL_VPHADDBD_LAST
XED_IFORMFL_VPHADDBQ_FIRST
XED_IFORMFL_VPHADDBQ_LAST
XED_IFORMFL_VPHADDBW_FIRST
XED_IFORMFL_VPHADDBW_LAST
XED_IFORMFL_VPHADDDQ_FIRST
XED_IFORMFL_VPHADDDQ_LAST
XED_IFORMFL_VPHADDD_FIRST
XED_IFORMFL_VPHADDD_LAST
XED_IFORMFL_VPHADDSW_FIRST
XED_IFORMFL_VPHADDSW_LAST
XED_IFORMFL_VPHADDUBD_FIRST
XED_IFORMFL_VPHADDUBD_LAST
XED_IFORMFL_VPHADDUBQ_FIRST
XED_IFORMFL_VPHADDUBQ_LAST
XED_IFORMFL_VPHADDUBW_FIRST
XED_IFORMFL_VPHADDUBW_LAST
XED_IFORMFL_VPHADDUDQ_FIRST
XED_IFORMFL_VPHADDUDQ_LAST
XED_IFORMFL_VPHADDUWD_FIRST
XED_IFORMFL_VPHADDUWD_LAST
XED_IFORMFL_VPHADDUWQ_FIRST
XED_IFORMFL_VPHADDUWQ_LAST
XED_IFORMFL_VPHADDWD_FIRST
XED_IFORMFL_VPHADDWD_LAST
XED_IFORMFL_VPHADDWQ_FIRST
XED_IFORMFL_VPHADDWQ_LAST
XED_IFORMFL_VPHADDW_FIRST
XED_IFORMFL_VPHADDW_LAST
XED_IFORMFL_VPHMINPOSUW_FIRST
XED_IFORMFL_VPHMINPOSUW_LAST
XED_IFORMFL_VPHSUBBW_FIRST
XED_IFORMFL_VPHSUBBW_LAST
XED_IFORMFL_VPHSUBDQ_FIRST
XED_IFORMFL_VPHSUBDQ_LAST
XED_IFORMFL_VPHSUBD_FIRST
XED_IFORMFL_VPHSUBD_LAST
XED_IFORMFL_VPHSUBSW_FIRST
XED_IFORMFL_VPHSUBSW_LAST
XED_IFORMFL_VPHSUBWD_FIRST
XED_IFORMFL_VPHSUBWD_LAST
XED_IFORMFL_VPHSUBW_FIRST
XED_IFORMFL_VPHSUBW_LAST
XED_IFORMFL_VPINSRB_FIRST
XED_IFORMFL_VPINSRB_LAST
XED_IFORMFL_VPINSRD_FIRST
XED_IFORMFL_VPINSRD_LAST
XED_IFORMFL_VPINSRQ_FIRST
XED_IFORMFL_VPINSRQ_LAST
XED_IFORMFL_VPINSRW_FIRST
XED_IFORMFL_VPINSRW_LAST
XED_IFORMFL_VPLZCNTD_FIRST
XED_IFORMFL_VPLZCNTD_LAST
XED_IFORMFL_VPLZCNTQ_FIRST
XED_IFORMFL_VPLZCNTQ_LAST
XED_IFORMFL_VPMACSDD_FIRST
XED_IFORMFL_VPMACSDD_LAST
XED_IFORMFL_VPMACSDQH_FIRST
XED_IFORMFL_VPMACSDQH_LAST
XED_IFORMFL_VPMACSDQL_FIRST
XED_IFORMFL_VPMACSDQL_LAST
XED_IFORMFL_VPMACSSDD_FIRST
XED_IFORMFL_VPMACSSDD_LAST
XED_IFORMFL_VPMACSSDQH_FIRST
XED_IFORMFL_VPMACSSDQH_LAST
XED_IFORMFL_VPMACSSDQL_FIRST
XED_IFORMFL_VPMACSSDQL_LAST
XED_IFORMFL_VPMACSSWD_FIRST
XED_IFORMFL_VPMACSSWD_LAST
XED_IFORMFL_VPMACSSWW_FIRST
XED_IFORMFL_VPMACSSWW_LAST
XED_IFORMFL_VPMACSWD_FIRST
XED_IFORMFL_VPMACSWD_LAST
XED_IFORMFL_VPMACSWW_FIRST
XED_IFORMFL_VPMACSWW_LAST
XED_IFORMFL_VPMADCSSWD_FIRST
XED_IFORMFL_VPMADCSSWD_LAST
XED_IFORMFL_VPMADCSWD_FIRST
XED_IFORMFL_VPMADCSWD_LAST
XED_IFORMFL_VPMADD52HUQ_FIRST
XED_IFORMFL_VPMADD52HUQ_LAST
XED_IFORMFL_VPMADD52LUQ_FIRST
XED_IFORMFL_VPMADD52LUQ_LAST
XED_IFORMFL_VPMADDUBSW_FIRST
XED_IFORMFL_VPMADDUBSW_LAST
XED_IFORMFL_VPMADDWD_FIRST
XED_IFORMFL_VPMADDWD_LAST
XED_IFORMFL_VPMASKMOVD_FIRST
XED_IFORMFL_VPMASKMOVD_LAST
XED_IFORMFL_VPMASKMOVQ_FIRST
XED_IFORMFL_VPMASKMOVQ_LAST
XED_IFORMFL_VPMAXSB_FIRST
XED_IFORMFL_VPMAXSB_LAST
XED_IFORMFL_VPMAXSD_FIRST
XED_IFORMFL_VPMAXSD_LAST
XED_IFORMFL_VPMAXSQ_FIRST
XED_IFORMFL_VPMAXSQ_LAST
XED_IFORMFL_VPMAXSW_FIRST
XED_IFORMFL_VPMAXSW_LAST
XED_IFORMFL_VPMAXUB_FIRST
XED_IFORMFL_VPMAXUB_LAST
XED_IFORMFL_VPMAXUD_FIRST
XED_IFORMFL_VPMAXUD_LAST
XED_IFORMFL_VPMAXUQ_FIRST
XED_IFORMFL_VPMAXUQ_LAST
XED_IFORMFL_VPMAXUW_FIRST
XED_IFORMFL_VPMAXUW_LAST
XED_IFORMFL_VPMINSB_FIRST
XED_IFORMFL_VPMINSB_LAST
XED_IFORMFL_VPMINSD_FIRST
XED_IFORMFL_VPMINSD_LAST
XED_IFORMFL_VPMINSQ_FIRST
XED_IFORMFL_VPMINSQ_LAST
XED_IFORMFL_VPMINSW_FIRST
XED_IFORMFL_VPMINSW_LAST
XED_IFORMFL_VPMINUB_FIRST
XED_IFORMFL_VPMINUB_LAST
XED_IFORMFL_VPMINUD_FIRST
XED_IFORMFL_VPMINUD_LAST
XED_IFORMFL_VPMINUQ_FIRST
XED_IFORMFL_VPMINUQ_LAST
XED_IFORMFL_VPMINUW_FIRST
XED_IFORMFL_VPMINUW_LAST
XED_IFORMFL_VPMOVB2M_FIRST
XED_IFORMFL_VPMOVB2M_LAST
XED_IFORMFL_VPMOVD2M_FIRST
XED_IFORMFL_VPMOVD2M_LAST
XED_IFORMFL_VPMOVDB_FIRST
XED_IFORMFL_VPMOVDB_LAST
XED_IFORMFL_VPMOVDW_FIRST
XED_IFORMFL_VPMOVDW_LAST
XED_IFORMFL_VPMOVM2B_FIRST
XED_IFORMFL_VPMOVM2B_LAST
XED_IFORMFL_VPMOVM2D_FIRST
XED_IFORMFL_VPMOVM2D_LAST
XED_IFORMFL_VPMOVM2Q_FIRST
XED_IFORMFL_VPMOVM2Q_LAST
XED_IFORMFL_VPMOVM2W_FIRST
XED_IFORMFL_VPMOVM2W_LAST
XED_IFORMFL_VPMOVMSKB_FIRST
XED_IFORMFL_VPMOVMSKB_LAST
XED_IFORMFL_VPMOVQ2M_FIRST
XED_IFORMFL_VPMOVQ2M_LAST
XED_IFORMFL_VPMOVQB_FIRST
XED_IFORMFL_VPMOVQB_LAST
XED_IFORMFL_VPMOVQD_FIRST
XED_IFORMFL_VPMOVQD_LAST
XED_IFORMFL_VPMOVQW_FIRST
XED_IFORMFL_VPMOVQW_LAST
XED_IFORMFL_VPMOVSDB_FIRST
XED_IFORMFL_VPMOVSDB_LAST
XED_IFORMFL_VPMOVSDW_FIRST
XED_IFORMFL_VPMOVSDW_LAST
XED_IFORMFL_VPMOVSQB_FIRST
XED_IFORMFL_VPMOVSQB_LAST
XED_IFORMFL_VPMOVSQD_FIRST
XED_IFORMFL_VPMOVSQD_LAST
XED_IFORMFL_VPMOVSQW_FIRST
XED_IFORMFL_VPMOVSQW_LAST
XED_IFORMFL_VPMOVSWB_FIRST
XED_IFORMFL_VPMOVSWB_LAST
XED_IFORMFL_VPMOVSXBD_FIRST
XED_IFORMFL_VPMOVSXBD_LAST
XED_IFORMFL_VPMOVSXBQ_FIRST
XED_IFORMFL_VPMOVSXBQ_LAST
XED_IFORMFL_VPMOVSXBW_FIRST
XED_IFORMFL_VPMOVSXBW_LAST
XED_IFORMFL_VPMOVSXDQ_FIRST
XED_IFORMFL_VPMOVSXDQ_LAST
XED_IFORMFL_VPMOVSXWD_FIRST
XED_IFORMFL_VPMOVSXWD_LAST
XED_IFORMFL_VPMOVSXWQ_FIRST
XED_IFORMFL_VPMOVSXWQ_LAST
XED_IFORMFL_VPMOVUSDB_FIRST
XED_IFORMFL_VPMOVUSDB_LAST
XED_IFORMFL_VPMOVUSDW_FIRST
XED_IFORMFL_VPMOVUSDW_LAST
XED_IFORMFL_VPMOVUSQB_FIRST
XED_IFORMFL_VPMOVUSQB_LAST
XED_IFORMFL_VPMOVUSQD_FIRST
XED_IFORMFL_VPMOVUSQD_LAST
XED_IFORMFL_VPMOVUSQW_FIRST
XED_IFORMFL_VPMOVUSQW_LAST
XED_IFORMFL_VPMOVUSWB_FIRST
XED_IFORMFL_VPMOVUSWB_LAST
XED_IFORMFL_VPMOVW2M_FIRST
XED_IFORMFL_VPMOVW2M_LAST
XED_IFORMFL_VPMOVWB_FIRST
XED_IFORMFL_VPMOVWB_LAST
XED_IFORMFL_VPMOVZXBD_FIRST
XED_IFORMFL_VPMOVZXBD_LAST
XED_IFORMFL_VPMOVZXBQ_FIRST
XED_IFORMFL_VPMOVZXBQ_LAST
XED_IFORMFL_VPMOVZXBW_FIRST
XED_IFORMFL_VPMOVZXBW_LAST
XED_IFORMFL_VPMOVZXDQ_FIRST
XED_IFORMFL_VPMOVZXDQ_LAST
XED_IFORMFL_VPMOVZXWD_FIRST
XED_IFORMFL_VPMOVZXWD_LAST
XED_IFORMFL_VPMOVZXWQ_FIRST
XED_IFORMFL_VPMOVZXWQ_LAST
XED_IFORMFL_VPMULDQ_FIRST
XED_IFORMFL_VPMULDQ_LAST
XED_IFORMFL_VPMULHRSW_FIRST
XED_IFORMFL_VPMULHRSW_LAST
XED_IFORMFL_VPMULHUW_FIRST
XED_IFORMFL_VPMULHUW_LAST
XED_IFORMFL_VPMULHW_FIRST
XED_IFORMFL_VPMULHW_LAST
XED_IFORMFL_VPMULLD_FIRST
XED_IFORMFL_VPMULLD_LAST
XED_IFORMFL_VPMULLQ_FIRST
XED_IFORMFL_VPMULLQ_LAST
XED_IFORMFL_VPMULLW_FIRST
XED_IFORMFL_VPMULLW_LAST
XED_IFORMFL_VPMULTISHIFTQB_FIRST
XED_IFORMFL_VPMULTISHIFTQB_LAST
XED_IFORMFL_VPMULUDQ_FIRST
XED_IFORMFL_VPMULUDQ_LAST
XED_IFORMFL_VPOPCNTB_FIRST
XED_IFORMFL_VPOPCNTB_LAST
XED_IFORMFL_VPOPCNTD_FIRST
XED_IFORMFL_VPOPCNTD_LAST
XED_IFORMFL_VPOPCNTQ_FIRST
XED_IFORMFL_VPOPCNTQ_LAST
XED_IFORMFL_VPOPCNTW_FIRST
XED_IFORMFL_VPOPCNTW_LAST
XED_IFORMFL_VPORD_FIRST
XED_IFORMFL_VPORD_LAST
XED_IFORMFL_VPORQ_FIRST
XED_IFORMFL_VPORQ_LAST
XED_IFORMFL_VPOR_FIRST
XED_IFORMFL_VPOR_LAST
XED_IFORMFL_VPPERM_FIRST
XED_IFORMFL_VPPERM_LAST
XED_IFORMFL_VPROLD_FIRST
XED_IFORMFL_VPROLD_LAST
XED_IFORMFL_VPROLQ_FIRST
XED_IFORMFL_VPROLQ_LAST
XED_IFORMFL_VPROLVD_FIRST
XED_IFORMFL_VPROLVD_LAST
XED_IFORMFL_VPROLVQ_FIRST
XED_IFORMFL_VPROLVQ_LAST
XED_IFORMFL_VPRORD_FIRST
XED_IFORMFL_VPRORD_LAST
XED_IFORMFL_VPRORQ_FIRST
XED_IFORMFL_VPRORQ_LAST
XED_IFORMFL_VPRORVD_FIRST
XED_IFORMFL_VPRORVD_LAST
XED_IFORMFL_VPRORVQ_FIRST
XED_IFORMFL_VPRORVQ_LAST
XED_IFORMFL_VPROTB_FIRST
XED_IFORMFL_VPROTB_LAST
XED_IFORMFL_VPROTD_FIRST
XED_IFORMFL_VPROTD_LAST
XED_IFORMFL_VPROTQ_FIRST
XED_IFORMFL_VPROTQ_LAST
XED_IFORMFL_VPROTW_FIRST
XED_IFORMFL_VPROTW_LAST
XED_IFORMFL_VPSADBW_FIRST
XED_IFORMFL_VPSADBW_LAST
XED_IFORMFL_VPSCATTERDD_FIRST
XED_IFORMFL_VPSCATTERDD_LAST
XED_IFORMFL_VPSCATTERDQ_FIRST
XED_IFORMFL_VPSCATTERDQ_LAST
XED_IFORMFL_VPSCATTERQD_FIRST
XED_IFORMFL_VPSCATTERQD_LAST
XED_IFORMFL_VPSCATTERQQ_FIRST
XED_IFORMFL_VPSCATTERQQ_LAST
XED_IFORMFL_VPSHAB_FIRST
XED_IFORMFL_VPSHAB_LAST
XED_IFORMFL_VPSHAD_FIRST
XED_IFORMFL_VPSHAD_LAST
XED_IFORMFL_VPSHAQ_FIRST
XED_IFORMFL_VPSHAQ_LAST
XED_IFORMFL_VPSHAW_FIRST
XED_IFORMFL_VPSHAW_LAST
XED_IFORMFL_VPSHLB_FIRST
XED_IFORMFL_VPSHLB_LAST
XED_IFORMFL_VPSHLDD_FIRST
XED_IFORMFL_VPSHLDD_LAST
XED_IFORMFL_VPSHLDQ_FIRST
XED_IFORMFL_VPSHLDQ_LAST
XED_IFORMFL_VPSHLDVD_FIRST
XED_IFORMFL_VPSHLDVD_LAST
XED_IFORMFL_VPSHLDVQ_FIRST
XED_IFORMFL_VPSHLDVQ_LAST
XED_IFORMFL_VPSHLDVW_FIRST
XED_IFORMFL_VPSHLDVW_LAST
XED_IFORMFL_VPSHLDW_FIRST
XED_IFORMFL_VPSHLDW_LAST
XED_IFORMFL_VPSHLD_FIRST
XED_IFORMFL_VPSHLD_LAST
XED_IFORMFL_VPSHLQ_FIRST
XED_IFORMFL_VPSHLQ_LAST
XED_IFORMFL_VPSHLW_FIRST
XED_IFORMFL_VPSHLW_LAST
XED_IFORMFL_VPSHRDD_FIRST
XED_IFORMFL_VPSHRDD_LAST
XED_IFORMFL_VPSHRDQ_FIRST
XED_IFORMFL_VPSHRDQ_LAST
XED_IFORMFL_VPSHRDVD_FIRST
XED_IFORMFL_VPSHRDVD_LAST
XED_IFORMFL_VPSHRDVQ_FIRST
XED_IFORMFL_VPSHRDVQ_LAST
XED_IFORMFL_VPSHRDVW_FIRST
XED_IFORMFL_VPSHRDVW_LAST
XED_IFORMFL_VPSHRDW_FIRST
XED_IFORMFL_VPSHRDW_LAST
XED_IFORMFL_VPSHUFBITQMB_FIRST
XED_IFORMFL_VPSHUFBITQMB_LAST
XED_IFORMFL_VPSHUFB_FIRST
XED_IFORMFL_VPSHUFB_LAST
XED_IFORMFL_VPSHUFD_FIRST
XED_IFORMFL_VPSHUFD_LAST
XED_IFORMFL_VPSHUFHW_FIRST
XED_IFORMFL_VPSHUFHW_LAST
XED_IFORMFL_VPSHUFLW_FIRST
XED_IFORMFL_VPSHUFLW_LAST
XED_IFORMFL_VPSIGNB_FIRST
XED_IFORMFL_VPSIGNB_LAST
XED_IFORMFL_VPSIGND_FIRST
XED_IFORMFL_VPSIGND_LAST
XED_IFORMFL_VPSIGNW_FIRST
XED_IFORMFL_VPSIGNW_LAST
XED_IFORMFL_VPSLLDQ_FIRST
XED_IFORMFL_VPSLLDQ_LAST
XED_IFORMFL_VPSLLD_FIRST
XED_IFORMFL_VPSLLD_LAST
XED_IFORMFL_VPSLLQ_FIRST
XED_IFORMFL_VPSLLQ_LAST
XED_IFORMFL_VPSLLVD_FIRST
XED_IFORMFL_VPSLLVD_LAST
XED_IFORMFL_VPSLLVQ_FIRST
XED_IFORMFL_VPSLLVQ_LAST
XED_IFORMFL_VPSLLVW_FIRST
XED_IFORMFL_VPSLLVW_LAST
XED_IFORMFL_VPSLLW_FIRST
XED_IFORMFL_VPSLLW_LAST
XED_IFORMFL_VPSRAD_FIRST
XED_IFORMFL_VPSRAD_LAST
XED_IFORMFL_VPSRAQ_FIRST
XED_IFORMFL_VPSRAQ_LAST
XED_IFORMFL_VPSRAVD_FIRST
XED_IFORMFL_VPSRAVD_LAST
XED_IFORMFL_VPSRAVQ_FIRST
XED_IFORMFL_VPSRAVQ_LAST
XED_IFORMFL_VPSRAVW_FIRST
XED_IFORMFL_VPSRAVW_LAST
XED_IFORMFL_VPSRAW_FIRST
XED_IFORMFL_VPSRAW_LAST
XED_IFORMFL_VPSRLDQ_FIRST
XED_IFORMFL_VPSRLDQ_LAST
XED_IFORMFL_VPSRLD_FIRST
XED_IFORMFL_VPSRLD_LAST
XED_IFORMFL_VPSRLQ_FIRST
XED_IFORMFL_VPSRLQ_LAST
XED_IFORMFL_VPSRLVD_FIRST
XED_IFORMFL_VPSRLVD_LAST
XED_IFORMFL_VPSRLVQ_FIRST
XED_IFORMFL_VPSRLVQ_LAST
XED_IFORMFL_VPSRLVW_FIRST
XED_IFORMFL_VPSRLVW_LAST
XED_IFORMFL_VPSRLW_FIRST
XED_IFORMFL_VPSRLW_LAST
XED_IFORMFL_VPSUBB_FIRST
XED_IFORMFL_VPSUBB_LAST
XED_IFORMFL_VPSUBD_FIRST
XED_IFORMFL_VPSUBD_LAST
XED_IFORMFL_VPSUBQ_FIRST
XED_IFORMFL_VPSUBQ_LAST
XED_IFORMFL_VPSUBSB_FIRST
XED_IFORMFL_VPSUBSB_LAST
XED_IFORMFL_VPSUBSW_FIRST
XED_IFORMFL_VPSUBSW_LAST
XED_IFORMFL_VPSUBUSB_FIRST
XED_IFORMFL_VPSUBUSB_LAST
XED_IFORMFL_VPSUBUSW_FIRST
XED_IFORMFL_VPSUBUSW_LAST
XED_IFORMFL_VPSUBW_FIRST
XED_IFORMFL_VPSUBW_LAST
XED_IFORMFL_VPTERNLOGD_FIRST
XED_IFORMFL_VPTERNLOGD_LAST
XED_IFORMFL_VPTERNLOGQ_FIRST
XED_IFORMFL_VPTERNLOGQ_LAST
XED_IFORMFL_VPTESTMB_FIRST
XED_IFORMFL_VPTESTMB_LAST
XED_IFORMFL_VPTESTMD_FIRST
XED_IFORMFL_VPTESTMD_LAST
XED_IFORMFL_VPTESTMQ_FIRST
XED_IFORMFL_VPTESTMQ_LAST
XED_IFORMFL_VPTESTMW_FIRST
XED_IFORMFL_VPTESTMW_LAST
XED_IFORMFL_VPTESTNMB_FIRST
XED_IFORMFL_VPTESTNMB_LAST
XED_IFORMFL_VPTESTNMD_FIRST
XED_IFORMFL_VPTESTNMD_LAST
XED_IFORMFL_VPTESTNMQ_FIRST
XED_IFORMFL_VPTESTNMQ_LAST
XED_IFORMFL_VPTESTNMW_FIRST
XED_IFORMFL_VPTESTNMW_LAST
XED_IFORMFL_VPTEST_FIRST
XED_IFORMFL_VPTEST_LAST
XED_IFORMFL_VPUNPCKHBW_FIRST
XED_IFORMFL_VPUNPCKHBW_LAST
XED_IFORMFL_VPUNPCKHDQ_FIRST
XED_IFORMFL_VPUNPCKHDQ_LAST
XED_IFORMFL_VPUNPCKHQDQ_FIRST
XED_IFORMFL_VPUNPCKHQDQ_LAST
XED_IFORMFL_VPUNPCKHWD_FIRST
XED_IFORMFL_VPUNPCKHWD_LAST
XED_IFORMFL_VPUNPCKLBW_FIRST
XED_IFORMFL_VPUNPCKLBW_LAST
XED_IFORMFL_VPUNPCKLDQ_FIRST
XED_IFORMFL_VPUNPCKLDQ_LAST
XED_IFORMFL_VPUNPCKLQDQ_FIRST
XED_IFORMFL_VPUNPCKLQDQ_LAST
XED_IFORMFL_VPUNPCKLWD_FIRST
XED_IFORMFL_VPUNPCKLWD_LAST
XED_IFORMFL_VPXORD_FIRST
XED_IFORMFL_VPXORD_LAST
XED_IFORMFL_VPXORQ_FIRST
XED_IFORMFL_VPXORQ_LAST
XED_IFORMFL_VPXOR_FIRST
XED_IFORMFL_VPXOR_LAST
XED_IFORMFL_VRANGEPD_FIRST
XED_IFORMFL_VRANGEPD_LAST
XED_IFORMFL_VRANGEPS_FIRST
XED_IFORMFL_VRANGEPS_LAST
XED_IFORMFL_VRANGESD_FIRST
XED_IFORMFL_VRANGESD_LAST
XED_IFORMFL_VRANGESS_FIRST
XED_IFORMFL_VRANGESS_LAST
XED_IFORMFL_VRCP14PD_FIRST
XED_IFORMFL_VRCP14PD_LAST
XED_IFORMFL_VRCP14PS_FIRST
XED_IFORMFL_VRCP14PS_LAST
XED_IFORMFL_VRCP14SD_FIRST
XED_IFORMFL_VRCP14SD_LAST
XED_IFORMFL_VRCP14SS_FIRST
XED_IFORMFL_VRCP14SS_LAST
XED_IFORMFL_VRCP28PD_FIRST
XED_IFORMFL_VRCP28PD_LAST
XED_IFORMFL_VRCP28PS_FIRST
XED_IFORMFL_VRCP28PS_LAST
XED_IFORMFL_VRCP28SD_FIRST
XED_IFORMFL_VRCP28SD_LAST
XED_IFORMFL_VRCP28SS_FIRST
XED_IFORMFL_VRCP28SS_LAST
XED_IFORMFL_VRCPPH_FIRST
XED_IFORMFL_VRCPPH_LAST
XED_IFORMFL_VRCPPS_FIRST
XED_IFORMFL_VRCPPS_LAST
XED_IFORMFL_VRCPSH_FIRST
XED_IFORMFL_VRCPSH_LAST
XED_IFORMFL_VRCPSS_FIRST
XED_IFORMFL_VRCPSS_LAST
XED_IFORMFL_VREDUCEPD_FIRST
XED_IFORMFL_VREDUCEPD_LAST
XED_IFORMFL_VREDUCEPH_FIRST
XED_IFORMFL_VREDUCEPH_LAST
XED_IFORMFL_VREDUCEPS_FIRST
XED_IFORMFL_VREDUCEPS_LAST
XED_IFORMFL_VREDUCESD_FIRST
XED_IFORMFL_VREDUCESD_LAST
XED_IFORMFL_VREDUCESH_FIRST
XED_IFORMFL_VREDUCESH_LAST
XED_IFORMFL_VREDUCESS_FIRST
XED_IFORMFL_VREDUCESS_LAST
XED_IFORMFL_VRNDSCALEPD_FIRST
XED_IFORMFL_VRNDSCALEPD_LAST
XED_IFORMFL_VRNDSCALEPH_FIRST
XED_IFORMFL_VRNDSCALEPH_LAST
XED_IFORMFL_VRNDSCALEPS_FIRST
XED_IFORMFL_VRNDSCALEPS_LAST
XED_IFORMFL_VRNDSCALESD_FIRST
XED_IFORMFL_VRNDSCALESD_LAST
XED_IFORMFL_VRNDSCALESH_FIRST
XED_IFORMFL_VRNDSCALESH_LAST
XED_IFORMFL_VRNDSCALESS_FIRST
XED_IFORMFL_VRNDSCALESS_LAST
XED_IFORMFL_VROUNDPD_FIRST
XED_IFORMFL_VROUNDPD_LAST
XED_IFORMFL_VROUNDPS_FIRST
XED_IFORMFL_VROUNDPS_LAST
XED_IFORMFL_VROUNDSD_FIRST
XED_IFORMFL_VROUNDSD_LAST
XED_IFORMFL_VROUNDSS_FIRST
XED_IFORMFL_VROUNDSS_LAST
XED_IFORMFL_VRSQRT14PD_FIRST
XED_IFORMFL_VRSQRT14PD_LAST
XED_IFORMFL_VRSQRT14PS_FIRST
XED_IFORMFL_VRSQRT14PS_LAST
XED_IFORMFL_VRSQRT14SD_FIRST
XED_IFORMFL_VRSQRT14SD_LAST
XED_IFORMFL_VRSQRT14SS_FIRST
XED_IFORMFL_VRSQRT14SS_LAST
XED_IFORMFL_VRSQRT28PD_FIRST
XED_IFORMFL_VRSQRT28PD_LAST
XED_IFORMFL_VRSQRT28PS_FIRST
XED_IFORMFL_VRSQRT28PS_LAST
XED_IFORMFL_VRSQRT28SD_FIRST
XED_IFORMFL_VRSQRT28SD_LAST
XED_IFORMFL_VRSQRT28SS_FIRST
XED_IFORMFL_VRSQRT28SS_LAST
XED_IFORMFL_VRSQRTPH_FIRST
XED_IFORMFL_VRSQRTPH_LAST
XED_IFORMFL_VRSQRTPS_FIRST
XED_IFORMFL_VRSQRTPS_LAST
XED_IFORMFL_VRSQRTSH_FIRST
XED_IFORMFL_VRSQRTSH_LAST
XED_IFORMFL_VRSQRTSS_FIRST
XED_IFORMFL_VRSQRTSS_LAST
XED_IFORMFL_VSCALEFPD_FIRST
XED_IFORMFL_VSCALEFPD_LAST
XED_IFORMFL_VSCALEFPH_FIRST
XED_IFORMFL_VSCALEFPH_LAST
XED_IFORMFL_VSCALEFPS_FIRST
XED_IFORMFL_VSCALEFPS_LAST
XED_IFORMFL_VSCALEFSD_FIRST
XED_IFORMFL_VSCALEFSD_LAST
XED_IFORMFL_VSCALEFSH_FIRST
XED_IFORMFL_VSCALEFSH_LAST
XED_IFORMFL_VSCALEFSS_FIRST
XED_IFORMFL_VSCALEFSS_LAST
XED_IFORMFL_VSCATTERDPD_FIRST
XED_IFORMFL_VSCATTERDPD_LAST
XED_IFORMFL_VSCATTERDPS_FIRST
XED_IFORMFL_VSCATTERDPS_LAST
XED_IFORMFL_VSCATTERPF0DPD_FIRST
XED_IFORMFL_VSCATTERPF0DPD_LAST
XED_IFORMFL_VSCATTERPF0DPS_FIRST
XED_IFORMFL_VSCATTERPF0DPS_LAST
XED_IFORMFL_VSCATTERPF0QPD_FIRST
XED_IFORMFL_VSCATTERPF0QPD_LAST
XED_IFORMFL_VSCATTERPF0QPS_FIRST
XED_IFORMFL_VSCATTERPF0QPS_LAST
XED_IFORMFL_VSCATTERPF1DPD_FIRST
XED_IFORMFL_VSCATTERPF1DPD_LAST
XED_IFORMFL_VSCATTERPF1DPS_FIRST
XED_IFORMFL_VSCATTERPF1DPS_LAST
XED_IFORMFL_VSCATTERPF1QPD_FIRST
XED_IFORMFL_VSCATTERPF1QPD_LAST
XED_IFORMFL_VSCATTERPF1QPS_FIRST
XED_IFORMFL_VSCATTERPF1QPS_LAST
XED_IFORMFL_VSCATTERQPD_FIRST
XED_IFORMFL_VSCATTERQPD_LAST
XED_IFORMFL_VSCATTERQPS_FIRST
XED_IFORMFL_VSCATTERQPS_LAST
XED_IFORMFL_VSHA512MSG1_FIRST
XED_IFORMFL_VSHA512MSG1_LAST
XED_IFORMFL_VSHA512MSG2_FIRST
XED_IFORMFL_VSHA512MSG2_LAST
XED_IFORMFL_VSHA512RNDS2_FIRST
XED_IFORMFL_VSHA512RNDS2_LAST
XED_IFORMFL_VSHUFF32X4_FIRST
XED_IFORMFL_VSHUFF32X4_LAST
XED_IFORMFL_VSHUFF64X2_FIRST
XED_IFORMFL_VSHUFF64X2_LAST
XED_IFORMFL_VSHUFI32X4_FIRST
XED_IFORMFL_VSHUFI32X4_LAST
XED_IFORMFL_VSHUFI64X2_FIRST
XED_IFORMFL_VSHUFI64X2_LAST
XED_IFORMFL_VSHUFPD_FIRST
XED_IFORMFL_VSHUFPD_LAST
XED_IFORMFL_VSHUFPS_FIRST
XED_IFORMFL_VSHUFPS_LAST
XED_IFORMFL_VSM3MSG1_FIRST
XED_IFORMFL_VSM3MSG1_LAST
XED_IFORMFL_VSM3MSG2_FIRST
XED_IFORMFL_VSM3MSG2_LAST
XED_IFORMFL_VSM3RNDS2_FIRST
XED_IFORMFL_VSM3RNDS2_LAST
XED_IFORMFL_VSM4KEY4_FIRST
XED_IFORMFL_VSM4KEY4_LAST
XED_IFORMFL_VSM4RNDS4_FIRST
XED_IFORMFL_VSM4RNDS4_LAST
XED_IFORMFL_VSQRTPD_FIRST
XED_IFORMFL_VSQRTPD_LAST
XED_IFORMFL_VSQRTPH_FIRST
XED_IFORMFL_VSQRTPH_LAST
XED_IFORMFL_VSQRTPS_FIRST
XED_IFORMFL_VSQRTPS_LAST
XED_IFORMFL_VSQRTSD_FIRST
XED_IFORMFL_VSQRTSD_LAST
XED_IFORMFL_VSQRTSH_FIRST
XED_IFORMFL_VSQRTSH_LAST
XED_IFORMFL_VSQRTSS_FIRST
XED_IFORMFL_VSQRTSS_LAST
XED_IFORMFL_VSTMXCSR_FIRST
XED_IFORMFL_VSTMXCSR_LAST
XED_IFORMFL_VSUBPD_FIRST
XED_IFORMFL_VSUBPD_LAST
XED_IFORMFL_VSUBPH_FIRST
XED_IFORMFL_VSUBPH_LAST
XED_IFORMFL_VSUBPS_FIRST
XED_IFORMFL_VSUBPS_LAST
XED_IFORMFL_VSUBSD_FIRST
XED_IFORMFL_VSUBSD_LAST
XED_IFORMFL_VSUBSH_FIRST
XED_IFORMFL_VSUBSH_LAST
XED_IFORMFL_VSUBSS_FIRST
XED_IFORMFL_VSUBSS_LAST
XED_IFORMFL_VTESTPD_FIRST
XED_IFORMFL_VTESTPD_LAST
XED_IFORMFL_VTESTPS_FIRST
XED_IFORMFL_VTESTPS_LAST
XED_IFORMFL_VUCOMISD_FIRST
XED_IFORMFL_VUCOMISD_LAST
XED_IFORMFL_VUCOMISH_FIRST
XED_IFORMFL_VUCOMISH_LAST
XED_IFORMFL_VUCOMISS_FIRST
XED_IFORMFL_VUCOMISS_LAST
XED_IFORMFL_VUNPCKHPD_FIRST
XED_IFORMFL_VUNPCKHPD_LAST
XED_IFORMFL_VUNPCKHPS_FIRST
XED_IFORMFL_VUNPCKHPS_LAST
XED_IFORMFL_VUNPCKLPD_FIRST
XED_IFORMFL_VUNPCKLPD_LAST
XED_IFORMFL_VUNPCKLPS_FIRST
XED_IFORMFL_VUNPCKLPS_LAST
XED_IFORMFL_VXORPD_FIRST
XED_IFORMFL_VXORPD_LAST
XED_IFORMFL_VXORPS_FIRST
XED_IFORMFL_VXORPS_LAST
XED_IFORMFL_VZEROALL_FIRST
XED_IFORMFL_VZEROALL_LAST
XED_IFORMFL_VZEROUPPER_FIRST
XED_IFORMFL_VZEROUPPER_LAST
XED_IFORMFL_WBINVD_FIRST
XED_IFORMFL_WBINVD_LAST
XED_IFORMFL_WBNOINVD_FIRST
XED_IFORMFL_WBNOINVD_LAST
XED_IFORMFL_WRFSBASE_FIRST
XED_IFORMFL_WRFSBASE_LAST
XED_IFORMFL_WRGSBASE_FIRST
XED_IFORMFL_WRGSBASE_LAST
XED_IFORMFL_WRMSRLIST_FIRST
XED_IFORMFL_WRMSRLIST_LAST
XED_IFORMFL_WRMSRNS_FIRST
XED_IFORMFL_WRMSRNS_LAST
XED_IFORMFL_WRMSR_FIRST
XED_IFORMFL_WRMSR_LAST
XED_IFORMFL_WRPKRU_FIRST
XED_IFORMFL_WRPKRU_LAST
XED_IFORMFL_WRSSD_FIRST
XED_IFORMFL_WRSSD_LAST
XED_IFORMFL_WRSSQ_FIRST
XED_IFORMFL_WRSSQ_LAST
XED_IFORMFL_WRUSSD_FIRST
XED_IFORMFL_WRUSSD_LAST
XED_IFORMFL_WRUSSQ_FIRST
XED_IFORMFL_WRUSSQ_LAST
XED_IFORMFL_XABORT_FIRST
XED_IFORMFL_XABORT_LAST
XED_IFORMFL_XADD_FIRST
XED_IFORMFL_XADD_LAST
XED_IFORMFL_XADD_LOCK_FIRST
XED_IFORMFL_XADD_LOCK_LAST
XED_IFORMFL_XBEGIN_FIRST
XED_IFORMFL_XBEGIN_LAST
XED_IFORMFL_XCHG_FIRST
XED_IFORMFL_XCHG_LAST
XED_IFORMFL_XEND_FIRST
XED_IFORMFL_XEND_LAST
XED_IFORMFL_XGETBV_FIRST
XED_IFORMFL_XGETBV_LAST
XED_IFORMFL_XLAT_FIRST
XED_IFORMFL_XLAT_LAST
XED_IFORMFL_XORPD_FIRST
XED_IFORMFL_XORPD_LAST
XED_IFORMFL_XORPS_FIRST
XED_IFORMFL_XORPS_LAST
XED_IFORMFL_XOR_FIRST
XED_IFORMFL_XOR_LAST
XED_IFORMFL_XOR_LOCK_FIRST
XED_IFORMFL_XOR_LOCK_LAST
XED_IFORMFL_XRESLDTRK_FIRST
XED_IFORMFL_XRESLDTRK_LAST
XED_IFORMFL_XRSTOR64_FIRST
XED_IFORMFL_XRSTOR64_LAST
XED_IFORMFL_XRSTORS64_FIRST
XED_IFORMFL_XRSTORS64_LAST
XED_IFORMFL_XRSTORS_FIRST
XED_IFORMFL_XRSTORS_LAST
XED_IFORMFL_XRSTOR_FIRST
XED_IFORMFL_XRSTOR_LAST
XED_IFORMFL_XSAVE64_FIRST
XED_IFORMFL_XSAVE64_LAST
XED_IFORMFL_XSAVEC64_FIRST
XED_IFORMFL_XSAVEC64_LAST
XED_IFORMFL_XSAVEC_FIRST
XED_IFORMFL_XSAVEC_LAST
XED_IFORMFL_XSAVEOPT64_FIRST
XED_IFORMFL_XSAVEOPT64_LAST
XED_IFORMFL_XSAVEOPT_FIRST
XED_IFORMFL_XSAVEOPT_LAST
XED_IFORMFL_XSAVES64_FIRST
XED_IFORMFL_XSAVES64_LAST
XED_IFORMFL_XSAVES_FIRST
XED_IFORMFL_XSAVES_LAST
XED_IFORMFL_XSAVE_FIRST
XED_IFORMFL_XSAVE_LAST
XED_IFORMFL_XSETBV_FIRST
XED_IFORMFL_XSETBV_LAST
XED_IFORMFL_XSTORE_FIRST
XED_IFORMFL_XSTORE_LAST
XED_IFORMFL_XSUSLDTRK_FIRST
XED_IFORMFL_XSUSLDTRK_LAST
XED_IFORMFL_XTEST_FIRST
XED_IFORMFL_XTEST_LAST
XED_IFORM_AAA
XED_IFORM_AADD_MEM32_GPR32
XED_IFORM_AADD_MEM64_GPR64
XED_IFORM_AADD_MEMi32_GPR32i32_APX
XED_IFORM_AADD_MEMi64_GPR64i64_APX
XED_IFORM_AAD_IMMb
XED_IFORM_AAM_IMMb
XED_IFORM_AAND_MEM32_GPR32
XED_IFORM_AAND_MEM64_GPR64
XED_IFORM_AAND_MEMi32_GPR32i32_APX
XED_IFORM_AAND_MEMi64_GPR64i64_APX
XED_IFORM_AAS
XED_IFORM_ADCX_GPR32d_GPR32d
XED_IFORM_ADCX_GPR32d_MEMd
XED_IFORM_ADCX_GPR32i32_GPR32i32_APX
XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_ADCX_GPR32i32_MEMi32_APX
XED_IFORM_ADCX_GPR64i64_GPR64i64_APX
XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_ADCX_GPR64i64_MEMi64_APX
XED_IFORM_ADCX_GPR64q_GPR64q
XED_IFORM_ADCX_GPR64q_MEMq
XED_IFORM_ADC_AL_IMMb
XED_IFORM_ADC_GPR8_GPR8_10
XED_IFORM_ADC_GPR8_GPR8_12
XED_IFORM_ADC_GPR8_IMMb_80r2
XED_IFORM_ADC_GPR8_IMMb_82r2
XED_IFORM_ADC_GPR8_MEMb
XED_IFORM_ADC_GPR8i8_GPR8i8_APX
XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_ADC_GPR8i8_IMM8_APX
XED_IFORM_ADC_GPR8i8_MEMi8_APX
XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_ADC_GPRv_GPRv_11
XED_IFORM_ADC_GPRv_GPRv_13
XED_IFORM_ADC_GPRv_GPRv_APX
XED_IFORM_ADC_GPRv_GPRv_GPRv_APX
XED_IFORM_ADC_GPRv_GPRv_IMM8_APX
XED_IFORM_ADC_GPRv_GPRv_IMMz_APX
XED_IFORM_ADC_GPRv_GPRv_MEMv_APX
XED_IFORM_ADC_GPRv_IMM8_APX
XED_IFORM_ADC_GPRv_IMMb
XED_IFORM_ADC_GPRv_IMMz
XED_IFORM_ADC_GPRv_IMMz_APX
XED_IFORM_ADC_GPRv_MEMv
XED_IFORM_ADC_GPRv_MEMv_APX
XED_IFORM_ADC_GPRv_MEMv_GPRv_APX
XED_IFORM_ADC_GPRv_MEMv_IMM8_APX
XED_IFORM_ADC_GPRv_MEMv_IMMz_APX
XED_IFORM_ADC_LOCK_MEMb_GPR8
XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2
XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2
XED_IFORM_ADC_LOCK_MEMv_GPRv
XED_IFORM_ADC_LOCK_MEMv_IMMb
XED_IFORM_ADC_LOCK_MEMv_IMMz
XED_IFORM_ADC_MEMb_GPR8
XED_IFORM_ADC_MEMb_IMMb_80r2
XED_IFORM_ADC_MEMb_IMMb_82r2
XED_IFORM_ADC_MEMi8_GPR8i8_APX
XED_IFORM_ADC_MEMi8_IMM8_APX
XED_IFORM_ADC_MEMv_GPRv
XED_IFORM_ADC_MEMv_GPRv_APX
XED_IFORM_ADC_MEMv_IMM8_APX
XED_IFORM_ADC_MEMv_IMMb
XED_IFORM_ADC_MEMv_IMMz
XED_IFORM_ADC_MEMv_IMMz_APX
XED_IFORM_ADC_OrAX_IMMz
XED_IFORM_ADDPD_XMMpd_MEMpd
XED_IFORM_ADDPD_XMMpd_XMMpd
XED_IFORM_ADDPS_XMMps_MEMps
XED_IFORM_ADDPS_XMMps_XMMps
XED_IFORM_ADDSD_XMMsd_MEMsd
XED_IFORM_ADDSD_XMMsd_XMMsd
XED_IFORM_ADDSS_XMMss_MEMss
XED_IFORM_ADDSS_XMMss_XMMss
XED_IFORM_ADDSUBPD_XMMpd_MEMpd
XED_IFORM_ADDSUBPD_XMMpd_XMMpd
XED_IFORM_ADDSUBPS_XMMps_MEMps
XED_IFORM_ADDSUBPS_XMMps_XMMps
XED_IFORM_ADD_AL_IMMb
XED_IFORM_ADD_GPR8_GPR8_00
XED_IFORM_ADD_GPR8_GPR8_02
XED_IFORM_ADD_GPR8_IMMb_80r0
XED_IFORM_ADD_GPR8_IMMb_82r0
XED_IFORM_ADD_GPR8_MEMb
XED_IFORM_ADD_GPR8i8_GPR8i8_APX
XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_ADD_GPR8i8_IMM8_APX
XED_IFORM_ADD_GPR8i8_MEMi8_APX
XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_ADD_GPRv_GPRv_01
XED_IFORM_ADD_GPRv_GPRv_03
XED_IFORM_ADD_GPRv_GPRv_APX
XED_IFORM_ADD_GPRv_GPRv_GPRv_APX
XED_IFORM_ADD_GPRv_GPRv_IMM8_APX
XED_IFORM_ADD_GPRv_GPRv_IMMz_APX
XED_IFORM_ADD_GPRv_GPRv_MEMv_APX
XED_IFORM_ADD_GPRv_IMM8_APX
XED_IFORM_ADD_GPRv_IMMb
XED_IFORM_ADD_GPRv_IMMz
XED_IFORM_ADD_GPRv_IMMz_APX
XED_IFORM_ADD_GPRv_MEMv
XED_IFORM_ADD_GPRv_MEMv_APX
XED_IFORM_ADD_GPRv_MEMv_GPRv_APX
XED_IFORM_ADD_GPRv_MEMv_IMM8_APX
XED_IFORM_ADD_GPRv_MEMv_IMMz_APX
XED_IFORM_ADD_LOCK_MEMb_GPR8
XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0
XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0
XED_IFORM_ADD_LOCK_MEMv_GPRv
XED_IFORM_ADD_LOCK_MEMv_IMMb
XED_IFORM_ADD_LOCK_MEMv_IMMz
XED_IFORM_ADD_MEMb_GPR8
XED_IFORM_ADD_MEMb_IMMb_80r0
XED_IFORM_ADD_MEMb_IMMb_82r0
XED_IFORM_ADD_MEMi8_GPR8i8_APX
XED_IFORM_ADD_MEMi8_IMM8_APX
XED_IFORM_ADD_MEMv_GPRv
XED_IFORM_ADD_MEMv_GPRv_APX
XED_IFORM_ADD_MEMv_IMM8_APX
XED_IFORM_ADD_MEMv_IMMb
XED_IFORM_ADD_MEMv_IMMz
XED_IFORM_ADD_MEMv_IMMz_APX
XED_IFORM_ADD_OrAX_IMMz
XED_IFORM_ADOX_GPR32d_GPR32d
XED_IFORM_ADOX_GPR32d_MEMd
XED_IFORM_ADOX_GPR32i32_GPR32i32_APX
XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_ADOX_GPR32i32_MEMi32_APX
XED_IFORM_ADOX_GPR64i64_GPR64i64_APX
XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_ADOX_GPR64i64_MEMi64_APX
XED_IFORM_ADOX_GPR64q_GPR64q
XED_IFORM_ADOX_GPR64q_MEMq
XED_IFORM_AESDEC128KL_XMMu8_MEMu8
XED_IFORM_AESDEC256KL_XMMu8_MEMu8
XED_IFORM_AESDECLAST_XMMdq_MEMdq
XED_IFORM_AESDECLAST_XMMdq_XMMdq
XED_IFORM_AESDECWIDE128KL_MEMu8
XED_IFORM_AESDECWIDE256KL_MEMu8
XED_IFORM_AESDEC_XMMdq_MEMdq
XED_IFORM_AESDEC_XMMdq_XMMdq
XED_IFORM_AESENC128KL_XMMu8_MEMu8
XED_IFORM_AESENC256KL_XMMu8_MEMu8
XED_IFORM_AESENCLAST_XMMdq_MEMdq
XED_IFORM_AESENCLAST_XMMdq_XMMdq
XED_IFORM_AESENCWIDE128KL_MEMu8
XED_IFORM_AESENCWIDE256KL_MEMu8
XED_IFORM_AESENC_XMMdq_MEMdq
XED_IFORM_AESENC_XMMdq_XMMdq
XED_IFORM_AESIMC_XMMdq_MEMdq
XED_IFORM_AESIMC_XMMdq_XMMdq
XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb
XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb
XED_IFORM_ANDNPD_XMMxuq_MEMxuq
XED_IFORM_ANDNPD_XMMxuq_XMMxuq
XED_IFORM_ANDNPS_XMMxud_MEMxud
XED_IFORM_ANDNPS_XMMxud_XMMxud
XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d
XED_IFORM_ANDN_GPR32d_GPR32d_MEMd
XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q
XED_IFORM_ANDN_GPR64q_GPR64q_MEMq
XED_IFORM_ANDPD_XMMxuq_MEMxuq
XED_IFORM_ANDPD_XMMxuq_XMMxuq
XED_IFORM_ANDPS_XMMxud_MEMxud
XED_IFORM_ANDPS_XMMxud_XMMxud
XED_IFORM_AND_AL_IMMb
XED_IFORM_AND_GPR8_GPR8_20
XED_IFORM_AND_GPR8_GPR8_22
XED_IFORM_AND_GPR8_IMMb_80r4
XED_IFORM_AND_GPR8_IMMb_82r4
XED_IFORM_AND_GPR8_MEMb
XED_IFORM_AND_GPR8i8_GPR8i8_APX
XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_AND_GPR8i8_IMM8_APX
XED_IFORM_AND_GPR8i8_MEMi8_APX
XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_AND_GPRv_GPRv_21
XED_IFORM_AND_GPRv_GPRv_23
XED_IFORM_AND_GPRv_GPRv_APX
XED_IFORM_AND_GPRv_GPRv_GPRv_APX
XED_IFORM_AND_GPRv_GPRv_IMM8_APX
XED_IFORM_AND_GPRv_GPRv_IMMz_APX
XED_IFORM_AND_GPRv_GPRv_MEMv_APX
XED_IFORM_AND_GPRv_IMM8_APX
XED_IFORM_AND_GPRv_IMMb
XED_IFORM_AND_GPRv_IMMz
XED_IFORM_AND_GPRv_IMMz_APX
XED_IFORM_AND_GPRv_MEMv
XED_IFORM_AND_GPRv_MEMv_APX
XED_IFORM_AND_GPRv_MEMv_GPRv_APX
XED_IFORM_AND_GPRv_MEMv_IMM8_APX
XED_IFORM_AND_GPRv_MEMv_IMMz_APX
XED_IFORM_AND_LOCK_MEMb_GPR8
XED_IFORM_AND_LOCK_MEMb_IMMb_80r4
XED_IFORM_AND_LOCK_MEMb_IMMb_82r4
XED_IFORM_AND_LOCK_MEMv_GPRv
XED_IFORM_AND_LOCK_MEMv_IMMb
XED_IFORM_AND_LOCK_MEMv_IMMz
XED_IFORM_AND_MEMb_GPR8
XED_IFORM_AND_MEMb_IMMb_80r4
XED_IFORM_AND_MEMb_IMMb_82r4
XED_IFORM_AND_MEMi8_GPR8i8_APX
XED_IFORM_AND_MEMi8_IMM8_APX
XED_IFORM_AND_MEMv_GPRv
XED_IFORM_AND_MEMv_GPRv_APX
XED_IFORM_AND_MEMv_IMM8_APX
XED_IFORM_AND_MEMv_IMMb
XED_IFORM_AND_MEMv_IMMz
XED_IFORM_AND_MEMv_IMMz_APX
XED_IFORM_AND_OrAX_IMMz
XED_IFORM_AOR_MEM32_GPR32
XED_IFORM_AOR_MEM64_GPR64
XED_IFORM_AOR_MEMi32_GPR32i32_APX
XED_IFORM_AOR_MEMi64_GPR64i64_APX
XED_IFORM_ARPL_GPR16_GPR16
XED_IFORM_ARPL_MEMw_GPR16
XED_IFORM_AXOR_MEM32_GPR32
XED_IFORM_AXOR_MEM64_GPR64
XED_IFORM_AXOR_MEMi32_GPR32i32_APX
XED_IFORM_AXOR_MEMi64_GPR64i64_APX
XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d
XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d
XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX
XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX
XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q
XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q
XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd
XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd
XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd
XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd
XED_IFORM_BLCFILL_GPR32d_GPR32d
XED_IFORM_BLCFILL_GPR32d_MEMd
XED_IFORM_BLCFILL_GPRyy_GPRyy
XED_IFORM_BLCFILL_GPRyy_MEMy
XED_IFORM_BLCIC_GPR32d_GPR32d
XED_IFORM_BLCIC_GPR32d_MEMd
XED_IFORM_BLCIC_GPRyy_GPRyy
XED_IFORM_BLCIC_GPRyy_MEMy
XED_IFORM_BLCI_GPR32d_GPR32d
XED_IFORM_BLCI_GPR32d_MEMd
XED_IFORM_BLCI_GPRyy_GPRyy
XED_IFORM_BLCI_GPRyy_MEMy
XED_IFORM_BLCMSK_GPR32d_GPR32d
XED_IFORM_BLCMSK_GPR32d_MEMd
XED_IFORM_BLCMSK_GPRyy_GPRyy
XED_IFORM_BLCMSK_GPRyy_MEMy
XED_IFORM_BLCS_GPR32d_GPR32d
XED_IFORM_BLCS_GPR32d_MEMd
XED_IFORM_BLCS_GPRyy_GPRyy
XED_IFORM_BLCS_GPRyy_MEMy
XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb
XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb
XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb
XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb
XED_IFORM_BLENDVPD_XMMdq_MEMdq
XED_IFORM_BLENDVPD_XMMdq_XMMdq
XED_IFORM_BLENDVPS_XMMdq_MEMdq
XED_IFORM_BLENDVPS_XMMdq_XMMdq
XED_IFORM_BLSFILL_GPR32d_GPR32d
XED_IFORM_BLSFILL_GPR32d_MEMd
XED_IFORM_BLSFILL_GPRyy_GPRyy
XED_IFORM_BLSFILL_GPRyy_MEMy
XED_IFORM_BLSIC_GPR32d_GPR32d
XED_IFORM_BLSIC_GPR32d_MEMd
XED_IFORM_BLSIC_GPRyy_GPRyy
XED_IFORM_BLSIC_GPRyy_MEMy
XED_IFORM_BLSI_GPR32d_GPR32d
XED_IFORM_BLSI_GPR32d_MEMd
XED_IFORM_BLSI_GPR32i32_GPR32i32_APX
XED_IFORM_BLSI_GPR32i32_MEMi32_APX
XED_IFORM_BLSI_GPR64i64_GPR64i64_APX
XED_IFORM_BLSI_GPR64i64_MEMi64_APX
XED_IFORM_BLSI_GPR64q_GPR64q
XED_IFORM_BLSI_GPR64q_MEMq
XED_IFORM_BLSMSK_GPR32d_GPR32d
XED_IFORM_BLSMSK_GPR32d_MEMd
XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX
XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX
XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX
XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX
XED_IFORM_BLSMSK_GPR64q_GPR64q
XED_IFORM_BLSMSK_GPR64q_MEMq
XED_IFORM_BLSR_GPR32d_GPR32d
XED_IFORM_BLSR_GPR32d_MEMd
XED_IFORM_BLSR_GPR32i32_GPR32i32_APX
XED_IFORM_BLSR_GPR32i32_MEMi32_APX
XED_IFORM_BLSR_GPR64i64_GPR64i64_APX
XED_IFORM_BLSR_GPR64i64_MEMi64_APX
XED_IFORM_BLSR_GPR64q_GPR64q
XED_IFORM_BLSR_GPR64q_MEMq
XED_IFORM_BNDCL_BND_AGEN
XED_IFORM_BNDCL_BND_GPR32
XED_IFORM_BNDCL_BND_GPR64
XED_IFORM_BNDCN_BND_AGEN
XED_IFORM_BNDCN_BND_GPR32
XED_IFORM_BNDCN_BND_GPR64
XED_IFORM_BNDCU_BND_AGEN
XED_IFORM_BNDCU_BND_GPR32
XED_IFORM_BNDCU_BND_GPR64
XED_IFORM_BNDLDX_BND_MEMbnd32
XED_IFORM_BNDLDX_BND_MEMbnd64
XED_IFORM_BNDMK_BND_AGEN
XED_IFORM_BNDMOV_BND_BND
XED_IFORM_BNDMOV_BND_MEMdq
XED_IFORM_BNDMOV_BND_MEMq
XED_IFORM_BNDMOV_MEMdq_BND
XED_IFORM_BNDMOV_MEMq_BND
XED_IFORM_BNDSTX_MEMbnd32_BND
XED_IFORM_BNDSTX_MEMbnd64_BND
XED_IFORM_BOUND_GPR16_MEMa16
XED_IFORM_BOUND_GPR32_MEMa32
XED_IFORM_BSF_GPRv_GPRv
XED_IFORM_BSF_GPRv_MEMv
XED_IFORM_BSR_GPRv_GPRv
XED_IFORM_BSR_GPRv_MEMv
XED_IFORM_BSWAP_GPRv
XED_IFORM_BTC_GPRv_GPRv
XED_IFORM_BTC_GPRv_IMMb
XED_IFORM_BTC_LOCK_MEMv_GPRv
XED_IFORM_BTC_LOCK_MEMv_IMMb
XED_IFORM_BTC_MEMv_GPRv
XED_IFORM_BTC_MEMv_IMMb
XED_IFORM_BTR_GPRv_GPRv
XED_IFORM_BTR_GPRv_IMMb
XED_IFORM_BTR_LOCK_MEMv_GPRv
XED_IFORM_BTR_LOCK_MEMv_IMMb
XED_IFORM_BTR_MEMv_GPRv
XED_IFORM_BTR_MEMv_IMMb
XED_IFORM_BTS_GPRv_GPRv
XED_IFORM_BTS_GPRv_IMMb
XED_IFORM_BTS_LOCK_MEMv_GPRv
XED_IFORM_BTS_LOCK_MEMv_IMMb
XED_IFORM_BTS_MEMv_GPRv
XED_IFORM_BTS_MEMv_IMMb
XED_IFORM_BT_GPRv_GPRv
XED_IFORM_BT_GPRv_IMMb
XED_IFORM_BT_MEMv_GPRv
XED_IFORM_BT_MEMv_IMMb
XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d
XED_IFORM_BZHI_GPR32d_MEMd_GPR32d
XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX
XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX
XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q
XED_IFORM_BZHI_GPR64q_MEMq_GPR64q
XED_IFORM_CALL_FAR_MEMp2
XED_IFORM_CALL_FAR_PTRp_IMMw
XED_IFORM_CALL_NEAR_GPRv
XED_IFORM_CALL_NEAR_MEMv
XED_IFORM_CALL_NEAR_RELBRd
XED_IFORM_CALL_NEAR_RELBRz
XED_IFORM_CBW
XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX
XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX
XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX
XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX
XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX
XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX
XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX
XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX
XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX
XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX
XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX
XED_IFORM_CDQ
XED_IFORM_CDQE
XED_IFORM_CFCMOVBE_GPRv_GPRv_APX
XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVBE_GPRv_MEMv_APX
XED_IFORM_CFCMOVBE_MEMv_GPRv_APX
XED_IFORM_CFCMOVB_GPRv_GPRv_APX
XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVB_GPRv_MEMv_APX
XED_IFORM_CFCMOVB_MEMv_GPRv_APX
XED_IFORM_CFCMOVLE_GPRv_GPRv_APX
XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVLE_GPRv_MEMv_APX
XED_IFORM_CFCMOVLE_MEMv_GPRv_APX
XED_IFORM_CFCMOVL_GPRv_GPRv_APX
XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVL_GPRv_MEMv_APX
XED_IFORM_CFCMOVL_MEMv_GPRv_APX
XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX
XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX
XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX
XED_IFORM_CFCMOVNB_GPRv_GPRv_APX
XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNB_GPRv_MEMv_APX
XED_IFORM_CFCMOVNB_MEMv_GPRv_APX
XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX
XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX
XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX
XED_IFORM_CFCMOVNL_GPRv_GPRv_APX
XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNL_GPRv_MEMv_APX
XED_IFORM_CFCMOVNL_MEMv_GPRv_APX
XED_IFORM_CFCMOVNO_GPRv_GPRv_APX
XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNO_GPRv_MEMv_APX
XED_IFORM_CFCMOVNO_MEMv_GPRv_APX
XED_IFORM_CFCMOVNP_GPRv_GPRv_APX
XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNP_GPRv_MEMv_APX
XED_IFORM_CFCMOVNP_MEMv_GPRv_APX
XED_IFORM_CFCMOVNS_GPRv_GPRv_APX
XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNS_GPRv_MEMv_APX
XED_IFORM_CFCMOVNS_MEMv_GPRv_APX
XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX
XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX
XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX
XED_IFORM_CFCMOVO_GPRv_GPRv_APX
XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVO_GPRv_MEMv_APX
XED_IFORM_CFCMOVO_MEMv_GPRv_APX
XED_IFORM_CFCMOVP_GPRv_GPRv_APX
XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVP_GPRv_MEMv_APX
XED_IFORM_CFCMOVP_MEMv_GPRv_APX
XED_IFORM_CFCMOVS_GPRv_GPRv_APX
XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVS_GPRv_MEMv_APX
XED_IFORM_CFCMOVS_MEMv_GPRv_APX
XED_IFORM_CFCMOVZ_GPRv_GPRv_APX
XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX
XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX
XED_IFORM_CFCMOVZ_GPRv_MEMv_APX
XED_IFORM_CFCMOVZ_MEMv_GPRv_APX
XED_IFORM_CLAC
XED_IFORM_CLC
XED_IFORM_CLD
XED_IFORM_CLDEMOTE_MEMu8
XED_IFORM_CLFLUSHOPT_MEMmprefetch
XED_IFORM_CLFLUSH_MEMmprefetch
XED_IFORM_CLGI
XED_IFORM_CLI
XED_IFORM_CLRSSBSY_MEMu64
XED_IFORM_CLTS
XED_IFORM_CLUI
XED_IFORM_CLWB_MEMmprefetch
XED_IFORM_CLZERO
XED_IFORM_CMC
XED_IFORM_CMOVBE_GPRv_GPRv
XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVBE_GPRv_MEMv
XED_IFORM_CMOVB_GPRv_GPRv
XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVB_GPRv_MEMv
XED_IFORM_CMOVLE_GPRv_GPRv
XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVLE_GPRv_MEMv
XED_IFORM_CMOVL_GPRv_GPRv
XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVL_GPRv_MEMv
XED_IFORM_CMOVNBE_GPRv_GPRv
XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNBE_GPRv_MEMv
XED_IFORM_CMOVNB_GPRv_GPRv
XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNB_GPRv_MEMv
XED_IFORM_CMOVNLE_GPRv_GPRv
XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNLE_GPRv_MEMv
XED_IFORM_CMOVNL_GPRv_GPRv
XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNL_GPRv_MEMv
XED_IFORM_CMOVNO_GPRv_GPRv
XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNO_GPRv_MEMv
XED_IFORM_CMOVNP_GPRv_GPRv
XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNP_GPRv_MEMv
XED_IFORM_CMOVNS_GPRv_GPRv
XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNS_GPRv_MEMv
XED_IFORM_CMOVNZ_GPRv_GPRv
XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVNZ_GPRv_MEMv
XED_IFORM_CMOVO_GPRv_GPRv
XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVO_GPRv_MEMv
XED_IFORM_CMOVP_GPRv_GPRv
XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVP_GPRv_MEMv
XED_IFORM_CMOVS_GPRv_GPRv
XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVS_GPRv_MEMv
XED_IFORM_CMOVZ_GPRv_GPRv
XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX
XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX
XED_IFORM_CMOVZ_GPRv_MEMv
XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb
XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb
XED_IFORM_CMPPS_XMMps_MEMps_IMMb
XED_IFORM_CMPPS_XMMps_XMMps_IMMb
XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPSB
XED_IFORM_CMPSD
XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb
XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb
XED_IFORM_CMPSQ
XED_IFORM_CMPSS_XMMss_MEMss_IMMb
XED_IFORM_CMPSS_XMMss_XMMss_IMMb
XED_IFORM_CMPSW
XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMPXCHG8B_LOCK_MEMq
XED_IFORM_CMPXCHG8B_MEMq
XED_IFORM_CMPXCHG16B_LOCK_MEMdq
XED_IFORM_CMPXCHG16B_MEMdq
XED_IFORM_CMPXCHG_GPR8_GPR8
XED_IFORM_CMPXCHG_GPRv_GPRv
XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8
XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv
XED_IFORM_CMPXCHG_MEMb_GPR8
XED_IFORM_CMPXCHG_MEMv_GPRv
XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32
XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX
XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64
XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX
XED_IFORM_CMP_AL_IMMb
XED_IFORM_CMP_GPR8_GPR8_3A
XED_IFORM_CMP_GPR8_GPR8_38
XED_IFORM_CMP_GPR8_IMMb_80r7
XED_IFORM_CMP_GPR8_IMMb_82r7
XED_IFORM_CMP_GPR8_MEMb
XED_IFORM_CMP_GPRv_GPRv_3B
XED_IFORM_CMP_GPRv_GPRv_39
XED_IFORM_CMP_GPRv_IMMb
XED_IFORM_CMP_GPRv_IMMz
XED_IFORM_CMP_GPRv_MEMv
XED_IFORM_CMP_MEMb_GPR8
XED_IFORM_CMP_MEMb_IMMb_80r7
XED_IFORM_CMP_MEMb_IMMb_82r7
XED_IFORM_CMP_MEMv_GPRv
XED_IFORM_CMP_MEMv_IMMb
XED_IFORM_CMP_MEMv_IMMz
XED_IFORM_CMP_OrAX_IMMz
XED_IFORM_COMISD_XMMsd_MEMsd
XED_IFORM_COMISD_XMMsd_XMMsd
XED_IFORM_COMISS_XMMss_MEMss
XED_IFORM_COMISS_XMMss_XMMss
XED_IFORM_CPUID
XED_IFORM_CQO
XED_IFORM_CRC32_GPRy_GPR8i8_APX
XED_IFORM_CRC32_GPRy_GPRv_APX
XED_IFORM_CRC32_GPRy_MEMi8_APX
XED_IFORM_CRC32_GPRy_MEMv_APX
XED_IFORM_CRC32_GPRyy_GPR8b
XED_IFORM_CRC32_GPRyy_GPRv
XED_IFORM_CRC32_GPRyy_MEMb
XED_IFORM_CRC32_GPRyy_MEMv
XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX
XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX
XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX
XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX
XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX
XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX
XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX
XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX
XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX
XED_IFORM_CVTDQ2PD_XMMpd_MEMq
XED_IFORM_CVTDQ2PD_XMMpd_XMMq
XED_IFORM_CVTDQ2PS_XMMps_MEMdq
XED_IFORM_CVTDQ2PS_XMMps_XMMdq
XED_IFORM_CVTPD2DQ_XMMdq_MEMpd
XED_IFORM_CVTPD2DQ_XMMdq_XMMpd
XED_IFORM_CVTPD2PI_MMXq_MEMpd
XED_IFORM_CVTPD2PI_MMXq_XMMpd
XED_IFORM_CVTPD2PS_XMMps_MEMpd
XED_IFORM_CVTPD2PS_XMMps_XMMpd
XED_IFORM_CVTPI2PD_XMMpd_MEMq
XED_IFORM_CVTPI2PD_XMMpd_MMXq
XED_IFORM_CVTPI2PS_XMMq_MEMq
XED_IFORM_CVTPI2PS_XMMq_MMXq
XED_IFORM_CVTPS2DQ_XMMdq_MEMps
XED_IFORM_CVTPS2DQ_XMMdq_XMMps
XED_IFORM_CVTPS2PD_XMMpd_MEMq
XED_IFORM_CVTPS2PD_XMMpd_XMMq
XED_IFORM_CVTPS2PI_MMXq_MEMq
XED_IFORM_CVTPS2PI_MMXq_XMMq
XED_IFORM_CVTSD2SI_GPR32d_MEMsd
XED_IFORM_CVTSD2SI_GPR32d_XMMsd
XED_IFORM_CVTSD2SI_GPR64q_MEMsd
XED_IFORM_CVTSD2SI_GPR64q_XMMsd
XED_IFORM_CVTSD2SS_XMMss_MEMsd
XED_IFORM_CVTSD2SS_XMMss_XMMsd
XED_IFORM_CVTSI2SD_XMMsd_GPR32d
XED_IFORM_CVTSI2SD_XMMsd_GPR64q
XED_IFORM_CVTSI2SD_XMMsd_MEMd
XED_IFORM_CVTSI2SD_XMMsd_MEMq
XED_IFORM_CVTSI2SS_XMMss_GPR32d
XED_IFORM_CVTSI2SS_XMMss_GPR64q
XED_IFORM_CVTSI2SS_XMMss_MEMd
XED_IFORM_CVTSI2SS_XMMss_MEMq
XED_IFORM_CVTSS2SD_XMMsd_MEMss
XED_IFORM_CVTSS2SD_XMMsd_XMMss
XED_IFORM_CVTSS2SI_GPR32d_MEMss
XED_IFORM_CVTSS2SI_GPR32d_XMMss
XED_IFORM_CVTSS2SI_GPR64q_MEMss
XED_IFORM_CVTSS2SI_GPR64q_XMMss
XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd
XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd
XED_IFORM_CVTTPD2PI_MMXq_MEMpd
XED_IFORM_CVTTPD2PI_MMXq_XMMpd
XED_IFORM_CVTTPS2DQ_XMMdq_MEMps
XED_IFORM_CVTTPS2DQ_XMMdq_XMMps
XED_IFORM_CVTTPS2PI_MMXq_MEMq
XED_IFORM_CVTTPS2PI_MMXq_XMMq
XED_IFORM_CVTTSD2SI_GPR32d_MEMsd
XED_IFORM_CVTTSD2SI_GPR32d_XMMsd
XED_IFORM_CVTTSD2SI_GPR64q_MEMsd
XED_IFORM_CVTTSD2SI_GPR64q_XMMsd
XED_IFORM_CVTTSS2SI_GPR32d_MEMss
XED_IFORM_CVTTSS2SI_GPR32d_XMMss
XED_IFORM_CVTTSS2SI_GPR64q_MEMss
XED_IFORM_CVTTSS2SI_GPR64q_XMMss
XED_IFORM_CWD
XED_IFORM_CWDE
XED_IFORM_DAA
XED_IFORM_DAS
XED_IFORM_DEC_GPR8
XED_IFORM_DEC_GPR8i8_APX
XED_IFORM_DEC_GPR8i8_GPR8i8_APX
XED_IFORM_DEC_GPR8i8_MEMi8_APX
XED_IFORM_DEC_GPRv_48
XED_IFORM_DEC_GPRv_APX
XED_IFORM_DEC_GPRv_FFr1
XED_IFORM_DEC_GPRv_GPRv_APX
XED_IFORM_DEC_GPRv_MEMv_APX
XED_IFORM_DEC_LOCK_MEMb
XED_IFORM_DEC_LOCK_MEMv
XED_IFORM_DEC_MEMb
XED_IFORM_DEC_MEMi8_APX
XED_IFORM_DEC_MEMv
XED_IFORM_DEC_MEMv_APX
XED_IFORM_DIVPD_XMMpd_MEMpd
XED_IFORM_DIVPD_XMMpd_XMMpd
XED_IFORM_DIVPS_XMMps_MEMps
XED_IFORM_DIVPS_XMMps_XMMps
XED_IFORM_DIVSD_XMMsd_MEMsd
XED_IFORM_DIVSD_XMMsd_XMMsd
XED_IFORM_DIVSS_XMMss_MEMss
XED_IFORM_DIVSS_XMMss_XMMss
XED_IFORM_DIV_GPR8
XED_IFORM_DIV_GPR8i8_APX
XED_IFORM_DIV_GPRv
XED_IFORM_DIV_GPRv_APX
XED_IFORM_DIV_MEMb
XED_IFORM_DIV_MEMi8_APX
XED_IFORM_DIV_MEMv
XED_IFORM_DIV_MEMv_APX
XED_IFORM_DPPD_XMMdq_MEMdq_IMMb
XED_IFORM_DPPD_XMMdq_XMMdq_IMMb
XED_IFORM_DPPS_XMMdq_MEMdq_IMMb
XED_IFORM_DPPS_XMMdq_XMMdq_IMMb
XED_IFORM_EMMS
XED_IFORM_ENCLS
XED_IFORM_ENCLU
XED_IFORM_ENCLV
XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8
XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8
XED_IFORM_ENDBR32
XED_IFORM_ENDBR64
XED_IFORM_ENQCMDS_GPRa_MEMu32
XED_IFORM_ENQCMDS_GPRav_MEMu32_APX
XED_IFORM_ENQCMD_GPRa_MEMu32
XED_IFORM_ENQCMD_GPRav_MEMu32_APX
XED_IFORM_ENTER_IMMw_IMMb
XED_IFORM_ERETS
XED_IFORM_ERETU
XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb
XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb
XED_IFORM_EXTRQ_XMMq_IMMb_IMMb
XED_IFORM_EXTRQ_XMMq_XMMdq
XED_IFORM_F2XM1
XED_IFORM_FABS
XED_IFORM_FADDP_X87_ST0
XED_IFORM_FADD_MEMm64real
XED_IFORM_FADD_MEMmem32real
XED_IFORM_FADD_ST0_X87
XED_IFORM_FADD_X87_ST0
XED_IFORM_FBLD_ST0_MEMmem80dec
XED_IFORM_FBSTP_MEMmem80dec_ST0
XED_IFORM_FCHS
XED_IFORM_FCMOVBE_ST0_X87
XED_IFORM_FCMOVB_ST0_X87
XED_IFORM_FCMOVE_ST0_X87
XED_IFORM_FCMOVNBE_ST0_X87
XED_IFORM_FCMOVNB_ST0_X87
XED_IFORM_FCMOVNE_ST0_X87
XED_IFORM_FCMOVNU_ST0_X87
XED_IFORM_FCMOVU_ST0_X87
XED_IFORM_FCOMIP_ST0_X87
XED_IFORM_FCOMI_ST0_X87
XED_IFORM_FCOMPP
XED_IFORM_FCOMP_ST0_MEMm64real
XED_IFORM_FCOMP_ST0_MEMmem32real
XED_IFORM_FCOMP_ST0_X87
XED_IFORM_FCOMP_ST0_X87_DCD1
XED_IFORM_FCOMP_ST0_X87_DED0
XED_IFORM_FCOM_ST0_MEMm64real
XED_IFORM_FCOM_ST0_MEMmem32real
XED_IFORM_FCOM_ST0_X87
XED_IFORM_FCOM_ST0_X87_DCD0
XED_IFORM_FCOS
XED_IFORM_FDECSTP
XED_IFORM_FDISI8087_NOP
XED_IFORM_FDIVP_X87_ST0
XED_IFORM_FDIVRP_X87_ST0
XED_IFORM_FDIVR_ST0_MEMm64real
XED_IFORM_FDIVR_ST0_MEMmem32real
XED_IFORM_FDIVR_ST0_X87
XED_IFORM_FDIVR_X87_ST0
XED_IFORM_FDIV_ST0_MEMm64real
XED_IFORM_FDIV_ST0_MEMmem32real
XED_IFORM_FDIV_ST0_X87
XED_IFORM_FDIV_X87_ST0
XED_IFORM_FEMMS
XED_IFORM_FENI8087_NOP
XED_IFORM_FFREEP_X87
XED_IFORM_FFREE_X87
XED_IFORM_FIADD_ST0_MEMmem16int
XED_IFORM_FIADD_ST0_MEMmem32int
XED_IFORM_FICOMP_ST0_MEMmem16int
XED_IFORM_FICOMP_ST0_MEMmem32int
XED_IFORM_FICOM_ST0_MEMmem16int
XED_IFORM_FICOM_ST0_MEMmem32int
XED_IFORM_FIDIVR_ST0_MEMmem16int
XED_IFORM_FIDIVR_ST0_MEMmem32int
XED_IFORM_FIDIV_ST0_MEMmem16int
XED_IFORM_FIDIV_ST0_MEMmem32int
XED_IFORM_FILD_ST0_MEMm64int
XED_IFORM_FILD_ST0_MEMmem16int
XED_IFORM_FILD_ST0_MEMmem32int
XED_IFORM_FIMUL_ST0_MEMmem16int
XED_IFORM_FIMUL_ST0_MEMmem32int
XED_IFORM_FINCSTP
XED_IFORM_FISTP_MEMm64int_ST0
XED_IFORM_FISTP_MEMmem16int_ST0
XED_IFORM_FISTP_MEMmem32int_ST0
XED_IFORM_FISTTP_MEMm64int_ST0
XED_IFORM_FISTTP_MEMmem16int_ST0
XED_IFORM_FISTTP_MEMmem32int_ST0
XED_IFORM_FIST_MEMmem16int_ST0
XED_IFORM_FIST_MEMmem32int_ST0
XED_IFORM_FISUBR_ST0_MEMmem16int
XED_IFORM_FISUBR_ST0_MEMmem32int
XED_IFORM_FISUB_ST0_MEMmem16int
XED_IFORM_FISUB_ST0_MEMmem32int
XED_IFORM_FLD1
XED_IFORM_FLDCW_MEMmem16
XED_IFORM_FLDENV_MEMmem14
XED_IFORM_FLDENV_MEMmem28
XED_IFORM_FLDL2E
XED_IFORM_FLDL2T
XED_IFORM_FLDLG2
XED_IFORM_FLDLN2
XED_IFORM_FLDPI
XED_IFORM_FLDZ
XED_IFORM_FLD_ST0_MEMm64real
XED_IFORM_FLD_ST0_MEMmem32real
XED_IFORM_FLD_ST0_MEMmem80real
XED_IFORM_FLD_ST0_X87
XED_IFORM_FMULP_X87_ST0
XED_IFORM_FMUL_ST0_MEMm64real
XED_IFORM_FMUL_ST0_MEMmem32real
XED_IFORM_FMUL_ST0_X87
XED_IFORM_FMUL_X87_ST0
XED_IFORM_FNCLEX
XED_IFORM_FNINIT
XED_IFORM_FNOP
XED_IFORM_FNSAVE_MEMmem94
XED_IFORM_FNSAVE_MEMmem108
XED_IFORM_FNSTCW_MEMmem16
XED_IFORM_FNSTENV_MEMmem14
XED_IFORM_FNSTENV_MEMmem28
XED_IFORM_FNSTSW_AX
XED_IFORM_FNSTSW_MEMmem16
XED_IFORM_FPATAN
XED_IFORM_FPREM
XED_IFORM_FPREM1
XED_IFORM_FPTAN
XED_IFORM_FRNDINT
XED_IFORM_FRSTOR_MEMmem94
XED_IFORM_FRSTOR_MEMmem108
XED_IFORM_FSCALE
XED_IFORM_FSETPM287_NOP
XED_IFORM_FSIN
XED_IFORM_FSINCOS
XED_IFORM_FSQRT
XED_IFORM_FSTPNCE_X87_ST0
XED_IFORM_FSTP_MEMm64real_ST0
XED_IFORM_FSTP_MEMmem32real_ST0
XED_IFORM_FSTP_MEMmem80real_ST0
XED_IFORM_FSTP_X87_ST0
XED_IFORM_FSTP_X87_ST0_DFD0
XED_IFORM_FSTP_X87_ST0_DFD1
XED_IFORM_FST_MEMm64real_ST0
XED_IFORM_FST_MEMmem32real_ST0
XED_IFORM_FST_X87_ST0
XED_IFORM_FSUBP_X87_ST0
XED_IFORM_FSUBRP_X87_ST0
XED_IFORM_FSUBR_ST0_MEMm64real
XED_IFORM_FSUBR_ST0_MEMmem32real
XED_IFORM_FSUBR_ST0_X87
XED_IFORM_FSUBR_X87_ST0
XED_IFORM_FSUB_ST0_MEMm64real
XED_IFORM_FSUB_ST0_MEMmem32real
XED_IFORM_FSUB_ST0_X87
XED_IFORM_FSUB_X87_ST0
XED_IFORM_FTST
XED_IFORM_FUCOMIP_ST0_X87
XED_IFORM_FUCOMI_ST0_X87
XED_IFORM_FUCOMPP
XED_IFORM_FUCOMP_ST0_X87
XED_IFORM_FUCOM_ST0_X87
XED_IFORM_FWAIT
XED_IFORM_FXAM
XED_IFORM_FXCH_ST0_X87
XED_IFORM_FXCH_ST0_X87_DDC1
XED_IFORM_FXCH_ST0_X87_DFC1
XED_IFORM_FXRSTOR64_MEMmfpxenv
XED_IFORM_FXRSTOR_MEMmfpxenv
XED_IFORM_FXSAVE64_MEMmfpxenv
XED_IFORM_FXSAVE_MEMmfpxenv
XED_IFORM_FXTRACT
XED_IFORM_FYL2X
XED_IFORM_FYL2XP1
XED_IFORM_GETSEC
XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8
XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8
XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8
XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8
XED_IFORM_GF2P8MULB_XMMu8_MEMu8
XED_IFORM_GF2P8MULB_XMMu8_XMMu8
XED_IFORM_HADDPD_XMMpd_MEMpd
XED_IFORM_HADDPD_XMMpd_XMMpd
XED_IFORM_HADDPS_XMMps_MEMps
XED_IFORM_HADDPS_XMMps_XMMps
XED_IFORM_HLT
XED_IFORM_HRESET_IMM8
XED_IFORM_HSUBPD_XMMpd_MEMpd
XED_IFORM_HSUBPD_XMMpd_XMMpd
XED_IFORM_HSUBPS_XMMps_MEMps
XED_IFORM_HSUBPS_XMMps_XMMps
XED_IFORM_IDIV_GPR8
XED_IFORM_IDIV_GPR8i8_APX
XED_IFORM_IDIV_GPRv
XED_IFORM_IDIV_GPRv_APX
XED_IFORM_IDIV_MEMb
XED_IFORM_IDIV_MEMi8_APX
XED_IFORM_IDIV_MEMv
XED_IFORM_IDIV_MEMv_APX
XED_IFORM_IMUL_GPR8
XED_IFORM_IMUL_GPR8i8_APX
XED_IFORM_IMUL_GPRv
XED_IFORM_IMUL_GPRv_APX
XED_IFORM_IMUL_GPRv_GPRv
XED_IFORM_IMUL_GPRv_GPRv_APX
XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX
XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX
XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU
XED_IFORM_IMUL_GPRv_GPRv_IMMb
XED_IFORM_IMUL_GPRv_GPRv_IMMz
XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX
XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU
XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX
XED_IFORM_IMUL_GPRv_MEMv
XED_IFORM_IMUL_GPRv_MEMv_APX
XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX
XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU
XED_IFORM_IMUL_GPRv_MEMv_IMMb
XED_IFORM_IMUL_GPRv_MEMv_IMMz
XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX
XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU
XED_IFORM_IMUL_MEMb
XED_IFORM_IMUL_MEMi8_APX
XED_IFORM_IMUL_MEMv
XED_IFORM_IMUL_MEMv_APX
XED_IFORM_INCSSPD_GPR32u8
XED_IFORM_INCSSPQ_GPR64u8
XED_IFORM_INC_GPR8
XED_IFORM_INC_GPR8i8_APX
XED_IFORM_INC_GPR8i8_GPR8i8_APX
XED_IFORM_INC_GPR8i8_MEMi8_APX
XED_IFORM_INC_GPRv_40
XED_IFORM_INC_GPRv_APX
XED_IFORM_INC_GPRv_FFr0
XED_IFORM_INC_GPRv_GPRv_APX
XED_IFORM_INC_GPRv_MEMv_APX
XED_IFORM_INC_LOCK_MEMb
XED_IFORM_INC_LOCK_MEMv
XED_IFORM_INC_MEMb
XED_IFORM_INC_MEMi8_APX
XED_IFORM_INC_MEMv
XED_IFORM_INC_MEMv_APX
XED_IFORM_INSB
XED_IFORM_INSD
XED_IFORM_INSERTPS_XMMps_MEMd_IMMb
XED_IFORM_INSERTPS_XMMps_XMMps_IMMb
XED_IFORM_INSERTQ_XMMq_XMMdq
XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb
XED_IFORM_INSW
XED_IFORM_INT1
XED_IFORM_INT3
XED_IFORM_INTO
XED_IFORM_INT_IMMb
XED_IFORM_INVALID
XED_IFORM_INVD
XED_IFORM_INVEPT_GPR32_MEMdq
XED_IFORM_INVEPT_GPR64_MEMdq
XED_IFORM_INVEPT_GPR64i64_MEMi128_APX
XED_IFORM_INVLPGA_ArAX_ECX
XED_IFORM_INVLPGB_EAX_EDX_ECX
XED_IFORM_INVLPGB_RAX_EDX_ECX
XED_IFORM_INVLPG_MEMb
XED_IFORM_INVPCID_GPR32_MEMdq
XED_IFORM_INVPCID_GPR64_MEMdq
XED_IFORM_INVPCID_GPR64i64_MEMi128_APX
XED_IFORM_INVVPID_GPR32_MEMdq
XED_IFORM_INVVPID_GPR64_MEMdq
XED_IFORM_INVVPID_GPR64i64_MEMi128_APX
XED_IFORM_IN_AL_DX
XED_IFORM_IN_AL_IMMb
XED_IFORM_IN_OeAX_DX
XED_IFORM_IN_OeAX_IMMb
XED_IFORM_IRET
XED_IFORM_IRETD
XED_IFORM_IRETQ
XED_IFORM_JBE_RELBRb
XED_IFORM_JBE_RELBRd
XED_IFORM_JBE_RELBRz
XED_IFORM_JB_RELBRb
XED_IFORM_JB_RELBRd
XED_IFORM_JB_RELBRz
XED_IFORM_JCXZ_RELBRb
XED_IFORM_JECXZ_RELBRb
XED_IFORM_JLE_RELBRb
XED_IFORM_JLE_RELBRd
XED_IFORM_JLE_RELBRz
XED_IFORM_JL_RELBRb
XED_IFORM_JL_RELBRd
XED_IFORM_JL_RELBRz
XED_IFORM_JMPABS_ABSBRu64_APX
XED_IFORM_JMP_FAR_MEMp2
XED_IFORM_JMP_FAR_PTRp_IMMw
XED_IFORM_JMP_GPRv
XED_IFORM_JMP_MEMv
XED_IFORM_JMP_RELBRb
XED_IFORM_JMP_RELBRd
XED_IFORM_JMP_RELBRz
XED_IFORM_JNBE_RELBRb
XED_IFORM_JNBE_RELBRd
XED_IFORM_JNBE_RELBRz
XED_IFORM_JNB_RELBRb
XED_IFORM_JNB_RELBRd
XED_IFORM_JNB_RELBRz
XED_IFORM_JNLE_RELBRb
XED_IFORM_JNLE_RELBRd
XED_IFORM_JNLE_RELBRz
XED_IFORM_JNL_RELBRb
XED_IFORM_JNL_RELBRd
XED_IFORM_JNL_RELBRz
XED_IFORM_JNO_RELBRb
XED_IFORM_JNO_RELBRd
XED_IFORM_JNO_RELBRz
XED_IFORM_JNP_RELBRb
XED_IFORM_JNP_RELBRd
XED_IFORM_JNP_RELBRz
XED_IFORM_JNS_RELBRb
XED_IFORM_JNS_RELBRd
XED_IFORM_JNS_RELBRz
XED_IFORM_JNZ_RELBRb
XED_IFORM_JNZ_RELBRd
XED_IFORM_JNZ_RELBRz
XED_IFORM_JO_RELBRb
XED_IFORM_JO_RELBRd
XED_IFORM_JO_RELBRz
XED_IFORM_JP_RELBRb
XED_IFORM_JP_RELBRd
XED_IFORM_JP_RELBRz
XED_IFORM_JRCXZ_RELBRb
XED_IFORM_JS_RELBRb
XED_IFORM_JS_RELBRd
XED_IFORM_JS_RELBRz
XED_IFORM_JZ_RELBRb
XED_IFORM_JZ_RELBRd
XED_IFORM_JZ_RELBRz
XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX
XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512
XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX
XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512
XED_IFORM_KMOVB_MASKmskw_MASKu8_APX
XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512
XED_IFORM_KMOVB_MASKmskw_MEMu8_APX
XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512
XED_IFORM_KMOVB_MEMu8_MASKmskw_APX
XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512
XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX
XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512
XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX
XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512
XED_IFORM_KMOVD_MASKmskw_MASKu32_APX
XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512
XED_IFORM_KMOVD_MASKmskw_MEMu32_APX
XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512
XED_IFORM_KMOVD_MEMu32_MASKmskw_APX
XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512
XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX
XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512
XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX
XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512
XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX
XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512
XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX
XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512
XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX
XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512
XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX
XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512
XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX
XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512
XED_IFORM_KMOVW_MASKmskw_MASKu16_APX
XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512
XED_IFORM_KMOVW_MASKmskw_MEMu16_APX
XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512
XED_IFORM_KMOVW_MEMu16_MASKmskw_APX
XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512
XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512
XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512
XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512
XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512
XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512
XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512
XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512
XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512
XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512
XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512
XED_IFORM_LAHF
XED_IFORM_LAR_GPRv_GPRv
XED_IFORM_LAR_GPRv_MEMw
XED_IFORM_LAST
XED_IFORM_LDDQU_XMMpd_MEMdq
XED_IFORM_LDMXCSR_MEMd
XED_IFORM_LDS_GPRz_MEMp
XED_IFORM_LDTILECFG_MEM
XED_IFORM_LDTILECFG_MEM_APX
XED_IFORM_LEAVE
XED_IFORM_LEA_GPRv_AGEN
XED_IFORM_LES_GPRz_MEMp
XED_IFORM_LFENCE
XED_IFORM_LFS_GPRv_MEMp2
XED_IFORM_LGDT_MEMs
XED_IFORM_LGDT_MEMs64
XED_IFORM_LGS_GPRv_MEMp2
XED_IFORM_LIDT_MEMs
XED_IFORM_LIDT_MEMs64
XED_IFORM_LKGS_GPR16u16
XED_IFORM_LKGS_MEMu16
XED_IFORM_LLDT_GPR16
XED_IFORM_LLDT_MEMw
XED_IFORM_LLWPCB_GPRyy
XED_IFORM_LMSW_GPR16
XED_IFORM_LMSW_MEMw
XED_IFORM_LOADIWKEY_XMMu8_XMMu8
XED_IFORM_LODSB
XED_IFORM_LODSD
XED_IFORM_LODSQ
XED_IFORM_LODSW
XED_IFORM_LOOPE_RELBRb
XED_IFORM_LOOPNE_RELBRb
XED_IFORM_LOOP_RELBRb
XED_IFORM_LSL_GPRv_GPRz
XED_IFORM_LSL_GPRv_MEMw
XED_IFORM_LSS_GPRv_MEMp2
XED_IFORM_LTR_GPR16
XED_IFORM_LTR_MEMw
XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd
XED_IFORM_LWPINS_GPRyy_MEMd_IMMd
XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd
XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd
XED_IFORM_LZCNT_GPRv_GPRv
XED_IFORM_LZCNT_GPRv_GPRv_APX
XED_IFORM_LZCNT_GPRv_MEMv
XED_IFORM_LZCNT_GPRv_MEMv_APX
XED_IFORM_MASKMOVDQU_XMMxub_XMMxub
XED_IFORM_MASKMOVQ_MMXq_MMXq
XED_IFORM_MAXPD_XMMpd_MEMpd
XED_IFORM_MAXPD_XMMpd_XMMpd
XED_IFORM_MAXPS_XMMps_MEMps
XED_IFORM_MAXPS_XMMps_XMMps
XED_IFORM_MAXSD_XMMsd_MEMsd
XED_IFORM_MAXSD_XMMsd_XMMsd
XED_IFORM_MAXSS_XMMss_MEMss
XED_IFORM_MAXSS_XMMss_XMMss
XED_IFORM_MCOMMIT
XED_IFORM_MFENCE
XED_IFORM_MINPD_XMMpd_MEMpd
XED_IFORM_MINPD_XMMpd_XMMpd
XED_IFORM_MINPS_XMMps_MEMps
XED_IFORM_MINPS_XMMps_XMMps
XED_IFORM_MINSD_XMMsd_MEMsd
XED_IFORM_MINSD_XMMsd_XMMsd
XED_IFORM_MINSS_XMMss_MEMss
XED_IFORM_MINSS_XMMss_XMMss
XED_IFORM_MONITOR
XED_IFORM_MONITORX
XED_IFORM_MOVAPD_MEMpd_XMMpd
XED_IFORM_MOVAPD_XMMpd_MEMpd
XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28
XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29
XED_IFORM_MOVAPS_MEMps_XMMps
XED_IFORM_MOVAPS_XMMps_MEMps
XED_IFORM_MOVAPS_XMMps_XMMps_0F28
XED_IFORM_MOVAPS_XMMps_XMMps_0F29
XED_IFORM_MOVBE_GPRv_GPRv_APX
XED_IFORM_MOVBE_GPRv_MEMv
XED_IFORM_MOVBE_GPRv_MEMv_APX
XED_IFORM_MOVBE_MEMv_GPRv
XED_IFORM_MOVBE_MEMv_GPRv_APX
XED_IFORM_MOVDDUP_XMMdq_MEMq
XED_IFORM_MOVDDUP_XMMdq_XMMq
XED_IFORM_MOVDIR64B_GPRa_MEM
XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX
XED_IFORM_MOVDIRI_MEMu32_GPR32u32
XED_IFORM_MOVDIRI_MEMu64_GPR64u64
XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX
XED_IFORM_MOVDQ2Q_MMXq_XMMq
XED_IFORM_MOVDQA_MEMdq_XMMdq
XED_IFORM_MOVDQA_XMMdq_MEMdq
XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F
XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F
XED_IFORM_MOVDQU_MEMdq_XMMdq
XED_IFORM_MOVDQU_XMMdq_MEMdq
XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F
XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F
XED_IFORM_MOVD_GPR32_MMXd
XED_IFORM_MOVD_GPR32_XMMd
XED_IFORM_MOVD_MEMd_MMXd
XED_IFORM_MOVD_MEMd_XMMd
XED_IFORM_MOVD_MMXq_GPR32
XED_IFORM_MOVD_MMXq_MEMd
XED_IFORM_MOVD_XMMdq_GPR32
XED_IFORM_MOVD_XMMdq_MEMd
XED_IFORM_MOVHLPS_XMMq_XMMq
XED_IFORM_MOVHPD_MEMq_XMMsd
XED_IFORM_MOVHPD_XMMsd_MEMq
XED_IFORM_MOVHPS_MEMq_XMMps
XED_IFORM_MOVHPS_XMMq_MEMq
XED_IFORM_MOVLHPS_XMMq_XMMq
XED_IFORM_MOVLPD_MEMq_XMMsd
XED_IFORM_MOVLPD_XMMsd_MEMq
XED_IFORM_MOVLPS_MEMq_XMMq
XED_IFORM_MOVLPS_XMMq_MEMq
XED_IFORM_MOVMSKPD_GPR32_XMMpd
XED_IFORM_MOVMSKPS_GPR32_XMMps
XED_IFORM_MOVNTDQA_XMMdq_MEMdq
XED_IFORM_MOVNTDQ_MEMdq_XMMdq
XED_IFORM_MOVNTI_MEMd_GPR32
XED_IFORM_MOVNTI_MEMq_GPR64
XED_IFORM_MOVNTPD_MEMdq_XMMpd
XED_IFORM_MOVNTPS_MEMdq_XMMps
XED_IFORM_MOVNTQ_MEMq_MMXq
XED_IFORM_MOVNTSD_MEMq_XMMq
XED_IFORM_MOVNTSS_MEMd_XMMd
XED_IFORM_MOVQ2DQ_XMMdq_MMXq
XED_IFORM_MOVQ_GPR64_MMXq
XED_IFORM_MOVQ_GPR64_XMMq
XED_IFORM_MOVQ_MEMq_MMXq_0F7E
XED_IFORM_MOVQ_MEMq_MMXq_0F7F
XED_IFORM_MOVQ_MEMq_XMMq_0F7E
XED_IFORM_MOVQ_MEMq_XMMq_0FD6
XED_IFORM_MOVQ_MMXq_GPR64
XED_IFORM_MOVQ_MMXq_MEMq_0F6E
XED_IFORM_MOVQ_MMXq_MEMq_0F6F
XED_IFORM_MOVQ_MMXq_MMXq_0F6F
XED_IFORM_MOVQ_MMXq_MMXq_0F7F
XED_IFORM_MOVQ_XMMdq_GPR64
XED_IFORM_MOVQ_XMMdq_MEMq_0F6E
XED_IFORM_MOVQ_XMMdq_MEMq_0F7E
XED_IFORM_MOVQ_XMMdq_XMMq_0F7E
XED_IFORM_MOVQ_XMMdq_XMMq_0FD6
XED_IFORM_MOVSB
XED_IFORM_MOVSD
XED_IFORM_MOVSD_XMM_MEMsd_XMMsd
XED_IFORM_MOVSD_XMM_XMMdq_MEMsd
XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10
XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11
XED_IFORM_MOVSHDUP_XMMps_MEMps
XED_IFORM_MOVSHDUP_XMMps_XMMps
XED_IFORM_MOVSLDUP_XMMps_MEMps
XED_IFORM_MOVSLDUP_XMMps_XMMps
XED_IFORM_MOVSQ
XED_IFORM_MOVSS_MEMss_XMMss
XED_IFORM_MOVSS_XMMdq_MEMss
XED_IFORM_MOVSS_XMMss_XMMss_0F10
XED_IFORM_MOVSS_XMMss_XMMss_0F11
XED_IFORM_MOVSW
XED_IFORM_MOVSXD_GPRv_GPRz
XED_IFORM_MOVSXD_GPRv_MEMz
XED_IFORM_MOVSX_GPRv_GPR8
XED_IFORM_MOVSX_GPRv_GPR16
XED_IFORM_MOVSX_GPRv_MEMb
XED_IFORM_MOVSX_GPRv_MEMw
XED_IFORM_MOVUPD_MEMpd_XMMpd
XED_IFORM_MOVUPD_XMMpd_MEMpd
XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10
XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11
XED_IFORM_MOVUPS_MEMps_XMMps
XED_IFORM_MOVUPS_XMMps_MEMps
XED_IFORM_MOVUPS_XMMps_XMMps_0F10
XED_IFORM_MOVUPS_XMMps_XMMps_0F11
XED_IFORM_MOVZX_GPRv_GPR8
XED_IFORM_MOVZX_GPRv_GPR16
XED_IFORM_MOVZX_GPRv_MEMb
XED_IFORM_MOVZX_GPRv_MEMw
XED_IFORM_MOV_AL_MEMb
XED_IFORM_MOV_CR_CR_GPR32
XED_IFORM_MOV_CR_CR_GPR64
XED_IFORM_MOV_CR_GPR32_CR
XED_IFORM_MOV_CR_GPR64_CR
XED_IFORM_MOV_DR_DR_GPR32
XED_IFORM_MOV_DR_DR_GPR64
XED_IFORM_MOV_DR_GPR32_DR
XED_IFORM_MOV_DR_GPR64_DR
XED_IFORM_MOV_GPR8_GPR8_8A
XED_IFORM_MOV_GPR8_GPR8_88
XED_IFORM_MOV_GPR8_IMMb_B0
XED_IFORM_MOV_GPR8_IMMb_C6r0
XED_IFORM_MOV_GPR8_MEMb
XED_IFORM_MOV_GPRv_GPRv_8B
XED_IFORM_MOV_GPRv_GPRv_89
XED_IFORM_MOV_GPRv_IMMv
XED_IFORM_MOV_GPRv_IMMz
XED_IFORM_MOV_GPRv_MEMv
XED_IFORM_MOV_GPRv_SEG
XED_IFORM_MOV_MEMb_AL
XED_IFORM_MOV_MEMb_GPR8
XED_IFORM_MOV_MEMb_IMMb
XED_IFORM_MOV_MEMv_GPRv
XED_IFORM_MOV_MEMv_IMMz
XED_IFORM_MOV_MEMv_OrAX
XED_IFORM_MOV_MEMw_SEG
XED_IFORM_MOV_OrAX_MEMv
XED_IFORM_MOV_SEG_GPR16
XED_IFORM_MOV_SEG_MEMw
XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb
XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb
XED_IFORM_MULPD_XMMpd_MEMpd
XED_IFORM_MULPD_XMMpd_XMMpd
XED_IFORM_MULPS_XMMps_MEMps
XED_IFORM_MULPS_XMMps_XMMps
XED_IFORM_MULSD_XMMsd_MEMsd
XED_IFORM_MULSD_XMMsd_XMMsd
XED_IFORM_MULSS_XMMss_MEMss
XED_IFORM_MULSS_XMMss_XMMss
XED_IFORM_MULX_GPR32d_GPR32d_GPR32d
XED_IFORM_MULX_GPR32d_GPR32d_MEMd
XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_MULX_GPR64q_GPR64q_GPR64q
XED_IFORM_MULX_GPR64q_GPR64q_MEMq
XED_IFORM_MUL_GPR8
XED_IFORM_MUL_GPR8i8_APX
XED_IFORM_MUL_GPRv
XED_IFORM_MUL_GPRv_APX
XED_IFORM_MUL_MEMb
XED_IFORM_MUL_MEMi8_APX
XED_IFORM_MUL_MEMv
XED_IFORM_MUL_MEMv_APX
XED_IFORM_MWAIT
XED_IFORM_MWAITX
XED_IFORM_NEG_GPR8
XED_IFORM_NEG_GPR8i8_APX
XED_IFORM_NEG_GPR8i8_GPR8i8_APX
XED_IFORM_NEG_GPR8i8_MEMi8_APX
XED_IFORM_NEG_GPRv
XED_IFORM_NEG_GPRv_APX
XED_IFORM_NEG_GPRv_GPRv_APX
XED_IFORM_NEG_GPRv_MEMv_APX
XED_IFORM_NEG_LOCK_MEMb
XED_IFORM_NEG_LOCK_MEMv
XED_IFORM_NEG_MEMb
XED_IFORM_NEG_MEMi8_APX
XED_IFORM_NEG_MEMv
XED_IFORM_NEG_MEMv_APX
XED_IFORM_NOP_90
XED_IFORM_NOP_GPRv_0F1F
XED_IFORM_NOP_GPRv_0F18r0
XED_IFORM_NOP_GPRv_0F18r1
XED_IFORM_NOP_GPRv_0F18r2
XED_IFORM_NOP_GPRv_0F18r3
XED_IFORM_NOP_GPRv_0F18r4
XED_IFORM_NOP_GPRv_0F18r5
XED_IFORM_NOP_GPRv_0F18r6
XED_IFORM_NOP_GPRv_0F18r7
XED_IFORM_NOP_GPRv_GPRv_0F0D
XED_IFORM_NOP_GPRv_GPRv_0F1A
XED_IFORM_NOP_GPRv_GPRv_0F1B
XED_IFORM_NOP_GPRv_GPRv_0F1C
XED_IFORM_NOP_GPRv_GPRv_0F1D
XED_IFORM_NOP_GPRv_GPRv_0F1E
XED_IFORM_NOP_GPRv_GPRv_0F19
XED_IFORM_NOP_GPRv_MEM_0F1B
XED_IFORM_NOP_GPRv_MEMv_0F1A
XED_IFORM_NOP_MEMv_0F1F
XED_IFORM_NOP_MEMv_0F18r4
XED_IFORM_NOP_MEMv_0F18r5
XED_IFORM_NOP_MEMv_GPRv_0F1C
XED_IFORM_NOP_MEMv_GPRv_0F1D
XED_IFORM_NOP_MEMv_GPRv_0F1E
XED_IFORM_NOP_MEMv_GPRv_0F19
XED_IFORM_NOT_GPR8
XED_IFORM_NOT_GPR8i8_APX
XED_IFORM_NOT_GPR8i8_GPR8i8_APX
XED_IFORM_NOT_GPR8i8_MEMi8_APX
XED_IFORM_NOT_GPRv
XED_IFORM_NOT_GPRv_APX
XED_IFORM_NOT_GPRv_GPRv_APX
XED_IFORM_NOT_GPRv_MEMv_APX
XED_IFORM_NOT_LOCK_MEMb
XED_IFORM_NOT_LOCK_MEMv
XED_IFORM_NOT_MEMb
XED_IFORM_NOT_MEMi8_APX
XED_IFORM_NOT_MEMv
XED_IFORM_NOT_MEMv_APX
XED_IFORM_ORPD_XMMxuq_MEMxuq
XED_IFORM_ORPD_XMMxuq_XMMxuq
XED_IFORM_ORPS_XMMxud_MEMxud
XED_IFORM_ORPS_XMMxud_XMMxud
XED_IFORM_OR_AL_IMMb
XED_IFORM_OR_GPR8_GPR8_0A
XED_IFORM_OR_GPR8_GPR8_08
XED_IFORM_OR_GPR8_IMMb_80r1
XED_IFORM_OR_GPR8_IMMb_82r1
XED_IFORM_OR_GPR8_MEMb
XED_IFORM_OR_GPR8i8_GPR8i8_APX
XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_OR_GPR8i8_IMM8_APX
XED_IFORM_OR_GPR8i8_MEMi8_APX
XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_OR_GPRv_GPRv_0B
XED_IFORM_OR_GPRv_GPRv_09
XED_IFORM_OR_GPRv_GPRv_APX
XED_IFORM_OR_GPRv_GPRv_GPRv_APX
XED_IFORM_OR_GPRv_GPRv_IMM8_APX
XED_IFORM_OR_GPRv_GPRv_IMMz_APX
XED_IFORM_OR_GPRv_GPRv_MEMv_APX
XED_IFORM_OR_GPRv_IMM8_APX
XED_IFORM_OR_GPRv_IMMb
XED_IFORM_OR_GPRv_IMMz
XED_IFORM_OR_GPRv_IMMz_APX
XED_IFORM_OR_GPRv_MEMv
XED_IFORM_OR_GPRv_MEMv_APX
XED_IFORM_OR_GPRv_MEMv_GPRv_APX
XED_IFORM_OR_GPRv_MEMv_IMM8_APX
XED_IFORM_OR_GPRv_MEMv_IMMz_APX
XED_IFORM_OR_LOCK_MEMb_GPR8
XED_IFORM_OR_LOCK_MEMb_IMMb_80r1
XED_IFORM_OR_LOCK_MEMb_IMMb_82r1
XED_IFORM_OR_LOCK_MEMv_GPRv
XED_IFORM_OR_LOCK_MEMv_IMMb
XED_IFORM_OR_LOCK_MEMv_IMMz
XED_IFORM_OR_MEMb_GPR8
XED_IFORM_OR_MEMb_IMMb_80r1
XED_IFORM_OR_MEMb_IMMb_82r1
XED_IFORM_OR_MEMi8_GPR8i8_APX
XED_IFORM_OR_MEMi8_IMM8_APX
XED_IFORM_OR_MEMv_GPRv
XED_IFORM_OR_MEMv_GPRv_APX
XED_IFORM_OR_MEMv_IMM8_APX
XED_IFORM_OR_MEMv_IMMb
XED_IFORM_OR_MEMv_IMMz
XED_IFORM_OR_MEMv_IMMz_APX
XED_IFORM_OR_OrAX_IMMz
XED_IFORM_OUTSB
XED_IFORM_OUTSD
XED_IFORM_OUTSW
XED_IFORM_OUT_DX_AL
XED_IFORM_OUT_DX_OeAX
XED_IFORM_OUT_IMMb_AL
XED_IFORM_OUT_IMMb_OeAX
XED_IFORM_PABSB_MMXq_MEMq
XED_IFORM_PABSB_MMXq_MMXq
XED_IFORM_PABSB_XMMdq_MEMdq
XED_IFORM_PABSB_XMMdq_XMMdq
XED_IFORM_PABSD_MMXq_MEMq
XED_IFORM_PABSD_MMXq_MMXq
XED_IFORM_PABSD_XMMdq_MEMdq
XED_IFORM_PABSD_XMMdq_XMMdq
XED_IFORM_PABSW_MMXq_MEMq
XED_IFORM_PABSW_MMXq_MMXq
XED_IFORM_PABSW_XMMdq_MEMdq
XED_IFORM_PABSW_XMMdq_XMMdq
XED_IFORM_PACKSSDW_MMXq_MEMq
XED_IFORM_PACKSSDW_MMXq_MMXq
XED_IFORM_PACKSSDW_XMMdq_MEMdq
XED_IFORM_PACKSSDW_XMMdq_XMMdq
XED_IFORM_PACKSSWB_MMXq_MEMq
XED_IFORM_PACKSSWB_MMXq_MMXq
XED_IFORM_PACKSSWB_XMMdq_MEMdq
XED_IFORM_PACKSSWB_XMMdq_XMMdq
XED_IFORM_PACKUSDW_XMMdq_MEMdq
XED_IFORM_PACKUSDW_XMMdq_XMMdq
XED_IFORM_PACKUSWB_MMXq_MEMq
XED_IFORM_PACKUSWB_MMXq_MMXq
XED_IFORM_PACKUSWB_XMMdq_MEMdq
XED_IFORM_PACKUSWB_XMMdq_XMMdq
XED_IFORM_PADDB_MMXq_MEMq
XED_IFORM_PADDB_MMXq_MMXq
XED_IFORM_PADDB_XMMdq_MEMdq
XED_IFORM_PADDB_XMMdq_XMMdq
XED_IFORM_PADDD_MMXq_MEMq
XED_IFORM_PADDD_MMXq_MMXq
XED_IFORM_PADDD_XMMdq_MEMdq
XED_IFORM_PADDD_XMMdq_XMMdq
XED_IFORM_PADDQ_MMXq_MEMq
XED_IFORM_PADDQ_MMXq_MMXq
XED_IFORM_PADDQ_XMMdq_MEMdq
XED_IFORM_PADDQ_XMMdq_XMMdq
XED_IFORM_PADDSB_MMXq_MEMq
XED_IFORM_PADDSB_MMXq_MMXq
XED_IFORM_PADDSB_XMMdq_MEMdq
XED_IFORM_PADDSB_XMMdq_XMMdq
XED_IFORM_PADDSW_MMXq_MEMq
XED_IFORM_PADDSW_MMXq_MMXq
XED_IFORM_PADDSW_XMMdq_MEMdq
XED_IFORM_PADDSW_XMMdq_XMMdq
XED_IFORM_PADDUSB_MMXq_MEMq
XED_IFORM_PADDUSB_MMXq_MMXq
XED_IFORM_PADDUSB_XMMdq_MEMdq
XED_IFORM_PADDUSB_XMMdq_XMMdq
XED_IFORM_PADDUSW_MMXq_MEMq
XED_IFORM_PADDUSW_MMXq_MMXq
XED_IFORM_PADDUSW_XMMdq_MEMdq
XED_IFORM_PADDUSW_XMMdq_XMMdq
XED_IFORM_PADDW_MMXq_MEMq
XED_IFORM_PADDW_MMXq_MMXq
XED_IFORM_PADDW_XMMdq_MEMdq
XED_IFORM_PADDW_XMMdq_XMMdq
XED_IFORM_PALIGNR_MMXq_MEMq_IMMb
XED_IFORM_PALIGNR_MMXq_MMXq_IMMb
XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb
XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb
XED_IFORM_PANDN_MMXq_MEMq
XED_IFORM_PANDN_MMXq_MMXq
XED_IFORM_PANDN_XMMdq_MEMdq
XED_IFORM_PANDN_XMMdq_XMMdq
XED_IFORM_PAND_MMXq_MEMq
XED_IFORM_PAND_MMXq_MMXq
XED_IFORM_PAND_XMMdq_MEMdq
XED_IFORM_PAND_XMMdq_XMMdq
XED_IFORM_PAUSE
XED_IFORM_PAVGB_MMXq_MEMq
XED_IFORM_PAVGB_MMXq_MMXq
XED_IFORM_PAVGB_XMMdq_MEMdq
XED_IFORM_PAVGB_XMMdq_XMMdq
XED_IFORM_PAVGUSB_MMXq_MEMq
XED_IFORM_PAVGUSB_MMXq_MMXq
XED_IFORM_PAVGW_MMXq_MEMq
XED_IFORM_PAVGW_MMXq_MMXq
XED_IFORM_PAVGW_XMMdq_MEMdq
XED_IFORM_PAVGW_XMMdq_XMMdq
XED_IFORM_PBLENDVB_XMMdq_MEMdq
XED_IFORM_PBLENDVB_XMMdq_XMMdq
XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb
XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb
XED_IFORM_PBNDKB
XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb
XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPEQB_MMXq_MEMq
XED_IFORM_PCMPEQB_MMXq_MMXq
XED_IFORM_PCMPEQB_XMMdq_MEMdq
XED_IFORM_PCMPEQB_XMMdq_XMMdq
XED_IFORM_PCMPEQD_MMXq_MEMq
XED_IFORM_PCMPEQD_MMXq_MMXq
XED_IFORM_PCMPEQD_XMMdq_MEMdq
XED_IFORM_PCMPEQD_XMMdq_XMMdq
XED_IFORM_PCMPEQQ_XMMdq_MEMdq
XED_IFORM_PCMPEQQ_XMMdq_XMMdq
XED_IFORM_PCMPEQW_MMXq_MEMq
XED_IFORM_PCMPEQW_MMXq_MMXq
XED_IFORM_PCMPEQW_XMMdq_MEMdq
XED_IFORM_PCMPEQW_XMMdq_XMMdq
XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPGTB_MMXq_MEMq
XED_IFORM_PCMPGTB_MMXq_MMXq
XED_IFORM_PCMPGTB_XMMdq_MEMdq
XED_IFORM_PCMPGTB_XMMdq_XMMdq
XED_IFORM_PCMPGTD_MMXq_MEMq
XED_IFORM_PCMPGTD_MMXq_MMXq
XED_IFORM_PCMPGTD_XMMdq_MEMdq
XED_IFORM_PCMPGTD_XMMdq_XMMdq
XED_IFORM_PCMPGTQ_XMMdq_MEMdq
XED_IFORM_PCMPGTQ_XMMdq_XMMdq
XED_IFORM_PCMPGTW_MMXq_MEMq
XED_IFORM_PCMPGTW_MMXq_MMXq
XED_IFORM_PCMPGTW_XMMdq_MEMdq
XED_IFORM_PCMPGTW_XMMdq_XMMdq
XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb
XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb
XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb
XED_IFORM_PCONFIG
XED_IFORM_PCONFIG64
XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d
XED_IFORM_PDEP_GPR32d_GPR32d_MEMd
XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q
XED_IFORM_PDEP_GPR64q_GPR64q_MEMq
XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb
XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb
XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb
XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb
XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb
XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb
XED_IFORM_PEXTRW_GPR32_MMXq_IMMb
XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb
XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb
XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb
XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d
XED_IFORM_PEXT_GPR32d_GPR32d_MEMd
XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX
XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX
XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q
XED_IFORM_PEXT_GPR64q_GPR64q_MEMq
XED_IFORM_PF2ID_MMXq_MEMq
XED_IFORM_PF2ID_MMXq_MMXq
XED_IFORM_PF2IW_MMXq_MEMq
XED_IFORM_PF2IW_MMXq_MMXq
XED_IFORM_PFACC_MMXq_MEMq
XED_IFORM_PFACC_MMXq_MMXq
XED_IFORM_PFADD_MMXq_MEMq
XED_IFORM_PFADD_MMXq_MMXq
XED_IFORM_PFCMPEQ_MMXq_MEMq
XED_IFORM_PFCMPEQ_MMXq_MMXq
XED_IFORM_PFCMPGE_MMXq_MEMq
XED_IFORM_PFCMPGE_MMXq_MMXq
XED_IFORM_PFCMPGT_MMXq_MEMq
XED_IFORM_PFCMPGT_MMXq_MMXq
XED_IFORM_PFMAX_MMXq_MEMq
XED_IFORM_PFMAX_MMXq_MMXq
XED_IFORM_PFMIN_MMXq_MEMq
XED_IFORM_PFMIN_MMXq_MMXq
XED_IFORM_PFMUL_MMXq_MEMq
XED_IFORM_PFMUL_MMXq_MMXq
XED_IFORM_PFNACC_MMXq_MEMq
XED_IFORM_PFNACC_MMXq_MMXq
XED_IFORM_PFPNACC_MMXq_MEMq
XED_IFORM_PFPNACC_MMXq_MMXq
XED_IFORM_PFRCPIT1_MMXq_MEMq
XED_IFORM_PFRCPIT1_MMXq_MMXq
XED_IFORM_PFRCPIT2_MMXq_MEMq
XED_IFORM_PFRCPIT2_MMXq_MMXq
XED_IFORM_PFRCP_MMXq_MEMq
XED_IFORM_PFRCP_MMXq_MMXq
XED_IFORM_PFRSQIT1_MMXq_MEMq
XED_IFORM_PFRSQIT1_MMXq_MMXq
XED_IFORM_PFRSQRT_MMXq_MEMq
XED_IFORM_PFRSQRT_MMXq_MMXq
XED_IFORM_PFSUBR_MMXq_MEMq
XED_IFORM_PFSUBR_MMXq_MMXq
XED_IFORM_PFSUB_MMXq_MEMq
XED_IFORM_PFSUB_MMXq_MMXq
XED_IFORM_PHADDD_MMXq_MEMq
XED_IFORM_PHADDD_MMXq_MMXq
XED_IFORM_PHADDD_XMMdq_MEMdq
XED_IFORM_PHADDD_XMMdq_XMMdq
XED_IFORM_PHADDSW_MMXq_MEMq
XED_IFORM_PHADDSW_MMXq_MMXq
XED_IFORM_PHADDSW_XMMdq_MEMdq
XED_IFORM_PHADDSW_XMMdq_XMMdq
XED_IFORM_PHADDW_MMXq_MEMq
XED_IFORM_PHADDW_MMXq_MMXq
XED_IFORM_PHADDW_XMMdq_MEMdq
XED_IFORM_PHADDW_XMMdq_XMMdq
XED_IFORM_PHMINPOSUW_XMMdq_MEMdq
XED_IFORM_PHMINPOSUW_XMMdq_XMMdq
XED_IFORM_PHSUBD_MMXq_MEMq
XED_IFORM_PHSUBD_MMXq_MMXq
XED_IFORM_PHSUBD_XMMdq_MEMdq
XED_IFORM_PHSUBD_XMMdq_XMMdq
XED_IFORM_PHSUBSW_MMXq_MEMq
XED_IFORM_PHSUBSW_MMXq_MMXq
XED_IFORM_PHSUBSW_XMMdq_MEMdq
XED_IFORM_PHSUBSW_XMMdq_XMMdq
XED_IFORM_PHSUBW_MMXq_MEMq
XED_IFORM_PHSUBW_MMXq_MMXq
XED_IFORM_PHSUBW_XMMdq_MEMdq
XED_IFORM_PHSUBW_XMMdq_XMMdq
XED_IFORM_PI2FD_MMXq_MEMq
XED_IFORM_PI2FD_MMXq_MMXq
XED_IFORM_PI2FW_MMXq_MEMq
XED_IFORM_PI2FW_MMXq_MMXq
XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb
XED_IFORM_PINSRB_XMMdq_MEMb_IMMb
XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb
XED_IFORM_PINSRD_XMMdq_MEMd_IMMb
XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb
XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb
XED_IFORM_PINSRW_MMXq_GPR32_IMMb
XED_IFORM_PINSRW_MMXq_MEMw_IMMb
XED_IFORM_PINSRW_XMMdq_GPR32_IMMb
XED_IFORM_PINSRW_XMMdq_MEMw_IMMb
XED_IFORM_PMADDUBSW_MMXq_MEMq
XED_IFORM_PMADDUBSW_MMXq_MMXq
XED_IFORM_PMADDUBSW_XMMdq_MEMdq
XED_IFORM_PMADDUBSW_XMMdq_XMMdq
XED_IFORM_PMADDWD_MMXq_MEMq
XED_IFORM_PMADDWD_MMXq_MMXq
XED_IFORM_PMADDWD_XMMdq_MEMdq
XED_IFORM_PMADDWD_XMMdq_XMMdq
XED_IFORM_PMAXSB_XMMdq_MEMdq
XED_IFORM_PMAXSB_XMMdq_XMMdq
XED_IFORM_PMAXSD_XMMdq_MEMdq
XED_IFORM_PMAXSD_XMMdq_XMMdq
XED_IFORM_PMAXSW_MMXq_MEMq
XED_IFORM_PMAXSW_MMXq_MMXq
XED_IFORM_PMAXSW_XMMdq_MEMdq
XED_IFORM_PMAXSW_XMMdq_XMMdq
XED_IFORM_PMAXUB_MMXq_MEMq
XED_IFORM_PMAXUB_MMXq_MMXq
XED_IFORM_PMAXUB_XMMdq_MEMdq
XED_IFORM_PMAXUB_XMMdq_XMMdq
XED_IFORM_PMAXUD_XMMdq_MEMdq
XED_IFORM_PMAXUD_XMMdq_XMMdq
XED_IFORM_PMAXUW_XMMdq_MEMdq
XED_IFORM_PMAXUW_XMMdq_XMMdq
XED_IFORM_PMINSB_XMMdq_MEMdq
XED_IFORM_PMINSB_XMMdq_XMMdq
XED_IFORM_PMINSD_XMMdq_MEMdq
XED_IFORM_PMINSD_XMMdq_XMMdq
XED_IFORM_PMINSW_MMXq_MEMq
XED_IFORM_PMINSW_MMXq_MMXq
XED_IFORM_PMINSW_XMMdq_MEMdq
XED_IFORM_PMINSW_XMMdq_XMMdq
XED_IFORM_PMINUB_MMXq_MEMq
XED_IFORM_PMINUB_MMXq_MMXq
XED_IFORM_PMINUB_XMMdq_MEMdq
XED_IFORM_PMINUB_XMMdq_XMMdq
XED_IFORM_PMINUD_XMMdq_MEMdq
XED_IFORM_PMINUD_XMMdq_XMMdq
XED_IFORM_PMINUW_XMMdq_MEMdq
XED_IFORM_PMINUW_XMMdq_XMMdq
XED_IFORM_PMOVMSKB_GPR32_MMXq
XED_IFORM_PMOVMSKB_GPR32_XMMdq
XED_IFORM_PMOVSXBD_XMMdq_MEMd
XED_IFORM_PMOVSXBD_XMMdq_XMMd
XED_IFORM_PMOVSXBQ_XMMdq_MEMw
XED_IFORM_PMOVSXBQ_XMMdq_XMMw
XED_IFORM_PMOVSXBW_XMMdq_MEMq
XED_IFORM_PMOVSXBW_XMMdq_XMMq
XED_IFORM_PMOVSXDQ_XMMdq_MEMq
XED_IFORM_PMOVSXDQ_XMMdq_XMMq
XED_IFORM_PMOVSXWD_XMMdq_MEMq
XED_IFORM_PMOVSXWD_XMMdq_XMMq
XED_IFORM_PMOVSXWQ_XMMdq_MEMd
XED_IFORM_PMOVSXWQ_XMMdq_XMMd
XED_IFORM_PMOVZXBD_XMMdq_MEMd
XED_IFORM_PMOVZXBD_XMMdq_XMMd
XED_IFORM_PMOVZXBQ_XMMdq_MEMw
XED_IFORM_PMOVZXBQ_XMMdq_XMMw
XED_IFORM_PMOVZXBW_XMMdq_MEMq
XED_IFORM_PMOVZXBW_XMMdq_XMMq
XED_IFORM_PMOVZXDQ_XMMdq_MEMq
XED_IFORM_PMOVZXDQ_XMMdq_XMMq
XED_IFORM_PMOVZXWD_XMMdq_MEMq
XED_IFORM_PMOVZXWD_XMMdq_XMMq
XED_IFORM_PMOVZXWQ_XMMdq_MEMd
XED_IFORM_PMOVZXWQ_XMMdq_XMMd
XED_IFORM_PMULDQ_XMMdq_MEMdq
XED_IFORM_PMULDQ_XMMdq_XMMdq
XED_IFORM_PMULHRSW_MMXq_MEMq
XED_IFORM_PMULHRSW_MMXq_MMXq
XED_IFORM_PMULHRSW_XMMdq_MEMdq
XED_IFORM_PMULHRSW_XMMdq_XMMdq
XED_IFORM_PMULHRW_MMXq_MEMq
XED_IFORM_PMULHRW_MMXq_MMXq
XED_IFORM_PMULHUW_MMXq_MEMq
XED_IFORM_PMULHUW_MMXq_MMXq
XED_IFORM_PMULHUW_XMMdq_MEMdq
XED_IFORM_PMULHUW_XMMdq_XMMdq
XED_IFORM_PMULHW_MMXq_MEMq
XED_IFORM_PMULHW_MMXq_MMXq
XED_IFORM_PMULHW_XMMdq_MEMdq
XED_IFORM_PMULHW_XMMdq_XMMdq
XED_IFORM_PMULLD_XMMdq_MEMdq
XED_IFORM_PMULLD_XMMdq_XMMdq
XED_IFORM_PMULLW_MMXq_MEMq
XED_IFORM_PMULLW_MMXq_MMXq
XED_IFORM_PMULLW_XMMdq_MEMdq
XED_IFORM_PMULLW_XMMdq_XMMdq
XED_IFORM_PMULUDQ_MMXq_MEMq
XED_IFORM_PMULUDQ_MMXq_MMXq
XED_IFORM_PMULUDQ_XMMdq_MEMdq
XED_IFORM_PMULUDQ_XMMdq_XMMdq
XED_IFORM_POP2P_GPR64u64_GPR64u64_APX
XED_IFORM_POP2_GPR64u64_GPR64u64_APX
XED_IFORM_POPA
XED_IFORM_POPAD
XED_IFORM_POPCNT_GPRv_GPRv
XED_IFORM_POPCNT_GPRv_GPRv_APX
XED_IFORM_POPCNT_GPRv_MEMv
XED_IFORM_POPCNT_GPRv_MEMv_APX
XED_IFORM_POPF
XED_IFORM_POPFD
XED_IFORM_POPFQ
XED_IFORM_POPP_GPR64
XED_IFORM_POP_DS
XED_IFORM_POP_ES
XED_IFORM_POP_FS
XED_IFORM_POP_GPRv_8F
XED_IFORM_POP_GPRv_58
XED_IFORM_POP_GS
XED_IFORM_POP_MEMv
XED_IFORM_POP_SS
XED_IFORM_POR_MMXq_MEMq
XED_IFORM_POR_MMXq_MMXq
XED_IFORM_POR_XMMdq_MEMdq
XED_IFORM_POR_XMMdq_XMMdq
XED_IFORM_PREFETCHIT0_MEMu8
XED_IFORM_PREFETCHIT1_MEMu8
XED_IFORM_PREFETCHNTA_MEMmprefetch
XED_IFORM_PREFETCHT0_MEMmprefetch
XED_IFORM_PREFETCHT1_MEMmprefetch
XED_IFORM_PREFETCHT2_MEMmprefetch
XED_IFORM_PREFETCHWT1_MEMu8
XED_IFORM_PREFETCHW_0F0Dr1
XED_IFORM_PREFETCHW_0F0Dr3
XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch
XED_IFORM_PREFETCH_RESERVED_0F0Dr4
XED_IFORM_PREFETCH_RESERVED_0F0Dr5
XED_IFORM_PREFETCH_RESERVED_0F0Dr6
XED_IFORM_PREFETCH_RESERVED_0F0Dr7
XED_IFORM_PSADBW_MMXq_MEMq
XED_IFORM_PSADBW_MMXq_MMXq
XED_IFORM_PSADBW_XMMdq_MEMdq
XED_IFORM_PSADBW_XMMdq_XMMdq
XED_IFORM_PSHUFB_MMXq_MEMq
XED_IFORM_PSHUFB_MMXq_MMXq
XED_IFORM_PSHUFB_XMMdq_MEMdq
XED_IFORM_PSHUFB_XMMdq_XMMdq
XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb
XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb
XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb
XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb
XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb
XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb
XED_IFORM_PSHUFW_MMXq_MEMq_IMMb
XED_IFORM_PSHUFW_MMXq_MMXq_IMMb
XED_IFORM_PSIGNB_MMXq_MEMq
XED_IFORM_PSIGNB_MMXq_MMXq
XED_IFORM_PSIGNB_XMMdq_MEMdq
XED_IFORM_PSIGNB_XMMdq_XMMdq
XED_IFORM_PSIGND_MMXq_MEMq
XED_IFORM_PSIGND_MMXq_MMXq
XED_IFORM_PSIGND_XMMdq_MEMdq
XED_IFORM_PSIGND_XMMdq_XMMdq
XED_IFORM_PSIGNW_MMXq_MEMq
XED_IFORM_PSIGNW_MMXq_MMXq
XED_IFORM_PSIGNW_XMMdq_MEMdq
XED_IFORM_PSIGNW_XMMdq_XMMdq
XED_IFORM_PSLLDQ_XMMdq_IMMb
XED_IFORM_PSLLD_MMXq_IMMb
XED_IFORM_PSLLD_MMXq_MEMq
XED_IFORM_PSLLD_MMXq_MMXq
XED_IFORM_PSLLD_XMMdq_IMMb
XED_IFORM_PSLLD_XMMdq_MEMdq
XED_IFORM_PSLLD_XMMdq_XMMdq
XED_IFORM_PSLLQ_MMXq_IMMb
XED_IFORM_PSLLQ_MMXq_MEMq
XED_IFORM_PSLLQ_MMXq_MMXq
XED_IFORM_PSLLQ_XMMdq_IMMb
XED_IFORM_PSLLQ_XMMdq_MEMdq
XED_IFORM_PSLLQ_XMMdq_XMMdq
XED_IFORM_PSLLW_MMXq_IMMb
XED_IFORM_PSLLW_MMXq_MEMq
XED_IFORM_PSLLW_MMXq_MMXq
XED_IFORM_PSLLW_XMMdq_IMMb
XED_IFORM_PSLLW_XMMdq_MEMdq
XED_IFORM_PSLLW_XMMdq_XMMdq
XED_IFORM_PSMASH_RAX
XED_IFORM_PSRAD_MMXq_IMMb
XED_IFORM_PSRAD_MMXq_MEMq
XED_IFORM_PSRAD_MMXq_MMXq
XED_IFORM_PSRAD_XMMdq_IMMb
XED_IFORM_PSRAD_XMMdq_MEMdq
XED_IFORM_PSRAD_XMMdq_XMMdq
XED_IFORM_PSRAW_MMXq_IMMb
XED_IFORM_PSRAW_MMXq_MEMq
XED_IFORM_PSRAW_MMXq_MMXq
XED_IFORM_PSRAW_XMMdq_IMMb
XED_IFORM_PSRAW_XMMdq_MEMdq
XED_IFORM_PSRAW_XMMdq_XMMdq
XED_IFORM_PSRLDQ_XMMdq_IMMb
XED_IFORM_PSRLD_MMXq_IMMb
XED_IFORM_PSRLD_MMXq_MEMq
XED_IFORM_PSRLD_MMXq_MMXq
XED_IFORM_PSRLD_XMMdq_IMMb
XED_IFORM_PSRLD_XMMdq_MEMdq
XED_IFORM_PSRLD_XMMdq_XMMdq
XED_IFORM_PSRLQ_MMXq_IMMb
XED_IFORM_PSRLQ_MMXq_MEMq
XED_IFORM_PSRLQ_MMXq_MMXq
XED_IFORM_PSRLQ_XMMdq_IMMb
XED_IFORM_PSRLQ_XMMdq_MEMdq
XED_IFORM_PSRLQ_XMMdq_XMMdq
XED_IFORM_PSRLW_MMXq_IMMb
XED_IFORM_PSRLW_MMXq_MEMq
XED_IFORM_PSRLW_MMXq_MMXq
XED_IFORM_PSRLW_XMMdq_IMMb
XED_IFORM_PSRLW_XMMdq_MEMdq
XED_IFORM_PSRLW_XMMdq_XMMdq
XED_IFORM_PSUBB_MMXq_MEMq
XED_IFORM_PSUBB_MMXq_MMXq
XED_IFORM_PSUBB_XMMdq_MEMdq
XED_IFORM_PSUBB_XMMdq_XMMdq
XED_IFORM_PSUBD_MMXq_MEMq
XED_IFORM_PSUBD_MMXq_MMXq
XED_IFORM_PSUBD_XMMdq_MEMdq
XED_IFORM_PSUBD_XMMdq_XMMdq
XED_IFORM_PSUBQ_MMXq_MEMq
XED_IFORM_PSUBQ_MMXq_MMXq
XED_IFORM_PSUBQ_XMMdq_MEMdq
XED_IFORM_PSUBQ_XMMdq_XMMdq
XED_IFORM_PSUBSB_MMXq_MEMq
XED_IFORM_PSUBSB_MMXq_MMXq
XED_IFORM_PSUBSB_XMMdq_MEMdq
XED_IFORM_PSUBSB_XMMdq_XMMdq
XED_IFORM_PSUBSW_MMXq_MEMq
XED_IFORM_PSUBSW_MMXq_MMXq
XED_IFORM_PSUBSW_XMMdq_MEMdq
XED_IFORM_PSUBSW_XMMdq_XMMdq
XED_IFORM_PSUBUSB_MMXq_MEMq
XED_IFORM_PSUBUSB_MMXq_MMXq
XED_IFORM_PSUBUSB_XMMdq_MEMdq
XED_IFORM_PSUBUSB_XMMdq_XMMdq
XED_IFORM_PSUBUSW_MMXq_MEMq
XED_IFORM_PSUBUSW_MMXq_MMXq
XED_IFORM_PSUBUSW_XMMdq_MEMdq
XED_IFORM_PSUBUSW_XMMdq_XMMdq
XED_IFORM_PSUBW_MMXq_MEMq
XED_IFORM_PSUBW_MMXq_MMXq
XED_IFORM_PSUBW_XMMdq_MEMdq
XED_IFORM_PSUBW_XMMdq_XMMdq
XED_IFORM_PSWAPD_MMXq_MEMq
XED_IFORM_PSWAPD_MMXq_MMXq
XED_IFORM_PTEST_XMMdq_MEMdq
XED_IFORM_PTEST_XMMdq_XMMdq
XED_IFORM_PTWRITE_GPRy
XED_IFORM_PTWRITE_MEMy
XED_IFORM_PUNPCKHBW_MMXq_MEMq
XED_IFORM_PUNPCKHBW_MMXq_MMXd
XED_IFORM_PUNPCKHBW_XMMdq_MEMdq
XED_IFORM_PUNPCKHBW_XMMdq_XMMq
XED_IFORM_PUNPCKHDQ_MMXq_MEMq
XED_IFORM_PUNPCKHDQ_MMXq_MMXd
XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq
XED_IFORM_PUNPCKHDQ_XMMdq_XMMq
XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq
XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq
XED_IFORM_PUNPCKHWD_MMXq_MEMq
XED_IFORM_PUNPCKHWD_MMXq_MMXd
XED_IFORM_PUNPCKHWD_XMMdq_MEMdq
XED_IFORM_PUNPCKHWD_XMMdq_XMMq
XED_IFORM_PUNPCKLBW_MMXq_MEMd
XED_IFORM_PUNPCKLBW_MMXq_MMXd
XED_IFORM_PUNPCKLBW_XMMdq_MEMdq
XED_IFORM_PUNPCKLBW_XMMdq_XMMq
XED_IFORM_PUNPCKLDQ_MMXq_MEMd
XED_IFORM_PUNPCKLDQ_MMXq_MMXd
XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq
XED_IFORM_PUNPCKLDQ_XMMdq_XMMq
XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq
XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq
XED_IFORM_PUNPCKLWD_MMXq_MEMd
XED_IFORM_PUNPCKLWD_MMXq_MMXd
XED_IFORM_PUNPCKLWD_XMMdq_MEMdq
XED_IFORM_PUNPCKLWD_XMMdq_XMMq
XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX
XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX
XED_IFORM_PUSHA
XED_IFORM_PUSHAD
XED_IFORM_PUSHF
XED_IFORM_PUSHFD
XED_IFORM_PUSHFQ
XED_IFORM_PUSHP_GPR64
XED_IFORM_PUSH_CS
XED_IFORM_PUSH_DS
XED_IFORM_PUSH_ES
XED_IFORM_PUSH_FS
XED_IFORM_PUSH_GPRv_50
XED_IFORM_PUSH_GPRv_FFr6
XED_IFORM_PUSH_GS
XED_IFORM_PUSH_IMMb
XED_IFORM_PUSH_IMMz
XED_IFORM_PUSH_MEMv
XED_IFORM_PUSH_SS
XED_IFORM_PVALIDATE_RAX_ECX_EDX
XED_IFORM_PXOR_MMXq_MEMq
XED_IFORM_PXOR_MMXq_MMXq
XED_IFORM_PXOR_XMMdq_MEMdq
XED_IFORM_PXOR_XMMdq_XMMdq
XED_IFORM_RCL_GPR8_CL
XED_IFORM_RCL_GPR8_IMMb
XED_IFORM_RCL_GPR8_ONE
XED_IFORM_RCL_GPR8i8_CL_APX
XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX
XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_RCL_GPR8i8_IMM8_APX
XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX
XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX
XED_IFORM_RCL_GPR8i8_ONE_APX
XED_IFORM_RCL_GPRv_CL
XED_IFORM_RCL_GPRv_CL_APX
XED_IFORM_RCL_GPRv_GPRv_CL_APX
XED_IFORM_RCL_GPRv_GPRv_IMM8_APX
XED_IFORM_RCL_GPRv_GPRv_ONE_APX
XED_IFORM_RCL_GPRv_IMM8_APX
XED_IFORM_RCL_GPRv_IMMb
XED_IFORM_RCL_GPRv_MEMv_CL_APX
XED_IFORM_RCL_GPRv_MEMv_IMM8_APX
XED_IFORM_RCL_GPRv_MEMv_ONE_APX
XED_IFORM_RCL_GPRv_ONE
XED_IFORM_RCL_GPRv_ONE_APX
XED_IFORM_RCL_MEMb_CL
XED_IFORM_RCL_MEMb_IMMb
XED_IFORM_RCL_MEMb_ONE
XED_IFORM_RCL_MEMi8_CL_APX
XED_IFORM_RCL_MEMi8_IMM8_APX
XED_IFORM_RCL_MEMi8_ONE_APX
XED_IFORM_RCL_MEMv_CL
XED_IFORM_RCL_MEMv_CL_APX
XED_IFORM_RCL_MEMv_IMM8_APX
XED_IFORM_RCL_MEMv_IMMb
XED_IFORM_RCL_MEMv_ONE
XED_IFORM_RCL_MEMv_ONE_APX
XED_IFORM_RCPPS_XMMps_MEMps
XED_IFORM_RCPPS_XMMps_XMMps
XED_IFORM_RCPSS_XMMss_MEMss
XED_IFORM_RCPSS_XMMss_XMMss
XED_IFORM_RCR_GPR8_CL
XED_IFORM_RCR_GPR8_IMMb
XED_IFORM_RCR_GPR8_ONE
XED_IFORM_RCR_GPR8i8_CL_APX
XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX
XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_RCR_GPR8i8_IMM8_APX
XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX
XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX
XED_IFORM_RCR_GPR8i8_ONE_APX
XED_IFORM_RCR_GPRv_CL
XED_IFORM_RCR_GPRv_CL_APX
XED_IFORM_RCR_GPRv_GPRv_CL_APX
XED_IFORM_RCR_GPRv_GPRv_IMM8_APX
XED_IFORM_RCR_GPRv_GPRv_ONE_APX
XED_IFORM_RCR_GPRv_IMM8_APX
XED_IFORM_RCR_GPRv_IMMb
XED_IFORM_RCR_GPRv_MEMv_CL_APX
XED_IFORM_RCR_GPRv_MEMv_IMM8_APX
XED_IFORM_RCR_GPRv_MEMv_ONE_APX
XED_IFORM_RCR_GPRv_ONE
XED_IFORM_RCR_GPRv_ONE_APX
XED_IFORM_RCR_MEMb_CL
XED_IFORM_RCR_MEMb_IMMb
XED_IFORM_RCR_MEMb_ONE
XED_IFORM_RCR_MEMi8_CL_APX
XED_IFORM_RCR_MEMi8_IMM8_APX
XED_IFORM_RCR_MEMi8_ONE_APX
XED_IFORM_RCR_MEMv_CL
XED_IFORM_RCR_MEMv_CL_APX
XED_IFORM_RCR_MEMv_IMM8_APX
XED_IFORM_RCR_MEMv_IMMb
XED_IFORM_RCR_MEMv_ONE
XED_IFORM_RCR_MEMv_ONE_APX
XED_IFORM_RDFSBASE_GPRy
XED_IFORM_RDGSBASE_GPRy
XED_IFORM_RDMSR
XED_IFORM_RDMSRLIST
XED_IFORM_RDPID_GPR32u32
XED_IFORM_RDPID_GPR64u64
XED_IFORM_RDPKRU
XED_IFORM_RDPMC
XED_IFORM_RDPRU
XED_IFORM_RDRAND_GPRv
XED_IFORM_RDSEED_GPRv
XED_IFORM_RDSSPD_GPR32u32
XED_IFORM_RDSSPQ_GPR64u64
XED_IFORM_RDTSC
XED_IFORM_RDTSCP
XED_IFORM_REPE_CMPSB
XED_IFORM_REPE_CMPSD
XED_IFORM_REPE_CMPSQ
XED_IFORM_REPE_CMPSW
XED_IFORM_REPE_SCASB
XED_IFORM_REPE_SCASD
XED_IFORM_REPE_SCASQ
XED_IFORM_REPE_SCASW
XED_IFORM_REPNE_CMPSB
XED_IFORM_REPNE_CMPSD
XED_IFORM_REPNE_CMPSQ
XED_IFORM_REPNE_CMPSW
XED_IFORM_REPNE_SCASB
XED_IFORM_REPNE_SCASD
XED_IFORM_REPNE_SCASQ
XED_IFORM_REPNE_SCASW
XED_IFORM_REP_INSB
XED_IFORM_REP_INSD
XED_IFORM_REP_INSW
XED_IFORM_REP_LODSB
XED_IFORM_REP_LODSD
XED_IFORM_REP_LODSQ
XED_IFORM_REP_LODSW
XED_IFORM_REP_MONTMUL
XED_IFORM_REP_MOVSB
XED_IFORM_REP_MOVSD
XED_IFORM_REP_MOVSQ
XED_IFORM_REP_MOVSW
XED_IFORM_REP_OUTSB
XED_IFORM_REP_OUTSD
XED_IFORM_REP_OUTSW
XED_IFORM_REP_STOSB
XED_IFORM_REP_STOSD
XED_IFORM_REP_STOSQ
XED_IFORM_REP_STOSW
XED_IFORM_REP_XCRYPTCBC
XED_IFORM_REP_XCRYPTCFB
XED_IFORM_REP_XCRYPTCTR
XED_IFORM_REP_XCRYPTECB
XED_IFORM_REP_XCRYPTOFB
XED_IFORM_REP_XSHA1
XED_IFORM_REP_XSHA256
XED_IFORM_REP_XSTORE
XED_IFORM_RET_FAR
XED_IFORM_RET_FAR_IMMw
XED_IFORM_RET_NEAR
XED_IFORM_RET_NEAR_IMMw
XED_IFORM_RMPADJUST_RAX_RCX_RDX
XED_IFORM_RMPUPDATE_RAX_RCX
XED_IFORM_ROL_GPR8_CL
XED_IFORM_ROL_GPR8_IMMb
XED_IFORM_ROL_GPR8_ONE
XED_IFORM_ROL_GPR8i8_CL_APX
XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX
XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_ROL_GPR8i8_IMM8_APX
XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX
XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX
XED_IFORM_ROL_GPR8i8_ONE_APX
XED_IFORM_ROL_GPRv_CL
XED_IFORM_ROL_GPRv_CL_APX
XED_IFORM_ROL_GPRv_GPRv_CL_APX
XED_IFORM_ROL_GPRv_GPRv_IMM8_APX
XED_IFORM_ROL_GPRv_GPRv_ONE_APX
XED_IFORM_ROL_GPRv_IMM8_APX
XED_IFORM_ROL_GPRv_IMMb
XED_IFORM_ROL_GPRv_MEMv_CL_APX
XED_IFORM_ROL_GPRv_MEMv_IMM8_APX
XED_IFORM_ROL_GPRv_MEMv_ONE_APX
XED_IFORM_ROL_GPRv_ONE
XED_IFORM_ROL_GPRv_ONE_APX
XED_IFORM_ROL_MEMb_CL
XED_IFORM_ROL_MEMb_IMMb
XED_IFORM_ROL_MEMb_ONE
XED_IFORM_ROL_MEMi8_CL_APX
XED_IFORM_ROL_MEMi8_IMM8_APX
XED_IFORM_ROL_MEMi8_ONE_APX
XED_IFORM_ROL_MEMv_CL
XED_IFORM_ROL_MEMv_CL_APX
XED_IFORM_ROL_MEMv_IMM8_APX
XED_IFORM_ROL_MEMv_IMMb
XED_IFORM_ROL_MEMv_ONE
XED_IFORM_ROL_MEMv_ONE_APX
XED_IFORM_RORX_GPR32d_GPR32d_IMMb
XED_IFORM_RORX_GPR32d_MEMd_IMMb
XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX
XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX
XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX
XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX
XED_IFORM_RORX_GPR64q_GPR64q_IMMb
XED_IFORM_RORX_GPR64q_MEMq_IMMb
XED_IFORM_ROR_GPR8_CL
XED_IFORM_ROR_GPR8_IMMb
XED_IFORM_ROR_GPR8_ONE
XED_IFORM_ROR_GPR8i8_CL_APX
XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX
XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_ROR_GPR8i8_IMM8_APX
XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX
XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX
XED_IFORM_ROR_GPR8i8_ONE_APX
XED_IFORM_ROR_GPRv_CL
XED_IFORM_ROR_GPRv_CL_APX
XED_IFORM_ROR_GPRv_GPRv_CL_APX
XED_IFORM_ROR_GPRv_GPRv_IMM8_APX
XED_IFORM_ROR_GPRv_GPRv_ONE_APX
XED_IFORM_ROR_GPRv_IMM8_APX
XED_IFORM_ROR_GPRv_IMMb
XED_IFORM_ROR_GPRv_MEMv_CL_APX
XED_IFORM_ROR_GPRv_MEMv_IMM8_APX
XED_IFORM_ROR_GPRv_MEMv_ONE_APX
XED_IFORM_ROR_GPRv_ONE
XED_IFORM_ROR_GPRv_ONE_APX
XED_IFORM_ROR_MEMb_CL
XED_IFORM_ROR_MEMb_IMMb
XED_IFORM_ROR_MEMb_ONE
XED_IFORM_ROR_MEMi8_CL_APX
XED_IFORM_ROR_MEMi8_IMM8_APX
XED_IFORM_ROR_MEMi8_ONE_APX
XED_IFORM_ROR_MEMv_CL
XED_IFORM_ROR_MEMv_CL_APX
XED_IFORM_ROR_MEMv_IMM8_APX
XED_IFORM_ROR_MEMv_IMMb
XED_IFORM_ROR_MEMv_ONE
XED_IFORM_ROR_MEMv_ONE_APX
XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb
XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb
XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb
XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb
XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb
XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb
XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb
XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb
XED_IFORM_RSM
XED_IFORM_RSQRTPS_XMMps_MEMps
XED_IFORM_RSQRTPS_XMMps_XMMps
XED_IFORM_RSQRTSS_XMMss_MEMss
XED_IFORM_RSQRTSS_XMMss_XMMss
XED_IFORM_RSTORSSP_MEMu64
XED_IFORM_SAHF
XED_IFORM_SALC
XED_IFORM_SARX_GPR32d_GPR32d_GPR32d
XED_IFORM_SARX_GPR32d_MEMd_GPR32d
XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX
XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX
XED_IFORM_SARX_GPR64q_GPR64q_GPR64q
XED_IFORM_SARX_GPR64q_MEMq_GPR64q
XED_IFORM_SAR_GPR8_CL
XED_IFORM_SAR_GPR8_IMMb
XED_IFORM_SAR_GPR8_ONE
XED_IFORM_SAR_GPR8i8_CL_APX
XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX
XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_SAR_GPR8i8_IMM8_APX
XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX
XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX
XED_IFORM_SAR_GPR8i8_ONE_APX
XED_IFORM_SAR_GPRv_CL
XED_IFORM_SAR_GPRv_CL_APX
XED_IFORM_SAR_GPRv_GPRv_CL_APX
XED_IFORM_SAR_GPRv_GPRv_IMM8_APX
XED_IFORM_SAR_GPRv_GPRv_ONE_APX
XED_IFORM_SAR_GPRv_IMM8_APX
XED_IFORM_SAR_GPRv_IMMb
XED_IFORM_SAR_GPRv_MEMv_CL_APX
XED_IFORM_SAR_GPRv_MEMv_IMM8_APX
XED_IFORM_SAR_GPRv_MEMv_ONE_APX
XED_IFORM_SAR_GPRv_ONE
XED_IFORM_SAR_GPRv_ONE_APX
XED_IFORM_SAR_MEMb_CL
XED_IFORM_SAR_MEMb_IMMb
XED_IFORM_SAR_MEMb_ONE
XED_IFORM_SAR_MEMi8_CL_APX
XED_IFORM_SAR_MEMi8_IMM8_APX
XED_IFORM_SAR_MEMi8_ONE_APX
XED_IFORM_SAR_MEMv_CL
XED_IFORM_SAR_MEMv_CL_APX
XED_IFORM_SAR_MEMv_IMM8_APX
XED_IFORM_SAR_MEMv_IMMb
XED_IFORM_SAR_MEMv_ONE
XED_IFORM_SAR_MEMv_ONE_APX
XED_IFORM_SAVEPREVSSP
XED_IFORM_SBB_AL_IMMb
XED_IFORM_SBB_GPR8_GPR8_1A
XED_IFORM_SBB_GPR8_GPR8_18
XED_IFORM_SBB_GPR8_IMMb_80r3
XED_IFORM_SBB_GPR8_IMMb_82r3
XED_IFORM_SBB_GPR8_MEMb
XED_IFORM_SBB_GPR8i8_GPR8i8_APX
XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_SBB_GPR8i8_IMM8_APX
XED_IFORM_SBB_GPR8i8_MEMi8_APX
XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_SBB_GPRv_GPRv_1B
XED_IFORM_SBB_GPRv_GPRv_19
XED_IFORM_SBB_GPRv_GPRv_APX
XED_IFORM_SBB_GPRv_GPRv_GPRv_APX
XED_IFORM_SBB_GPRv_GPRv_IMM8_APX
XED_IFORM_SBB_GPRv_GPRv_IMMz_APX
XED_IFORM_SBB_GPRv_GPRv_MEMv_APX
XED_IFORM_SBB_GPRv_IMM8_APX
XED_IFORM_SBB_GPRv_IMMb
XED_IFORM_SBB_GPRv_IMMz
XED_IFORM_SBB_GPRv_IMMz_APX
XED_IFORM_SBB_GPRv_MEMv
XED_IFORM_SBB_GPRv_MEMv_APX
XED_IFORM_SBB_GPRv_MEMv_GPRv_APX
XED_IFORM_SBB_GPRv_MEMv_IMM8_APX
XED_IFORM_SBB_GPRv_MEMv_IMMz_APX
XED_IFORM_SBB_LOCK_MEMb_GPR8
XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3
XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3
XED_IFORM_SBB_LOCK_MEMv_GPRv
XED_IFORM_SBB_LOCK_MEMv_IMMb
XED_IFORM_SBB_LOCK_MEMv_IMMz
XED_IFORM_SBB_MEMb_GPR8
XED_IFORM_SBB_MEMb_IMMb_80r3
XED_IFORM_SBB_MEMb_IMMb_82r3
XED_IFORM_SBB_MEMi8_GPR8i8_APX
XED_IFORM_SBB_MEMi8_IMM8_APX
XED_IFORM_SBB_MEMv_GPRv
XED_IFORM_SBB_MEMv_GPRv_APX
XED_IFORM_SBB_MEMv_IMM8_APX
XED_IFORM_SBB_MEMv_IMMb
XED_IFORM_SBB_MEMv_IMMz
XED_IFORM_SBB_MEMv_IMMz_APX
XED_IFORM_SBB_OrAX_IMMz
XED_IFORM_SCASB
XED_IFORM_SCASD
XED_IFORM_SCASQ
XED_IFORM_SCASW
XED_IFORM_SEAMCALL
XED_IFORM_SEAMOPS
XED_IFORM_SEAMRET
XED_IFORM_SENDUIPI_GPR64u32
XED_IFORM_SERIALIZE
XED_IFORM_SETBE_GPR8
XED_IFORM_SETBE_GPR8i8_APX
XED_IFORM_SETBE_GPR8i8_APX_ZU
XED_IFORM_SETBE_MEMb
XED_IFORM_SETBE_MEMi8_APX
XED_IFORM_SETBE_MEMi8_APX_ZU
XED_IFORM_SETB_GPR8
XED_IFORM_SETB_GPR8i8_APX
XED_IFORM_SETB_GPR8i8_APX_ZU
XED_IFORM_SETB_MEMb
XED_IFORM_SETB_MEMi8_APX
XED_IFORM_SETB_MEMi8_APX_ZU
XED_IFORM_SETLE_GPR8
XED_IFORM_SETLE_GPR8i8_APX
XED_IFORM_SETLE_GPR8i8_APX_ZU
XED_IFORM_SETLE_MEMb
XED_IFORM_SETLE_MEMi8_APX
XED_IFORM_SETLE_MEMi8_APX_ZU
XED_IFORM_SETL_GPR8
XED_IFORM_SETL_GPR8i8_APX
XED_IFORM_SETL_GPR8i8_APX_ZU
XED_IFORM_SETL_MEMb
XED_IFORM_SETL_MEMi8_APX
XED_IFORM_SETL_MEMi8_APX_ZU
XED_IFORM_SETNBE_GPR8
XED_IFORM_SETNBE_GPR8i8_APX
XED_IFORM_SETNBE_GPR8i8_APX_ZU
XED_IFORM_SETNBE_MEMb
XED_IFORM_SETNBE_MEMi8_APX
XED_IFORM_SETNBE_MEMi8_APX_ZU
XED_IFORM_SETNB_GPR8
XED_IFORM_SETNB_GPR8i8_APX
XED_IFORM_SETNB_GPR8i8_APX_ZU
XED_IFORM_SETNB_MEMb
XED_IFORM_SETNB_MEMi8_APX
XED_IFORM_SETNB_MEMi8_APX_ZU
XED_IFORM_SETNLE_GPR8
XED_IFORM_SETNLE_GPR8i8_APX
XED_IFORM_SETNLE_GPR8i8_APX_ZU
XED_IFORM_SETNLE_MEMb
XED_IFORM_SETNLE_MEMi8_APX
XED_IFORM_SETNLE_MEMi8_APX_ZU
XED_IFORM_SETNL_GPR8
XED_IFORM_SETNL_GPR8i8_APX
XED_IFORM_SETNL_GPR8i8_APX_ZU
XED_IFORM_SETNL_MEMb
XED_IFORM_SETNL_MEMi8_APX
XED_IFORM_SETNL_MEMi8_APX_ZU
XED_IFORM_SETNO_GPR8
XED_IFORM_SETNO_GPR8i8_APX
XED_IFORM_SETNO_GPR8i8_APX_ZU
XED_IFORM_SETNO_MEMb
XED_IFORM_SETNO_MEMi8_APX
XED_IFORM_SETNO_MEMi8_APX_ZU
XED_IFORM_SETNP_GPR8
XED_IFORM_SETNP_GPR8i8_APX
XED_IFORM_SETNP_GPR8i8_APX_ZU
XED_IFORM_SETNP_MEMb
XED_IFORM_SETNP_MEMi8_APX
XED_IFORM_SETNP_MEMi8_APX_ZU
XED_IFORM_SETNS_GPR8
XED_IFORM_SETNS_GPR8i8_APX
XED_IFORM_SETNS_GPR8i8_APX_ZU
XED_IFORM_SETNS_MEMb
XED_IFORM_SETNS_MEMi8_APX
XED_IFORM_SETNS_MEMi8_APX_ZU
XED_IFORM_SETNZ_GPR8
XED_IFORM_SETNZ_GPR8i8_APX
XED_IFORM_SETNZ_GPR8i8_APX_ZU
XED_IFORM_SETNZ_MEMb
XED_IFORM_SETNZ_MEMi8_APX
XED_IFORM_SETNZ_MEMi8_APX_ZU
XED_IFORM_SETO_GPR8
XED_IFORM_SETO_GPR8i8_APX
XED_IFORM_SETO_GPR8i8_APX_ZU
XED_IFORM_SETO_MEMb
XED_IFORM_SETO_MEMi8_APX
XED_IFORM_SETO_MEMi8_APX_ZU
XED_IFORM_SETP_GPR8
XED_IFORM_SETP_GPR8i8_APX
XED_IFORM_SETP_GPR8i8_APX_ZU
XED_IFORM_SETP_MEMb
XED_IFORM_SETP_MEMi8_APX
XED_IFORM_SETP_MEMi8_APX_ZU
XED_IFORM_SETSSBSY
XED_IFORM_SETS_GPR8
XED_IFORM_SETS_GPR8i8_APX
XED_IFORM_SETS_GPR8i8_APX_ZU
XED_IFORM_SETS_MEMb
XED_IFORM_SETS_MEMi8_APX
XED_IFORM_SETS_MEMi8_APX_ZU
XED_IFORM_SETZ_GPR8
XED_IFORM_SETZ_GPR8i8_APX
XED_IFORM_SETZ_GPR8i8_APX_ZU
XED_IFORM_SETZ_MEMb
XED_IFORM_SETZ_MEMi8_APX
XED_IFORM_SETZ_MEMi8_APX_ZU
XED_IFORM_SFENCE
XED_IFORM_SGDT_MEMs
XED_IFORM_SGDT_MEMs64
XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA
XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA
XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA
XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA
XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA
XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA
XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA
XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA
XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA
XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA
XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA
XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA
XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA
XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA
XED_IFORM_SHLD_GPRv_GPRv_CL
XED_IFORM_SHLD_GPRv_GPRv_CL_APX
XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX
XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX
XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX
XED_IFORM_SHLD_GPRv_GPRv_IMMb
XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX
XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX
XED_IFORM_SHLD_MEMv_GPRv_CL
XED_IFORM_SHLD_MEMv_GPRv_CL_APX
XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX
XED_IFORM_SHLD_MEMv_GPRv_IMMb
XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d
XED_IFORM_SHLX_GPR32d_MEMd_GPR32d
XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX
XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX
XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q
XED_IFORM_SHLX_GPR64q_MEMq_GPR64q
XED_IFORM_SHL_GPR8_CL_D2r4
XED_IFORM_SHL_GPR8_CL_D2r6
XED_IFORM_SHL_GPR8_IMMb_C0r4
XED_IFORM_SHL_GPR8_IMMb_C0r6
XED_IFORM_SHL_GPR8_ONE_D0r4
XED_IFORM_SHL_GPR8_ONE_D0r6
XED_IFORM_SHL_GPR8i8_CL_APX
XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX
XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_SHL_GPR8i8_IMM8_APX
XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX
XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX
XED_IFORM_SHL_GPR8i8_ONE_APX
XED_IFORM_SHL_GPRv_CL_APX
XED_IFORM_SHL_GPRv_CL_D3r4
XED_IFORM_SHL_GPRv_CL_D3r6
XED_IFORM_SHL_GPRv_GPRv_CL_APX
XED_IFORM_SHL_GPRv_GPRv_IMM8_APX
XED_IFORM_SHL_GPRv_GPRv_ONE_APX
XED_IFORM_SHL_GPRv_IMM8_APX
XED_IFORM_SHL_GPRv_IMMb_C1r4
XED_IFORM_SHL_GPRv_IMMb_C1r6
XED_IFORM_SHL_GPRv_MEMv_CL_APX
XED_IFORM_SHL_GPRv_MEMv_IMM8_APX
XED_IFORM_SHL_GPRv_MEMv_ONE_APX
XED_IFORM_SHL_GPRv_ONE_APX
XED_IFORM_SHL_GPRv_ONE_D1r4
XED_IFORM_SHL_GPRv_ONE_D1r6
XED_IFORM_SHL_MEMb_CL_D2r4
XED_IFORM_SHL_MEMb_CL_D2r6
XED_IFORM_SHL_MEMb_IMMb_C0r4
XED_IFORM_SHL_MEMb_IMMb_C0r6
XED_IFORM_SHL_MEMb_ONE_D0r4
XED_IFORM_SHL_MEMb_ONE_D0r6
XED_IFORM_SHL_MEMi8_CL_APX
XED_IFORM_SHL_MEMi8_IMM8_APX
XED_IFORM_SHL_MEMi8_ONE_APX
XED_IFORM_SHL_MEMv_CL_APX
XED_IFORM_SHL_MEMv_CL_D3r4
XED_IFORM_SHL_MEMv_CL_D3r6
XED_IFORM_SHL_MEMv_IMM8_APX
XED_IFORM_SHL_MEMv_IMMb_C1r4
XED_IFORM_SHL_MEMv_IMMb_C1r6
XED_IFORM_SHL_MEMv_ONE_APX
XED_IFORM_SHL_MEMv_ONE_D1r4
XED_IFORM_SHL_MEMv_ONE_D1r6
XED_IFORM_SHRD_GPRv_GPRv_CL
XED_IFORM_SHRD_GPRv_GPRv_CL_APX
XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX
XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX
XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX
XED_IFORM_SHRD_GPRv_GPRv_IMMb
XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX
XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX
XED_IFORM_SHRD_MEMv_GPRv_CL
XED_IFORM_SHRD_MEMv_GPRv_CL_APX
XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX
XED_IFORM_SHRD_MEMv_GPRv_IMMb
XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d
XED_IFORM_SHRX_GPR32d_MEMd_GPR32d
XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX
XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX
XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX
XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX
XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q
XED_IFORM_SHRX_GPR64q_MEMq_GPR64q
XED_IFORM_SHR_GPR8_CL
XED_IFORM_SHR_GPR8_IMMb
XED_IFORM_SHR_GPR8_ONE
XED_IFORM_SHR_GPR8i8_CL_APX
XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX
XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX
XED_IFORM_SHR_GPR8i8_IMM8_APX
XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX
XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX
XED_IFORM_SHR_GPR8i8_ONE_APX
XED_IFORM_SHR_GPRv_CL
XED_IFORM_SHR_GPRv_CL_APX
XED_IFORM_SHR_GPRv_GPRv_CL_APX
XED_IFORM_SHR_GPRv_GPRv_IMM8_APX
XED_IFORM_SHR_GPRv_GPRv_ONE_APX
XED_IFORM_SHR_GPRv_IMM8_APX
XED_IFORM_SHR_GPRv_IMMb
XED_IFORM_SHR_GPRv_MEMv_CL_APX
XED_IFORM_SHR_GPRv_MEMv_IMM8_APX
XED_IFORM_SHR_GPRv_MEMv_ONE_APX
XED_IFORM_SHR_GPRv_ONE
XED_IFORM_SHR_GPRv_ONE_APX
XED_IFORM_SHR_MEMb_CL
XED_IFORM_SHR_MEMb_IMMb
XED_IFORM_SHR_MEMb_ONE
XED_IFORM_SHR_MEMi8_CL_APX
XED_IFORM_SHR_MEMi8_IMM8_APX
XED_IFORM_SHR_MEMi8_ONE_APX
XED_IFORM_SHR_MEMv_CL
XED_IFORM_SHR_MEMv_CL_APX
XED_IFORM_SHR_MEMv_IMM8_APX
XED_IFORM_SHR_MEMv_IMMb
XED_IFORM_SHR_MEMv_ONE
XED_IFORM_SHR_MEMv_ONE_APX
XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb
XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb
XED_IFORM_SHUFPS_XMMps_MEMps_IMMb
XED_IFORM_SHUFPS_XMMps_XMMps_IMMb
XED_IFORM_SIDT_MEMs
XED_IFORM_SIDT_MEMs64
XED_IFORM_SKINIT_EAX
XED_IFORM_SLDT_GPRv
XED_IFORM_SLDT_MEMw
XED_IFORM_SLWPCB_GPRyy
XED_IFORM_SMSW_GPRv
XED_IFORM_SMSW_MEMw
XED_IFORM_SQRTPD_XMMpd_MEMpd
XED_IFORM_SQRTPD_XMMpd_XMMpd
XED_IFORM_SQRTPS_XMMps_MEMps
XED_IFORM_SQRTPS_XMMps_XMMps
XED_IFORM_SQRTSD_XMMsd_MEMsd
XED_IFORM_SQRTSD_XMMsd_XMMsd
XED_IFORM_SQRTSS_XMMss_MEMss
XED_IFORM_SQRTSS_XMMss_XMMss
XED_IFORM_STAC
XED_IFORM_STC
XED_IFORM_STD
XED_IFORM_STGI
XED_IFORM_STI
XED_IFORM_STMXCSR_MEMd
XED_IFORM_STOSB
XED_IFORM_STOSD
XED_IFORM_STOSQ
XED_IFORM_STOSW
XED_IFORM_STR_GPRv
XED_IFORM_STR_MEMw
XED_IFORM_STTILECFG_MEM
XED_IFORM_STTILECFG_MEM_APX
XED_IFORM_STUI
XED_IFORM_SUBPD_XMMpd_MEMpd
XED_IFORM_SUBPD_XMMpd_XMMpd
XED_IFORM_SUBPS_XMMps_MEMps
XED_IFORM_SUBPS_XMMps_XMMps
XED_IFORM_SUBSD_XMMsd_MEMsd
XED_IFORM_SUBSD_XMMsd_XMMsd
XED_IFORM_SUBSS_XMMss_MEMss
XED_IFORM_SUBSS_XMMss_XMMss
XED_IFORM_SUB_AL_IMMb
XED_IFORM_SUB_GPR8_GPR8_2A
XED_IFORM_SUB_GPR8_GPR8_28
XED_IFORM_SUB_GPR8_IMMb_80r5
XED_IFORM_SUB_GPR8_IMMb_82r5
XED_IFORM_SUB_GPR8_MEMb
XED_IFORM_SUB_GPR8i8_GPR8i8_APX
XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_SUB_GPR8i8_IMM8_APX
XED_IFORM_SUB_GPR8i8_MEMi8_APX
XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_SUB_GPRv_GPRv_2B
XED_IFORM_SUB_GPRv_GPRv_29
XED_IFORM_SUB_GPRv_GPRv_APX
XED_IFORM_SUB_GPRv_GPRv_GPRv_APX
XED_IFORM_SUB_GPRv_GPRv_IMM8_APX
XED_IFORM_SUB_GPRv_GPRv_IMMz_APX
XED_IFORM_SUB_GPRv_GPRv_MEMv_APX
XED_IFORM_SUB_GPRv_IMM8_APX
XED_IFORM_SUB_GPRv_IMMb
XED_IFORM_SUB_GPRv_IMMz
XED_IFORM_SUB_GPRv_IMMz_APX
XED_IFORM_SUB_GPRv_MEMv
XED_IFORM_SUB_GPRv_MEMv_APX
XED_IFORM_SUB_GPRv_MEMv_GPRv_APX
XED_IFORM_SUB_GPRv_MEMv_IMM8_APX
XED_IFORM_SUB_GPRv_MEMv_IMMz_APX
XED_IFORM_SUB_LOCK_MEMb_GPR8
XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5
XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5
XED_IFORM_SUB_LOCK_MEMv_GPRv
XED_IFORM_SUB_LOCK_MEMv_IMMb
XED_IFORM_SUB_LOCK_MEMv_IMMz
XED_IFORM_SUB_MEMb_GPR8
XED_IFORM_SUB_MEMb_IMMb_80r5
XED_IFORM_SUB_MEMb_IMMb_82r5
XED_IFORM_SUB_MEMi8_GPR8i8_APX
XED_IFORM_SUB_MEMi8_IMM8_APX
XED_IFORM_SUB_MEMv_GPRv
XED_IFORM_SUB_MEMv_GPRv_APX
XED_IFORM_SUB_MEMv_IMM8_APX
XED_IFORM_SUB_MEMv_IMMb
XED_IFORM_SUB_MEMv_IMMz
XED_IFORM_SUB_MEMv_IMMz_APX
XED_IFORM_SUB_OrAX_IMMz
XED_IFORM_SWAPGS
XED_IFORM_SYSCALL
XED_IFORM_SYSCALL_32
XED_IFORM_SYSENTER
XED_IFORM_SYSEXIT
XED_IFORM_SYSRET
XED_IFORM_SYSRET64
XED_IFORM_SYSRET_AMD
XED_IFORM_T1MSKC_GPR32d_GPR32d
XED_IFORM_T1MSKC_GPR32d_MEMd
XED_IFORM_T1MSKC_GPRyy_GPRyy
XED_IFORM_T1MSKC_GPRyy_MEMy
XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16
XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16
XED_IFORM_TDCALL
XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16
XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8
XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8
XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8
XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8
XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16
XED_IFORM_TESTUI
XED_IFORM_TEST_AL_IMMb
XED_IFORM_TEST_GPR8_GPR8
XED_IFORM_TEST_GPR8_IMMb_F6r0
XED_IFORM_TEST_GPR8_IMMb_F6r1
XED_IFORM_TEST_GPRv_GPRv
XED_IFORM_TEST_GPRv_IMMz_F7r0
XED_IFORM_TEST_GPRv_IMMz_F7r1
XED_IFORM_TEST_MEMb_GPR8
XED_IFORM_TEST_MEMb_IMMb_F6r0
XED_IFORM_TEST_MEMb_IMMb_F6r1
XED_IFORM_TEST_MEMv_GPRv
XED_IFORM_TEST_MEMv_IMMz_F7r0
XED_IFORM_TEST_MEMv_IMMz_F7r1
XED_IFORM_TEST_OrAX_IMMz
XED_IFORM_TILELOADDT1_TMMu32_MEMu32
XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX
XED_IFORM_TILELOADD_TMMu32_MEMu32
XED_IFORM_TILELOADD_TMMu32_MEMu32_APX
XED_IFORM_TILERELEASE
XED_IFORM_TILESTORED_MEMu32_TMMu32
XED_IFORM_TILESTORED_MEMu32_TMMu32_APX
XED_IFORM_TILEZERO_TMMu32
XED_IFORM_TLBSYNC
XED_IFORM_TPAUSE_GPR32u32
XED_IFORM_TZCNT_GPRv_GPRv
XED_IFORM_TZCNT_GPRv_GPRv_APX
XED_IFORM_TZCNT_GPRv_MEMv
XED_IFORM_TZCNT_GPRv_MEMv_APX
XED_IFORM_TZMSK_GPR32d_GPR32d
XED_IFORM_TZMSK_GPR32d_MEMd
XED_IFORM_TZMSK_GPRyy_GPRyy
XED_IFORM_TZMSK_GPRyy_MEMy
XED_IFORM_UCOMISD_XMMsd_MEMsd
XED_IFORM_UCOMISD_XMMsd_XMMsd
XED_IFORM_UCOMISS_XMMss_MEMss
XED_IFORM_UCOMISS_XMMss_XMMss
XED_IFORM_UD0
XED_IFORM_UD0_GPR32_GPR32
XED_IFORM_UD0_GPR32_MEMd
XED_IFORM_UD2
XED_IFORM_UD1_GPR32_GPR32
XED_IFORM_UD1_GPR32_MEMd
XED_IFORM_UIRET
XED_IFORM_UMONITOR_GPRa
XED_IFORM_UMWAIT_GPR32
XED_IFORM_UNPCKHPD_XMMpd_MEMdq
XED_IFORM_UNPCKHPD_XMMpd_XMMq
XED_IFORM_UNPCKHPS_XMMps_MEMdq
XED_IFORM_UNPCKHPS_XMMps_XMMdq
XED_IFORM_UNPCKLPD_XMMpd_MEMdq
XED_IFORM_UNPCKLPD_XMMpd_XMMq
XED_IFORM_UNPCKLPS_XMMps_MEMdq
XED_IFORM_UNPCKLPS_XMMps_XMMq
XED_IFORM_URDMSR_GPR64u64_GPR64u64
XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX
XED_IFORM_URDMSR_GPR64u64_IMM32
XED_IFORM_URDMSR_GPR64u64_IMM32_APX
XED_IFORM_UWRMSR_GPR64u64_GPR64u64
XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX
XED_IFORM_UWRMSR_IMM32_GPR64u64
XED_IFORM_UWRMSR_IMM32_GPR64u64_APX
XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq
XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq
XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd
XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd
XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq
XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq
XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512
XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512
XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512
XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq
XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq
XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512
XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512
XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128
XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512
XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128
XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512
XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512
XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512
XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq
XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq
XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512
XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512
XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512
XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq
XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq
XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512
XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512
XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128
XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512
XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128
XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512
XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512
XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512
XED_IFORM_VAESIMC_XMMdq_MEMdq
XED_IFORM_VAESIMC_XMMdq_XMMdq
XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb
XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb
XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16
XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16
XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16
XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16
XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VBROADCASTF128_YMMqq_MEMdq
XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VBROADCASTI128_YMMqq_MEMdq
XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VBROADCASTSD_YMMqq_MEMq
XED_IFORM_VBROADCASTSD_YMMqq_XMMdq
XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VBROADCASTSS_XMMdq_MEMd
XED_IFORM_VBROADCASTSS_XMMdq_XMMdq
XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VBROADCASTSS_YMMqq_MEMd
XED_IFORM_VBROADCASTSS_YMMqq_XMMdq
XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb
XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb
XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb
XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb
XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512
XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512
XED_IFORM_VCOMISD_XMMq_MEMq
XED_IFORM_VCOMISD_XMMq_XMMq
XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512
XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512
XED_IFORM_VCOMISS_XMMd_MEMd
XED_IFORM_VCOMISS_XMMd_XMMd
XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512
XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTDQ2PD_XMMdq_MEMq
XED_IFORM_VCVTDQ2PD_XMMdq_XMMq
XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512
XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512
XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq
XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq
XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512
XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512
XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq
XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq
XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512
XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512
XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq
XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq
XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512
XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128
XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256
XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512
XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16
XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16
XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16
XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16
XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16
XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16
XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16
XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256
XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32
XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32
XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512
XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq
XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq
XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq
XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTPD2PS_XMMdq_MEMdq
XED_IFORM_VCVTPD2PS_XMMdq_MEMqq
XED_IFORM_VCVTPD2PS_XMMdq_XMMdq
XED_IFORM_VCVTPD2PS_XMMdq_YMMqq
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2PS_XMMdq_MEMq
XED_IFORM_VCVTPH2PS_XMMdq_XMMq
XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2PS_YMMqq_MEMdq
XED_IFORM_VCVTPH2PS_YMMqq_XMMdq
XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq
XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq
XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq
XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq
XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTPS2PD_XMMdq_MEMq
XED_IFORM_VCVTPS2PD_XMMdq_XMMq
XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2PD_YMMqq_MEMdq
XED_IFORM_VCVTPS2PD_YMMqq_XMMdq
XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512
XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb
XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb
XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb
XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VCVTSD2SI_GPR32d_MEMq
XED_IFORM_VCVTSD2SI_GPR32d_XMMq
XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512
XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512
XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512
XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512
XED_IFORM_VCVTSD2SI_GPR64q_MEMq
XED_IFORM_VCVTSD2SI_GPR64q_XMMq
XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq
XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq
XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512
XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512
XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512
XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512
XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512
XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512
XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512
XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512
XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512
XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512
XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512
XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512
XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512
XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512
XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512
XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd
XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd
XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512
XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512
XED_IFORM_VCVTSS2SI_GPR32d_MEMd
XED_IFORM_VCVTSS2SI_GPR32d_XMMd
XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512
XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512
XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512
XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512
XED_IFORM_VCVTSS2SI_GPR64q_MEMd
XED_IFORM_VCVTSS2SI_GPR64q_XMMd
XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512
XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512
XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512
XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512
XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq
XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq
XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq
XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq
XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq
XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq
XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq
XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
XED_IFORM_VCVTTSD2SI_GPR32d_MEMq
XED_IFORM_VCVTTSD2SI_GPR32d_XMMq
XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512
XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512
XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512
XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512
XED_IFORM_VCVTTSD2SI_GPR64q_MEMq
XED_IFORM_VCVTTSD2SI_GPR64q_XMMq
XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512
XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512
XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512
XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512
XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512
XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512
XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512
XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512
XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512
XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512
XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512
XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512
XED_IFORM_VCVTTSS2SI_GPR32d_MEMd
XED_IFORM_VCVTTSS2SI_GPR32d_XMMd
XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512
XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512
XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512
XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512
XED_IFORM_VCVTTSS2SI_GPR64q_MEMd
XED_IFORM_VCVTTSS2SI_GPR64q_XMMd
XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512
XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512
XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512
XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512
XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512
XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512
XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512
XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512
XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512
XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512
XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512
XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512
XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512
XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512
XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512
XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512
XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512
XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512
XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512
XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512
XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512
XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512
XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512
XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512
XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512
XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512
XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512
XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq
XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq
XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd
XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd
XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VERR_GPR16
XED_IFORM_VERR_MEMw
XED_IFORM_VERW_GPR16
XED_IFORM_VERW_MEMw
XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb
XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb
XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb
XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb
XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb
XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512
XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb
XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512
XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq
XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq
XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq
XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd
XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd
XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd
XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq
XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq
XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd
XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd
XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq
XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq
XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq
XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd
XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd
XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd
XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq
XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq
XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq
XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd
XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd
XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd
XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq
XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq
XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd
XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd
XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VFRCZPD_XMMdq_MEMdq
XED_IFORM_VFRCZPD_XMMdq_XMMdq
XED_IFORM_VFRCZPD_YMMqq_MEMqq
XED_IFORM_VFRCZPD_YMMqq_YMMqq
XED_IFORM_VFRCZPS_XMMdq_MEMdq
XED_IFORM_VFRCZPS_XMMdq_XMMdq
XED_IFORM_VFRCZPS_YMMqq_MEMqq
XED_IFORM_VFRCZPS_YMMqq_YMMqq
XED_IFORM_VFRCZSD_XMMdq_MEMq
XED_IFORM_VFRCZSD_XMMdq_XMMq
XED_IFORM_VFRCZSS_XMMdq_MEMd
XED_IFORM_VFRCZSS_XMMdq_XMMd
XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128
XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256
XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128
XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256
XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256
XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512
XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128
XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256
XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256
XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128
XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256
XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512
XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512
XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512
XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8
XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8
XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8
XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8
XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8
XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8
XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8
XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8
XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8
XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb
XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb
XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb
XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb
XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb
XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VLDDQU_XMMdq_MEMdq
XED_IFORM_VLDDQU_YMMqq_MEMqq
XED_IFORM_VLDMXCSR_MEMd
XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub
XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq
XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq
XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq
XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq
XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq
XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq
XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd
XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd
XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMCALL
XED_IFORM_VMCLEAR_MEMq
XED_IFORM_VMFUNC
XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq
XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq
XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd
XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd
XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMLAUNCH
XED_IFORM_VMLOAD_ArAX
XED_IFORM_VMMCALL
XED_IFORM_VMOVAPD_MEMdq_XMMdq
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VMOVAPD_MEMqq_YMMqq
XED_IFORM_VMOVAPD_XMMdq_MEMdq
XED_IFORM_VMOVAPD_XMMdq_XMMdq_28
XED_IFORM_VMOVAPD_XMMdq_XMMdq_29
XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VMOVAPD_YMMqq_MEMqq
XED_IFORM_VMOVAPD_YMMqq_YMMqq_28
XED_IFORM_VMOVAPD_YMMqq_YMMqq_29
XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VMOVAPS_MEMdq_XMMdq
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVAPS_MEMqq_YMMqq
XED_IFORM_VMOVAPS_XMMdq_MEMdq
XED_IFORM_VMOVAPS_XMMdq_XMMdq_28
XED_IFORM_VMOVAPS_XMMdq_XMMdq_29
XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVAPS_YMMqq_MEMqq
XED_IFORM_VMOVAPS_YMMqq_YMMqq_28
XED_IFORM_VMOVAPS_YMMqq_YMMqq_29
XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVDDUP_XMMdq_MEMq
XED_IFORM_VMOVDDUP_XMMdq_XMMq
XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VMOVDDUP_YMMqq_MEMqq
XED_IFORM_VMOVDDUP_YMMqq_YMMqq
XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VMOVDQA_MEMdq_XMMdq
XED_IFORM_VMOVDQA_MEMqq_YMMqq
XED_IFORM_VMOVDQA_XMMdq_MEMdq
XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F
XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F
XED_IFORM_VMOVDQA_YMMqq_MEMqq
XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F
XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VMOVDQU_MEMdq_XMMdq
XED_IFORM_VMOVDQU_MEMqq_YMMqq
XED_IFORM_VMOVDQU_XMMdq_MEMdq
XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F
XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F
XED_IFORM_VMOVDQU_YMMqq_MEMqq
XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F
XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F
XED_IFORM_VMOVD_GPR32d_XMMd
XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512
XED_IFORM_VMOVD_MEMd_XMMd
XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512
XED_IFORM_VMOVD_XMMdq_GPR32d
XED_IFORM_VMOVD_XMMdq_MEMd
XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512
XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512
XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512
XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512
XED_IFORM_VMOVHPD_MEMq_XMMdq
XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq
XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512
XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512
XED_IFORM_VMOVHPS_MEMq_XMMdq
XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq
XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512
XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq
XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512
XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512
XED_IFORM_VMOVLPD_MEMq_XMMq
XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq
XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512
XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512
XED_IFORM_VMOVLPS_MEMq_XMMq
XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq
XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512
XED_IFORM_VMOVMSKPD_GPR32d_XMMdq
XED_IFORM_VMOVMSKPD_GPR32d_YMMqq
XED_IFORM_VMOVMSKPS_GPR32d_XMMdq
XED_IFORM_VMOVMSKPS_GPR32d_YMMqq
XED_IFORM_VMOVNTDQA_XMMdq_MEMdq
XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512
XED_IFORM_VMOVNTDQA_YMMqq_MEMqq
XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512
XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512
XED_IFORM_VMOVNTDQ_MEMdq_XMMdq
XED_IFORM_VMOVNTDQ_MEMqq_YMMqq
XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512
XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512
XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512
XED_IFORM_VMOVNTPD_MEMdq_XMMdq
XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512
XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512
XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512
XED_IFORM_VMOVNTPD_MEMqq_YMMqq
XED_IFORM_VMOVNTPS_MEMdq_XMMdq
XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512
XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512
XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512
XED_IFORM_VMOVNTPS_MEMqq_YMMqq
XED_IFORM_VMOVQ_GPR64q_XMMq
XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512
XED_IFORM_VMOVQ_MEMq_XMMq_7E
XED_IFORM_VMOVQ_MEMq_XMMq_D6
XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512
XED_IFORM_VMOVQ_XMMdq_GPR64q
XED_IFORM_VMOVQ_XMMdq_MEMq_6E
XED_IFORM_VMOVQ_XMMdq_MEMq_7E
XED_IFORM_VMOVQ_XMMdq_XMMq_7E
XED_IFORM_VMOVQ_XMMdq_XMMq_D6
XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512
XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512
XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512
XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVSD_MEMq_XMMq
XED_IFORM_VMOVSD_XMMdq_MEMq
XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10
XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11
XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMOVSHDUP_XMMdq_MEMdq
XED_IFORM_VMOVSHDUP_XMMdq_XMMdq
XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVSHDUP_YMMqq_MEMqq
XED_IFORM_VMOVSHDUP_YMMqq_YMMqq
XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512
XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMOVSLDUP_XMMdq_MEMdq
XED_IFORM_VMOVSLDUP_XMMdq_XMMdq
XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVSLDUP_YMMqq_MEMqq
XED_IFORM_VMOVSLDUP_YMMqq_YMMqq
XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVSS_MEMd_XMMd
XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVSS_XMMdq_MEMd
XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10
XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11
XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMOVUPD_MEMdq_XMMdq
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VMOVUPD_MEMqq_YMMqq
XED_IFORM_VMOVUPD_XMMdq_MEMdq
XED_IFORM_VMOVUPD_XMMdq_XMMdq_10
XED_IFORM_VMOVUPD_XMMdq_XMMdq_11
XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VMOVUPD_YMMqq_MEMqq
XED_IFORM_VMOVUPD_YMMqq_YMMqq_10
XED_IFORM_VMOVUPD_YMMqq_YMMqq_11
XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VMOVUPS_MEMdq_XMMdq
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVUPS_MEMqq_YMMqq
XED_IFORM_VMOVUPS_XMMdq_MEMdq
XED_IFORM_VMOVUPS_XMMdq_XMMdq_10
XED_IFORM_VMOVUPS_XMMdq_XMMdq_11
XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VMOVUPS_YMMqq_MEMqq
XED_IFORM_VMOVUPS_YMMqq_YMMqq_10
XED_IFORM_VMOVUPS_YMMqq_YMMqq_11
XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512
XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512
XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512
XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512
XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VMPTRLD_MEMq
XED_IFORM_VMPTRST_MEMq
XED_IFORM_VMREAD_GPR32_GPR32
XED_IFORM_VMREAD_GPR64_GPR64
XED_IFORM_VMREAD_MEMd_GPR32
XED_IFORM_VMREAD_MEMq_GPR64
XED_IFORM_VMRESUME
XED_IFORM_VMRUN_ArAX
XED_IFORM_VMSAVE
XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq
XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq
XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd
XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd
XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VMWRITE_GPR32_GPR32
XED_IFORM_VMWRITE_GPR32_MEMd
XED_IFORM_VMWRITE_GPR64_GPR64
XED_IFORM_VMWRITE_GPR64_MEMq
XED_IFORM_VMXOFF
XED_IFORM_VMXON_MEMq
XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
XED_IFORM_VPABSB_XMMdq_MEMdq
XED_IFORM_VPABSB_XMMdq_XMMdq
XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512
XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512
XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512
XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512
XED_IFORM_VPABSB_YMMqq_MEMqq
XED_IFORM_VPABSB_YMMqq_YMMqq
XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512
XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512
XED_IFORM_VPABSD_XMMdq_MEMdq
XED_IFORM_VPABSD_XMMdq_XMMdq
XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512
XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512
XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512
XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512
XED_IFORM_VPABSD_YMMqq_MEMqq
XED_IFORM_VPABSD_YMMqq_YMMqq
XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512
XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512
XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512
XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512
XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512
XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512
XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512
XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPABSW_XMMdq_MEMdq
XED_IFORM_VPABSW_XMMdq_XMMdq
XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512
XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512
XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512
XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512
XED_IFORM_VPABSW_YMMqq_MEMqq
XED_IFORM_VPABSW_YMMqq_YMMqq
XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512
XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512
XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512
XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512
XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512
XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512
XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512
XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512
XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq
XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq
XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq
XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq
XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq
XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq
XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq
XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq
XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPBROADCASTB_XMMdq_MEMb
XED_IFORM_VPBROADCASTB_XMMdq_XMMb
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPBROADCASTB_YMMqq_MEMb
XED_IFORM_VPBROADCASTB_YMMqq_XMMb
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPBROADCASTD_XMMdq_MEMd
XED_IFORM_VPBROADCASTD_XMMdq_XMMd
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPBROADCASTD_YMMqq_MEMd
XED_IFORM_VPBROADCASTD_YMMqq_XMMd
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512
XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512
XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD
XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512
XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512
XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD
XED_IFORM_VPBROADCASTQ_XMMdq_MEMq
XED_IFORM_VPBROADCASTQ_XMMdq_XMMq
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPBROADCASTQ_YMMqq_MEMq
XED_IFORM_VPBROADCASTQ_YMMqq_XMMq
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPBROADCASTW_XMMdq_MEMw
XED_IFORM_VPBROADCASTW_XMMdq_XMMw
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPBROADCASTW_YMMqq_MEMw
XED_IFORM_VPBROADCASTW_YMMqq_XMMw
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq
XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512
XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512
XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb
XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512
XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8
XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8
XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8
XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8
XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8
XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8
XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8
XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8
XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8
XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8
XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8
XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8
XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8
XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8
XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8
XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8
XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32
XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32
XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32
XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32
XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32
XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32
XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32
XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32
XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8
XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8
XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8
XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8
XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8
XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8
XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8
XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8
XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32
XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32
XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32
XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32
XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32
XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32
XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32
XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32
XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16
XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16
XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16
XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16
XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16
XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16
XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16
XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16
XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16
XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16
XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16
XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16
XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16
XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16
XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16
XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16
XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16
XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16
XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16
XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16
XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16
XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16
XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16
XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16
XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb
XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb
XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb
XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb
XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb
XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb
XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb
XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512
XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb
XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512
XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb
XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb
XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb
XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512
XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb
XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15
XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5
XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512
XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb
XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128
XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256
XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256
XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512
XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128
XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256
XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256
XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128
XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256
XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512
XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128
XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256
XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
XED_IFORM_VPHADDBD_XMMdq_MEMdq
XED_IFORM_VPHADDBD_XMMdq_XMMdq
XED_IFORM_VPHADDBQ_XMMdq_MEMdq
XED_IFORM_VPHADDBQ_XMMdq_XMMdq
XED_IFORM_VPHADDBW_XMMdq_MEMdq
XED_IFORM_VPHADDBW_XMMdq_XMMdq
XED_IFORM_VPHADDDQ_XMMdq_MEMdq
XED_IFORM_VPHADDDQ_XMMdq_XMMdq
XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPHADDUBD_XMMdq_MEMdq
XED_IFORM_VPHADDUBD_XMMdq_XMMdq
XED_IFORM_VPHADDUBQ_XMMdq_MEMdq
XED_IFORM_VPHADDUBQ_XMMdq_XMMdq
XED_IFORM_VPHADDUBW_XMMdq_MEMdq
XED_IFORM_VPHADDUBW_XMMdq_XMMdq
XED_IFORM_VPHADDUDQ_XMMdq_MEMdq
XED_IFORM_VPHADDUDQ_XMMdq_XMMdq
XED_IFORM_VPHADDUWD_XMMdq_MEMdq
XED_IFORM_VPHADDUWD_XMMdq_XMMdq
XED_IFORM_VPHADDUWQ_XMMdq_MEMdq
XED_IFORM_VPHADDUWQ_XMMdq_XMMdq
XED_IFORM_VPHADDWD_XMMdq_MEMdq
XED_IFORM_VPHADDWD_XMMdq_XMMdq
XED_IFORM_VPHADDWQ_XMMdq_MEMdq
XED_IFORM_VPHADDWQ_XMMdq_XMMdq
XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq
XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq
XED_IFORM_VPHSUBBW_XMMdq_MEMdq
XED_IFORM_VPHSUBBW_XMMdq_XMMdq
XED_IFORM_VPHSUBDQ_XMMdq_MEMdq
XED_IFORM_VPHSUBDQ_XMMdq_XMMdq
XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPHSUBWD_XMMdq_MEMdq
XED_IFORM_VPHSUBWD_XMMdq_XMMdq
XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb
XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb
XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512
XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb
XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb
XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb
XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb
XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512
XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb
XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb
XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512
XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64
XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64
XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64
XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64
XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64
XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64
XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64
XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64
XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq
XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq
XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq
XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq
XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512
XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512
XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512
XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512
XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512
XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512
XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512
XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512
XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512
XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512
XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512
XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512
XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512
XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512
XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512
XED_IFORM_VPMOVMSKB_GPR32d_XMMdq
XED_IFORM_VPMOVMSKB_GPR32d_YMMqq
XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512
XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512
XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512
XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512
XED_IFORM_VPMOVSXBD_XMMdq_MEMd
XED_IFORM_VPMOVSXBD_XMMdq_XMMd
XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBD_YMMqq_MEMq
XED_IFORM_VPMOVSXBD_YMMqq_XMMq
XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBQ_XMMdq_MEMw
XED_IFORM_VPMOVSXBQ_XMMdq_XMMw
XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBQ_YMMqq_MEMd
XED_IFORM_VPMOVSXBQ_YMMqq_XMMd
XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBW_XMMdq_MEMq
XED_IFORM_VPMOVSXBW_XMMdq_XMMq
XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVSXBW_YMMqq_MEMdq
XED_IFORM_VPMOVSXBW_YMMqq_XMMdq
XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512
XED_IFORM_VPMOVSXDQ_XMMdq_MEMq
XED_IFORM_VPMOVSXDQ_XMMdq_XMMq
XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq
XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq
XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVSXWD_XMMdq_MEMq
XED_IFORM_VPMOVSXWD_XMMdq_XMMq
XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSXWD_YMMqq_MEMdq
XED_IFORM_VPMOVSXWD_YMMqq_XMMdq
XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512
XED_IFORM_VPMOVSXWQ_XMMdq_MEMd
XED_IFORM_VPMOVSXWQ_XMMdq_XMMd
XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVSXWQ_YMMqq_MEMq
XED_IFORM_VPMOVSXWQ_YMMqq_XMMq
XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512
XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512
XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512
XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512
XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512
XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512
XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512
XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512
XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPMOVZXBD_XMMdq_MEMd
XED_IFORM_VPMOVZXBD_XMMdq_XMMd
XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBD_YMMqq_MEMq
XED_IFORM_VPMOVZXBD_YMMqq_XMMq
XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBQ_XMMdq_MEMw
XED_IFORM_VPMOVZXBQ_XMMdq_XMMw
XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBQ_YMMqq_MEMd
XED_IFORM_VPMOVZXBQ_YMMqq_XMMd
XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBW_XMMdq_MEMq
XED_IFORM_VPMOVZXBW_XMMdq_XMMq
XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512
XED_IFORM_VPMOVZXBW_YMMqq_MEMdq
XED_IFORM_VPMOVZXBW_YMMqq_XMMdq
XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512
XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512
XED_IFORM_VPMOVZXDQ_XMMdq_MEMq
XED_IFORM_VPMOVZXDQ_XMMdq_XMMq
XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512
XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq
XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq
XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
XED_IFORM_VPMOVZXWD_XMMdq_MEMq
XED_IFORM_VPMOVZXWD_XMMdq_XMMq
XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVZXWD_YMMqq_MEMdq
XED_IFORM_VPMOVZXWD_YMMqq_XMMdq
XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512
XED_IFORM_VPMOVZXWQ_XMMdq_MEMd
XED_IFORM_VPMOVZXWQ_XMMdq_XMMd
XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMOVZXWQ_YMMqq_MEMq
XED_IFORM_VPMOVZXWQ_YMMqq_XMMq
XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512
XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512
XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512
XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512
XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512
XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512
XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512
XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512
XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512
XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512
XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512
XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512
XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512
XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512
XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512
XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512
XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512
XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512
XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512
XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512
XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512
XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512
XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512
XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512
XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512
XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512
XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq
XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq
XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq
XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq
XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq
XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq
XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq
XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb
XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq
XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb
XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb
XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq
XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb
XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb
XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq
XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb
XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb
XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq
XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb
XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512
XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512
XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512
XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512
XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512
XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq
XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512
XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb
XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb
XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb
XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb
XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb
XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb
XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb
XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb
XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb
XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb
XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb
XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb
XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb
XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512
XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb
XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512
XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512
XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb
XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb
XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq
XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb
XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb
XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb
XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb
XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq
XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq
XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq
XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512
XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512
XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512
XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512
XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq
XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb
XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb
XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq
XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq
XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPTEST_XMMdq_MEMdq
XED_IFORM_VPTEST_XMMdq_XMMdq
XED_IFORM_VPTEST_YMMqq_MEMqq
XED_IFORM_VPTEST_YMMqq_YMMqq
XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq
XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq
XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq
XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq
XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq
XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq
XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq
XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq
XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512
XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512
XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VRCPPS_XMMdq_MEMdq
XED_IFORM_VRCPPS_XMMdq_XMMdq
XED_IFORM_VRCPPS_YMMqq_MEMqq
XED_IFORM_VRCPPS_YMMqq_YMMqq
XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd
XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd
XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb
XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb
XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb
XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb
XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb
XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb
XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb
XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb
XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb
XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb
XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb
XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb
XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VRSQRTPS_XMMdq_MEMdq
XED_IFORM_VRSQRTPS_XMMdq_XMMdq
XED_IFORM_VRSQRTPS_YMMqq_MEMqq
XED_IFORM_VRSQRTPS_YMMqq_YMMqq
XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd
XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd
XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512
XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512
XED_IFORM_VSHA512MSG1_YMMu64_XMMu64
XED_IFORM_VSHA512MSG2_YMMu64_YMMu64
XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64
XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb
XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb
XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb
XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb
XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32
XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32
XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32
XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32
XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8
XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32
XED_IFORM_VSQRTPD_XMMdq_MEMdq
XED_IFORM_VSQRTPD_XMMdq_XMMdq
XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512
XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512
XED_IFORM_VSQRTPD_YMMqq_MEMqq
XED_IFORM_VSQRTPD_YMMqq_YMMqq
XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512
XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
XED_IFORM_VSQRTPS_XMMdq_MEMdq
XED_IFORM_VSQRTPS_XMMdq_XMMdq
XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512
XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512
XED_IFORM_VSQRTPS_YMMqq_MEMqq
XED_IFORM_VSQRTPS_YMMqq_YMMqq
XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512
XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq
XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq
XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd
XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd
XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VSTMXCSR_MEMd
XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq
XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq
XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd
XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd
XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VTESTPD_XMMdq_MEMdq
XED_IFORM_VTESTPD_XMMdq_XMMdq
XED_IFORM_VTESTPD_YMMqq_MEMqq
XED_IFORM_VTESTPD_YMMqq_YMMqq
XED_IFORM_VTESTPS_XMMdq_MEMdq
XED_IFORM_VTESTPS_XMMdq_XMMdq
XED_IFORM_VTESTPS_YMMqq_MEMqq
XED_IFORM_VTESTPS_YMMqq_YMMqq
XED_IFORM_VUCOMISD_XMMdq_MEMq
XED_IFORM_VUCOMISD_XMMdq_XMMq
XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512
XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512
XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512
XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512
XED_IFORM_VUCOMISS_XMMdq_MEMd
XED_IFORM_VUCOMISS_XMMdq_XMMd
XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512
XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512
XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq
XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq
XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq
XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq
XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq
XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq
XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq
XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq
XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
XED_IFORM_VZEROALL
XED_IFORM_VZEROUPPER
XED_IFORM_WBINVD
XED_IFORM_WBNOINVD
XED_IFORM_WRFSBASE_GPRy
XED_IFORM_WRGSBASE_GPRy
XED_IFORM_WRMSR
XED_IFORM_WRMSRLIST
XED_IFORM_WRMSRNS
XED_IFORM_WRPKRU
XED_IFORM_WRSSD_MEMu32_GPR32u32
XED_IFORM_WRSSD_MEMu32_GPR32u32_APX
XED_IFORM_WRSSQ_MEMu64_GPR64u64
XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX
XED_IFORM_WRUSSD_MEMu32_GPR32u32
XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX
XED_IFORM_WRUSSQ_MEMu64_GPR64u64
XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX
XED_IFORM_XABORT_IMMb
XED_IFORM_XADD_GPR8_GPR8
XED_IFORM_XADD_GPRv_GPRv
XED_IFORM_XADD_LOCK_MEMb_GPR8
XED_IFORM_XADD_LOCK_MEMv_GPRv
XED_IFORM_XADD_MEMb_GPR8
XED_IFORM_XADD_MEMv_GPRv
XED_IFORM_XBEGIN_RELBRz
XED_IFORM_XCHG_GPR8_GPR8
XED_IFORM_XCHG_GPRv_GPRv
XED_IFORM_XCHG_GPRv_OrAX
XED_IFORM_XCHG_MEMb_GPR8
XED_IFORM_XCHG_MEMv_GPRv
XED_IFORM_XEND
XED_IFORM_XGETBV
XED_IFORM_XLAT
XED_IFORM_XORPD_XMMxuq_MEMxuq
XED_IFORM_XORPD_XMMxuq_XMMxuq
XED_IFORM_XORPS_XMMxud_MEMxud
XED_IFORM_XORPS_XMMxud_XMMxud
XED_IFORM_XOR_AL_IMMb
XED_IFORM_XOR_GPR8_GPR8_30
XED_IFORM_XOR_GPR8_GPR8_32
XED_IFORM_XOR_GPR8_IMMb_80r6
XED_IFORM_XOR_GPR8_IMMb_82r6
XED_IFORM_XOR_GPR8_MEMb
XED_IFORM_XOR_GPR8i8_GPR8i8_APX
XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX
XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX
XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX
XED_IFORM_XOR_GPR8i8_IMM8_APX
XED_IFORM_XOR_GPR8i8_MEMi8_APX
XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX
XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX
XED_IFORM_XOR_GPRv_GPRv_31
XED_IFORM_XOR_GPRv_GPRv_33
XED_IFORM_XOR_GPRv_GPRv_APX
XED_IFORM_XOR_GPRv_GPRv_GPRv_APX
XED_IFORM_XOR_GPRv_GPRv_IMM8_APX
XED_IFORM_XOR_GPRv_GPRv_IMMz_APX
XED_IFORM_XOR_GPRv_GPRv_MEMv_APX
XED_IFORM_XOR_GPRv_IMM8_APX
XED_IFORM_XOR_GPRv_IMMb
XED_IFORM_XOR_GPRv_IMMz
XED_IFORM_XOR_GPRv_IMMz_APX
XED_IFORM_XOR_GPRv_MEMv
XED_IFORM_XOR_GPRv_MEMv_APX
XED_IFORM_XOR_GPRv_MEMv_GPRv_APX
XED_IFORM_XOR_GPRv_MEMv_IMM8_APX
XED_IFORM_XOR_GPRv_MEMv_IMMz_APX
XED_IFORM_XOR_LOCK_MEMb_GPR8
XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6
XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6
XED_IFORM_XOR_LOCK_MEMv_GPRv
XED_IFORM_XOR_LOCK_MEMv_IMMb
XED_IFORM_XOR_LOCK_MEMv_IMMz
XED_IFORM_XOR_MEMb_GPR8
XED_IFORM_XOR_MEMb_IMMb_80r6
XED_IFORM_XOR_MEMb_IMMb_82r6
XED_IFORM_XOR_MEMi8_GPR8i8_APX
XED_IFORM_XOR_MEMi8_IMM8_APX
XED_IFORM_XOR_MEMv_GPRv
XED_IFORM_XOR_MEMv_GPRv_APX
XED_IFORM_XOR_MEMv_IMM8_APX
XED_IFORM_XOR_MEMv_IMMb
XED_IFORM_XOR_MEMv_IMMz
XED_IFORM_XOR_MEMv_IMMz_APX
XED_IFORM_XOR_OrAX_IMMz
XED_IFORM_XRESLDTRK
XED_IFORM_XRSTOR64_MEMmxsave
XED_IFORM_XRSTORS64_MEMmxsave
XED_IFORM_XRSTORS_MEMmxsave
XED_IFORM_XRSTOR_MEMmxsave
XED_IFORM_XSAVE64_MEMmxsave
XED_IFORM_XSAVEC64_MEMmxsave
XED_IFORM_XSAVEC_MEMmxsave
XED_IFORM_XSAVEOPT64_MEMmxsave
XED_IFORM_XSAVEOPT_MEMmxsave
XED_IFORM_XSAVES64_MEMmxsave
XED_IFORM_XSAVES_MEMmxsave
XED_IFORM_XSAVE_MEMmxsave
XED_IFORM_XSETBV
XED_IFORM_XSTORE
XED_IFORM_XSUSLDTRK
XED_IFORM_XTEST
XED_INFO2_VERBOSE
XED_INFO_VERBOSE
XED_ISA_SET_3DNOW
XED_ISA_SET_ADOX_ADCX
XED_ISA_SET_AES
XED_ISA_SET_AMD
XED_ISA_SET_AMD_INVLPGB
XED_ISA_SET_AMX_BF16
XED_ISA_SET_AMX_COMPLEX
XED_ISA_SET_AMX_FP16
XED_ISA_SET_AMX_INT8
XED_ISA_SET_AMX_TILE
XED_ISA_SET_APX_F
XED_ISA_SET_APX_F_ADX
XED_ISA_SET_APX_F_AMX
XED_ISA_SET_APX_F_BMI1
XED_ISA_SET_APX_F_BMI2
XED_ISA_SET_APX_F_CET
XED_ISA_SET_APX_F_CMPCCXADD
XED_ISA_SET_APX_F_ENQCMD
XED_ISA_SET_APX_F_INVPCID
XED_ISA_SET_APX_F_KOPB
XED_ISA_SET_APX_F_KOPD
XED_ISA_SET_APX_F_KOPQ
XED_ISA_SET_APX_F_KOPW
XED_ISA_SET_APX_F_LZCNT
XED_ISA_SET_APX_F_MOVBE
XED_ISA_SET_APX_F_MOVDIR64B
XED_ISA_SET_APX_F_MOVDIRI
XED_ISA_SET_APX_F_POPCNT
XED_ISA_SET_APX_F_RAO_INT
XED_ISA_SET_APX_F_USER_MSR
XED_ISA_SET_APX_F_VMX
XED_ISA_SET_AVX
XED_ISA_SET_AVX2
XED_ISA_SET_AVX2GATHER
XED_ISA_SET_AVX512BW_128
XED_ISA_SET_AVX512BW_256
XED_ISA_SET_AVX512BW_512
XED_ISA_SET_AVX512BW_128N
XED_ISA_SET_AVX512BW_KOPD
XED_ISA_SET_AVX512BW_KOPQ
XED_ISA_SET_AVX512CD_128
XED_ISA_SET_AVX512CD_256
XED_ISA_SET_AVX512CD_512
XED_ISA_SET_AVX512DQ_128
XED_ISA_SET_AVX512DQ_256
XED_ISA_SET_AVX512DQ_512
XED_ISA_SET_AVX512DQ_128N
XED_ISA_SET_AVX512DQ_KOPB
XED_ISA_SET_AVX512DQ_KOPW
XED_ISA_SET_AVX512DQ_SCALAR
XED_ISA_SET_AVX512ER_512
XED_ISA_SET_AVX512ER_SCALAR
XED_ISA_SET_AVX512F_128
XED_ISA_SET_AVX512F_256
XED_ISA_SET_AVX512F_512
XED_ISA_SET_AVX512F_128N
XED_ISA_SET_AVX512F_KOPW
XED_ISA_SET_AVX512F_SCALAR
XED_ISA_SET_AVX512PF_512
XED_ISA_SET_AVX512_4FMAPS_512
XED_ISA_SET_AVX512_4FMAPS_SCALAR
XED_ISA_SET_AVX512_4VNNIW_512
XED_ISA_SET_AVX512_BF16_128
XED_ISA_SET_AVX512_BF16_256
XED_ISA_SET_AVX512_BF16_512
XED_ISA_SET_AVX512_BITALG_128
XED_ISA_SET_AVX512_BITALG_256
XED_ISA_SET_AVX512_BITALG_512
XED_ISA_SET_AVX512_FP16_128
XED_ISA_SET_AVX512_FP16_256
XED_ISA_SET_AVX512_FP16_512
XED_ISA_SET_AVX512_FP16_128N
XED_ISA_SET_AVX512_FP16_SCALAR
XED_ISA_SET_AVX512_GFNI_128
XED_ISA_SET_AVX512_GFNI_256
XED_ISA_SET_AVX512_GFNI_512
XED_ISA_SET_AVX512_IFMA_128
XED_ISA_SET_AVX512_IFMA_256
XED_ISA_SET_AVX512_IFMA_512
XED_ISA_SET_AVX512_VAES_128
XED_ISA_SET_AVX512_VAES_256
XED_ISA_SET_AVX512_VAES_512
XED_ISA_SET_AVX512_VBMI2_128
XED_ISA_SET_AVX512_VBMI2_256
XED_ISA_SET_AVX512_VBMI2_512
XED_ISA_SET_AVX512_VBMI_128
XED_ISA_SET_AVX512_VBMI_256
XED_ISA_SET_AVX512_VBMI_512
XED_ISA_SET_AVX512_VNNI_128
XED_ISA_SET_AVX512_VNNI_256
XED_ISA_SET_AVX512_VNNI_512
XED_ISA_SET_AVX512_VP2INTERSECT_128
XED_ISA_SET_AVX512_VP2INTERSECT_256
XED_ISA_SET_AVX512_VP2INTERSECT_512
XED_ISA_SET_AVX512_VPCLMULQDQ_128
XED_ISA_SET_AVX512_VPCLMULQDQ_256
XED_ISA_SET_AVX512_VPCLMULQDQ_512
XED_ISA_SET_AVX512_VPOPCNTDQ_128
XED_ISA_SET_AVX512_VPOPCNTDQ_256
XED_ISA_SET_AVX512_VPOPCNTDQ_512
XED_ISA_SET_AVXAES
XED_ISA_SET_AVX_GFNI
XED_ISA_SET_AVX_IFMA
XED_ISA_SET_AVX_NE_CONVERT
XED_ISA_SET_AVX_VNNI
XED_ISA_SET_AVX_VNNI_INT8
XED_ISA_SET_AVX_VNNI_INT16
XED_ISA_SET_BMI1
XED_ISA_SET_BMI2
XED_ISA_SET_CET
XED_ISA_SET_CLDEMOTE
XED_ISA_SET_CLFLUSHOPT
XED_ISA_SET_CLFSH
XED_ISA_SET_CLWB
XED_ISA_SET_CLZERO
XED_ISA_SET_CMOV
XED_ISA_SET_CMPCCXADD
XED_ISA_SET_CMPXCHG16B
XED_ISA_SET_ENQCMD
XED_ISA_SET_F16C
XED_ISA_SET_FAT_NOP
XED_ISA_SET_FCMOV
XED_ISA_SET_FCOMI
XED_ISA_SET_FMA
XED_ISA_SET_FMA4
XED_ISA_SET_FRED
XED_ISA_SET_FXSAVE
XED_ISA_SET_FXSAVE64
XED_ISA_SET_GFNI
XED_ISA_SET_HRESET
XED_ISA_SET_I86
XED_ISA_SET_I186
XED_ISA_SET_I386
XED_ISA_SET_I486
XED_ISA_SET_I286PROTECTED
XED_ISA_SET_I286REAL
XED_ISA_SET_I486REAL
XED_ISA_SET_ICACHE_PREFETCH
XED_ISA_SET_INVALID
XED_ISA_SET_INVPCID
XED_ISA_SET_KEYLOCKER
XED_ISA_SET_KEYLOCKER_WIDE
XED_ISA_SET_LAHF
XED_ISA_SET_LAST
XED_ISA_SET_LKGS
XED_ISA_SET_LONGMODE
XED_ISA_SET_LWP
XED_ISA_SET_LZCNT
XED_ISA_SET_MCOMMIT
XED_ISA_SET_MONITOR
XED_ISA_SET_MONITORX
XED_ISA_SET_MOVBE
XED_ISA_SET_MOVDIR64B
XED_ISA_SET_MOVDIRI
XED_ISA_SET_MPX
XED_ISA_SET_MSRLIST
XED_ISA_SET_PAUSE
XED_ISA_SET_PBNDKB
XED_ISA_SET_PCLMULQDQ
XED_ISA_SET_PCONFIG
XED_ISA_SET_PENTIUMMMX
XED_ISA_SET_PENTIUMREAL
XED_ISA_SET_PKU
XED_ISA_SET_POPCNT
XED_ISA_SET_PPRO
XED_ISA_SET_PPRO_UD0_LONG
XED_ISA_SET_PPRO_UD0_SHORT
XED_ISA_SET_PREFETCHW
XED_ISA_SET_PREFETCHWT1
XED_ISA_SET_PREFETCH_NOP
XED_ISA_SET_PTWRITE
XED_ISA_SET_RAO_INT
XED_ISA_SET_RDPID
XED_ISA_SET_RDPMC
XED_ISA_SET_RDPRU
XED_ISA_SET_RDRAND
XED_ISA_SET_RDSEED
XED_ISA_SET_RDTSCP
XED_ISA_SET_RDWRFSGS
XED_ISA_SET_RTM
XED_ISA_SET_SEP
XED_ISA_SET_SERIALIZE
XED_ISA_SET_SGX
XED_ISA_SET_SGX_ENCLV
XED_ISA_SET_SHA
XED_ISA_SET_SHA512
XED_ISA_SET_SM3
XED_ISA_SET_SM4
XED_ISA_SET_SMAP
XED_ISA_SET_SMX
XED_ISA_SET_SNP
XED_ISA_SET_SSE
XED_ISA_SET_SSE2
XED_ISA_SET_SSE3
XED_ISA_SET_SSE4
XED_ISA_SET_SSE2MMX
XED_ISA_SET_SSE3X87
XED_ISA_SET_SSE4A
XED_ISA_SET_SSE42
XED_ISA_SET_SSEMXCSR
XED_ISA_SET_SSE_PREFETCH
XED_ISA_SET_SSSE3
XED_ISA_SET_SSSE3MMX
XED_ISA_SET_SVM
XED_ISA_SET_TBM
XED_ISA_SET_TDX
XED_ISA_SET_TSX_LDTRK
XED_ISA_SET_UINTR
XED_ISA_SET_USER_MSR
XED_ISA_SET_VAES
XED_ISA_SET_VIA_PADLOCK_AES
XED_ISA_SET_VIA_PADLOCK_MONTMUL
XED_ISA_SET_VIA_PADLOCK_RNG
XED_ISA_SET_VIA_PADLOCK_SHA
XED_ISA_SET_VMFUNC
XED_ISA_SET_VPCLMULQDQ
XED_ISA_SET_VTX
XED_ISA_SET_WAITPKG
XED_ISA_SET_WBNOINVD
XED_ISA_SET_WRMSRNS
XED_ISA_SET_X87
XED_ISA_SET_XOP
XED_ISA_SET_XSAVE
XED_ISA_SET_XSAVEC
XED_ISA_SET_XSAVEOPT
XED_ISA_SET_XSAVES
XED_MACHINE_MODE_INVALID
XED_MACHINE_MODE_LAST
XED_MACHINE_MODE_LEGACY_16: < 16b protected mode
XED_MACHINE_MODE_LEGACY_32: < 32b protected mode
XED_MACHINE_MODE_LONG_64: < 64b operating mode
XED_MACHINE_MODE_LONG_COMPAT_16: < 16b protected mode
XED_MACHINE_MODE_LONG_COMPAT_32: < 32b protected mode
XED_MACHINE_MODE_REAL_16: < 16b real mode
XED_MACHINE_MODE_REAL_32: < 32b real mode (CS.D bit = 1)
XED_MAX_ATTRIBUTE_COUNT
XED_MAX_CONVERT_PATTERNS
XED_MAX_CPUID_GROUPS_PER_ISA_SET
XED_MAX_CPUID_RECS_PER_GROUP
XED_MAX_DECORATIONS_PER_OPERAND
XED_MAX_DISPLACEMENT_BYTES
XED_MAX_GLOBAL_FLAG_ACTIONS
XED_MAX_IFORMS_PER_ICLASS
XED_MAX_IMMEDIATE_BYTES
XED_MAX_INSTRUCTION_BYTES
XED_MAX_INST_TABLE_NODES
XED_MAX_MAP_EVEX
XED_MAX_MAP_VEX
XED_MAX_OPERAND_SEQUENCES
XED_MAX_OPERAND_TABLE_NODES
XED_MAX_REQUIRED_ATTRIBUTES
XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES
XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES
XED_MORE_VERBOSE
XED_NONTERMINAL_AR8
XED_NONTERMINAL_AR9
XED_NONTERMINAL_AR10
XED_NONTERMINAL_AR11
XED_NONTERMINAL_AR12
XED_NONTERMINAL_AR13
XED_NONTERMINAL_AR14
XED_NONTERMINAL_AR15
XED_NONTERMINAL_AR16
XED_NONTERMINAL_AR17
XED_NONTERMINAL_AR18
XED_NONTERMINAL_AR19
XED_NONTERMINAL_AR20
XED_NONTERMINAL_AR21
XED_NONTERMINAL_AR22
XED_NONTERMINAL_AR23
XED_NONTERMINAL_AR24
XED_NONTERMINAL_AR25
XED_NONTERMINAL_AR26
XED_NONTERMINAL_AR27
XED_NONTERMINAL_AR28
XED_NONTERMINAL_AR29
XED_NONTERMINAL_AR30
XED_NONTERMINAL_AR31
XED_NONTERMINAL_ARAX
XED_NONTERMINAL_ARBP
XED_NONTERMINAL_ARBX
XED_NONTERMINAL_ARCX
XED_NONTERMINAL_ARDI
XED_NONTERMINAL_ARDX
XED_NONTERMINAL_ARSI
XED_NONTERMINAL_ARSP
XED_NONTERMINAL_ASZ_NONTERM
XED_NONTERMINAL_AVX512_ROUND
XED_NONTERMINAL_AVX_INSTRUCTIONS
XED_NONTERMINAL_AVX_SPLITTER
XED_NONTERMINAL_A_GPR_B
XED_NONTERMINAL_A_GPR_R
XED_NONTERMINAL_BND_B
XED_NONTERMINAL_BND_B_CHECK
XED_NONTERMINAL_BND_R
XED_NONTERMINAL_BND_R_CHECK
XED_NONTERMINAL_BRANCH_HINT
XED_NONTERMINAL_BRDISP8
XED_NONTERMINAL_BRDISP32
XED_NONTERMINAL_BRDISP64
XED_NONTERMINAL_BRDISPZ
XED_NONTERMINAL_CET_NO_TRACK
XED_NONTERMINAL_CR_B
XED_NONTERMINAL_CR_R
XED_NONTERMINAL_CR_WIDTH
XED_NONTERMINAL_DF64
XED_NONTERMINAL_DFV
XED_NONTERMINAL_DR_R
XED_NONTERMINAL_ESIZE_1_BITS
XED_NONTERMINAL_ESIZE_2_BITS
XED_NONTERMINAL_ESIZE_4_BITS
XED_NONTERMINAL_ESIZE_8_BITS
XED_NONTERMINAL_ESIZE_16_BITS
XED_NONTERMINAL_ESIZE_32_BITS
XED_NONTERMINAL_ESIZE_64_BITS
XED_NONTERMINAL_ESIZE_128_BITS
XED_NONTERMINAL_EVAPX
XED_NONTERMINAL_EVAPX_SCC
XED_NONTERMINAL_EVEXR4_ONE
XED_NONTERMINAL_EVEX_INSTRUCTIONS
XED_NONTERMINAL_EVEX_SPLITTER
XED_NONTERMINAL_FINAL_DSEG
XED_NONTERMINAL_FINAL_DSEG1
XED_NONTERMINAL_FINAL_DSEG1_MODE64
XED_NONTERMINAL_FINAL_DSEG1_NOT64
XED_NONTERMINAL_FINAL_DSEG_MODE64
XED_NONTERMINAL_FINAL_DSEG_NOT64
XED_NONTERMINAL_FINAL_ESEG
XED_NONTERMINAL_FINAL_ESEG1
XED_NONTERMINAL_FINAL_SSEG
XED_NONTERMINAL_FINAL_SSEG0
XED_NONTERMINAL_FINAL_SSEG1
XED_NONTERMINAL_FINAL_SSEG_MODE64
XED_NONTERMINAL_FINAL_SSEG_NOT64
XED_NONTERMINAL_FIX_ROUND_LEN128
XED_NONTERMINAL_FIX_ROUND_LEN512
XED_NONTERMINAL_FORCE64
XED_NONTERMINAL_GPR8_B
XED_NONTERMINAL_GPR8_N
XED_NONTERMINAL_GPR8_R
XED_NONTERMINAL_GPR8_SB
XED_NONTERMINAL_GPR16_B
XED_NONTERMINAL_GPR16_N
XED_NONTERMINAL_GPR16_R
XED_NONTERMINAL_GPR16_SB
XED_NONTERMINAL_GPR32_B
XED_NONTERMINAL_GPR32_N
XED_NONTERMINAL_GPR32_R
XED_NONTERMINAL_GPR32_SB
XED_NONTERMINAL_GPR64_B
XED_NONTERMINAL_GPR64_B_NORSP
XED_NONTERMINAL_GPR64_N
XED_NONTERMINAL_GPR64_N_NORSP
XED_NONTERMINAL_GPR64_R
XED_NONTERMINAL_GPR64_SB
XED_NONTERMINAL_GPRV_B
XED_NONTERMINAL_GPRV_N
XED_NONTERMINAL_GPRV_R
XED_NONTERMINAL_GPRV_SB
XED_NONTERMINAL_GPRY_B
XED_NONTERMINAL_GPRY_R
XED_NONTERMINAL_GPRZ_B
XED_NONTERMINAL_GPRZ_R
XED_NONTERMINAL_IGNORE66
XED_NONTERMINAL_IMMUNE66
XED_NONTERMINAL_IMMUNE66_LOOP64
XED_NONTERMINAL_IMMUNE_REXW
XED_NONTERMINAL_INSTRUCTIONS
XED_NONTERMINAL_INVALID
XED_NONTERMINAL_ISA
XED_NONTERMINAL_LAST
XED_NONTERMINAL_MASK1
XED_NONTERMINAL_MASKNOT0
XED_NONTERMINAL_MASK_B
XED_NONTERMINAL_MASK_N
XED_NONTERMINAL_MASK_N32
XED_NONTERMINAL_MASK_N64
XED_NONTERMINAL_MASK_R
XED_NONTERMINAL_MEMDISP
XED_NONTERMINAL_MEMDISP8
XED_NONTERMINAL_MEMDISP16
XED_NONTERMINAL_MEMDISP32
XED_NONTERMINAL_MEMDISPV
XED_NONTERMINAL_MMX_B
XED_NONTERMINAL_MMX_R
XED_NONTERMINAL_MODRM
XED_NONTERMINAL_MODRM16
XED_NONTERMINAL_MODRM32
XED_NONTERMINAL_MODRM64ALT32
XED_NONTERMINAL_NELEM_EIGHTHMEM
XED_NONTERMINAL_NELEM_FULL
XED_NONTERMINAL_NELEM_FULLMEM
XED_NONTERMINAL_NELEM_GPR_READER
XED_NONTERMINAL_NELEM_GPR_READER_BYTE
XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD
XED_NONTERMINAL_NELEM_GPR_READER_WORD
XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP
XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D
XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q
XED_NONTERMINAL_NELEM_GPR_WRITER_STORE
XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE
XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD
XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD
XED_NONTERMINAL_NELEM_GSCAT
XED_NONTERMINAL_NELEM_HALF
XED_NONTERMINAL_NELEM_HALFMEM
XED_NONTERMINAL_NELEM_MEM128
XED_NONTERMINAL_NELEM_MOVDDUP
XED_NONTERMINAL_NELEM_QUARTER
XED_NONTERMINAL_NELEM_QUARTERMEM
XED_NONTERMINAL_NELEM_SCALAR
XED_NONTERMINAL_NELEM_TUPLE1
XED_NONTERMINAL_NELEM_TUPLE2
XED_NONTERMINAL_NELEM_TUPLE4
XED_NONTERMINAL_NELEM_TUPLE8
XED_NONTERMINAL_NELEM_TUPLE1_4X
XED_NONTERMINAL_NELEM_TUPLE1_BYTE
XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD
XED_NONTERMINAL_NELEM_TUPLE1_WORD
XED_NONTERMINAL_OEAX
XED_NONTERMINAL_ONE
XED_NONTERMINAL_ORAX
XED_NONTERMINAL_ORBP
XED_NONTERMINAL_ORBX
XED_NONTERMINAL_ORCX
XED_NONTERMINAL_ORDX
XED_NONTERMINAL_ORSP
XED_NONTERMINAL_OSZ_NONTERM
XED_NONTERMINAL_OVERRIDE_SEG0
XED_NONTERMINAL_OVERRIDE_SEG1
XED_NONTERMINAL_PREFIXES
XED_NONTERMINAL_REFINING66
XED_NONTERMINAL_REMOVE_SEGMENT
XED_NONTERMINAL_RFLAGS
XED_NONTERMINAL_RIP
XED_NONTERMINAL_RIPA
XED_NONTERMINAL_SAE
XED_NONTERMINAL_SEG
XED_NONTERMINAL_SEG_MOV
XED_NONTERMINAL_SE_IMM8
XED_NONTERMINAL_SIB
XED_NONTERMINAL_SIB_BASE0
XED_NONTERMINAL_SIMM8
XED_NONTERMINAL_SIMMZ
XED_NONTERMINAL_SRBP
XED_NONTERMINAL_SRSP
XED_NONTERMINAL_TMM_B
XED_NONTERMINAL_TMM_N
XED_NONTERMINAL_TMM_R
XED_NONTERMINAL_TMM_R3
XED_NONTERMINAL_UIMM8
XED_NONTERMINAL_UIMM8_1
XED_NONTERMINAL_UIMM16
XED_NONTERMINAL_UIMM32
XED_NONTERMINAL_UIMMV
XED_NONTERMINAL_UISA_VMODRM_XMM
XED_NONTERMINAL_UISA_VMODRM_YMM
XED_NONTERMINAL_UISA_VMODRM_ZMM
XED_NONTERMINAL_UISA_VSIB_BASE
XED_NONTERMINAL_UISA_VSIB_INDEX_XMM
XED_NONTERMINAL_UISA_VSIB_INDEX_YMM
XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM
XED_NONTERMINAL_UISA_VSIB_XMM
XED_NONTERMINAL_UISA_VSIB_YMM
XED_NONTERMINAL_UISA_VSIB_ZMM
XED_NONTERMINAL_VGPR32_B
XED_NONTERMINAL_VGPR32_B_32
XED_NONTERMINAL_VGPR32_B_64
XED_NONTERMINAL_VGPR32_N
XED_NONTERMINAL_VGPR32_N_32
XED_NONTERMINAL_VGPR32_N_64
XED_NONTERMINAL_VGPR32_R
XED_NONTERMINAL_VGPR32_R_32
XED_NONTERMINAL_VGPR32_R_64
XED_NONTERMINAL_VGPR64_B
XED_NONTERMINAL_VGPR64_N
XED_NONTERMINAL_VGPR64_R
XED_NONTERMINAL_VGPRY_B
XED_NONTERMINAL_VGPRY_N
XED_NONTERMINAL_VGPRY_R
XED_NONTERMINAL_VMODRM_XMM
XED_NONTERMINAL_VMODRM_YMM
XED_NONTERMINAL_VSIB_BASE
XED_NONTERMINAL_VSIB_INDEX_XMM
XED_NONTERMINAL_VSIB_INDEX_YMM
XED_NONTERMINAL_VSIB_XMM
XED_NONTERMINAL_VSIB_YMM
XED_NONTERMINAL_X87
XED_NONTERMINAL_XMM_B
XED_NONTERMINAL_XMM_B3
XED_NONTERMINAL_XMM_B3_32
XED_NONTERMINAL_XMM_B3_64
XED_NONTERMINAL_XMM_B_32
XED_NONTERMINAL_XMM_B_64
XED_NONTERMINAL_XMM_N
XED_NONTERMINAL_XMM_N3
XED_NONTERMINAL_XMM_N3_32
XED_NONTERMINAL_XMM_N3_64
XED_NONTERMINAL_XMM_N_32
XED_NONTERMINAL_XMM_N_64
XED_NONTERMINAL_XMM_R
XED_NONTERMINAL_XMM_R3
XED_NONTERMINAL_XMM_R3_32
XED_NONTERMINAL_XMM_R3_64
XED_NONTERMINAL_XMM_R_32
XED_NONTERMINAL_XMM_R_64
XED_NONTERMINAL_XMM_SE
XED_NONTERMINAL_XMM_SE32
XED_NONTERMINAL_XMM_SE64
XED_NONTERMINAL_XOP_INSTRUCTIONS
XED_NONTERMINAL_YMM_B
XED_NONTERMINAL_YMM_B3
XED_NONTERMINAL_YMM_B3_32
XED_NONTERMINAL_YMM_B3_64
XED_NONTERMINAL_YMM_B_32
XED_NONTERMINAL_YMM_B_64
XED_NONTERMINAL_YMM_N
XED_NONTERMINAL_YMM_N3
XED_NONTERMINAL_YMM_N3_32
XED_NONTERMINAL_YMM_N3_64
XED_NONTERMINAL_YMM_N_32
XED_NONTERMINAL_YMM_N_64
XED_NONTERMINAL_YMM_R
XED_NONTERMINAL_YMM_R3
XED_NONTERMINAL_YMM_R3_32
XED_NONTERMINAL_YMM_R3_64
XED_NONTERMINAL_YMM_R_32
XED_NONTERMINAL_YMM_R_64
XED_NONTERMINAL_YMM_SE
XED_NONTERMINAL_YMM_SE32
XED_NONTERMINAL_YMM_SE64
XED_NONTERMINAL_ZMM_B3
XED_NONTERMINAL_ZMM_B3_32
XED_NONTERMINAL_ZMM_B3_64
XED_NONTERMINAL_ZMM_N3
XED_NONTERMINAL_ZMM_N3_32
XED_NONTERMINAL_ZMM_N3_64
XED_NONTERMINAL_ZMM_R3
XED_NONTERMINAL_ZMM_R3_32
XED_NONTERMINAL_ZMM_R3_64
XED_OPERAND_ABSBR
XED_OPERAND_ACTION_CR: < Conditional read
XED_OPERAND_ACTION_CRW: < Conditionlly read, always written (must write)
XED_OPERAND_ACTION_CW: < Conditionlly written (may write)
XED_OPERAND_ACTION_INVALID
XED_OPERAND_ACTION_LAST
XED_OPERAND_ACTION_R: < Read-only
XED_OPERAND_ACTION_RCW: < Read and conditionlly written (may write)
XED_OPERAND_ACTION_RW: < Read and written (must write)
XED_OPERAND_ACTION_W: < Write-only (must write)
XED_OPERAND_AGEN
XED_OPERAND_AMD3DNOW
XED_OPERAND_ASZ
XED_OPERAND_BASE0
XED_OPERAND_BASE1
XED_OPERAND_BCAST
XED_OPERAND_BCRC
XED_OPERAND_BRDISP_WIDTH
XED_OPERAND_CET
XED_OPERAND_CHIP
XED_OPERAND_CLDEMOTE
XED_OPERAND_CONVERT_BCASTSTR
XED_OPERAND_CONVERT_INVALID
XED_OPERAND_CONVERT_LAST
XED_OPERAND_CONVERT_MULTIREG2
XED_OPERAND_CONVERT_MULTIREG3
XED_OPERAND_CONVERT_MULTIREG4
XED_OPERAND_CONVERT_MULTIREG5
XED_OPERAND_CONVERT_MULTIREG6
XED_OPERAND_CONVERT_MULTIREG7
XED_OPERAND_CONVERT_MULTIREG8
XED_OPERAND_CONVERT_MULTIREG9
XED_OPERAND_CONVERT_MULTIREG10
XED_OPERAND_CONVERT_MULTIREG11
XED_OPERAND_CONVERT_MULTIREG12
XED_OPERAND_CONVERT_MULTIREG13
XED_OPERAND_CONVERT_MULTIREG14
XED_OPERAND_CONVERT_MULTIREG15
XED_OPERAND_CONVERT_MULTIREG16
XED_OPERAND_CONVERT_MULTIREG_START
XED_OPERAND_CONVERT_ROUNDC
XED_OPERAND_CONVERT_SAESTR
XED_OPERAND_CONVERT_ZEROSTR
XED_OPERAND_DEFAULT_SEG
XED_OPERAND_DF32
XED_OPERAND_DF64
XED_OPERAND_DISP
XED_OPERAND_DISP_WIDTH
XED_OPERAND_DUMMY
XED_OPERAND_EASZ
XED_OPERAND_ELEMENT_SIZE
XED_OPERAND_ELEMENT_TYPE_BFLOAT16: < bfloat16 floating point
XED_OPERAND_ELEMENT_TYPE_DOUBLE: < 64b FP double precision
XED_OPERAND_ELEMENT_TYPE_FLOAT16: < 16b floating point
XED_OPERAND_ELEMENT_TYPE_INT: < Signed integer
XED_OPERAND_ELEMENT_TYPE_INT8: < 8 bit integer
XED_OPERAND_ELEMENT_TYPE_INVALID
XED_OPERAND_ELEMENT_TYPE_LAST
XED_OPERAND_ELEMENT_TYPE_LONGBCD: < 80b decimal BCD
XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE: < 80b FP x87
XED_OPERAND_ELEMENT_TYPE_SINGLE: < 32b FP single precision
XED_OPERAND_ELEMENT_TYPE_STRUCT: < a structure of various fields
XED_OPERAND_ELEMENT_TYPE_UINT: < Unsigned integer
XED_OPERAND_ELEMENT_TYPE_UINT8: < 8 bit unsigned integer
XED_OPERAND_ELEMENT_TYPE_VARIABLE: < depends on other fields in the instruction
XED_OPERAND_ENCODER_PREFERRED
XED_OPERAND_ENCODE_FORCE
XED_OPERAND_EOSZ
XED_OPERAND_ERROR
XED_OPERAND_ESRC
XED_OPERAND_EVVSPACE
XED_OPERAND_FIRST_F2F3
XED_OPERAND_HAS_EGPR
XED_OPERAND_HAS_MODRM
XED_OPERAND_HAS_SIB
XED_OPERAND_HINT
XED_OPERAND_ICLASS
XED_OPERAND_ILD_F2
XED_OPERAND_ILD_F3
XED_OPERAND_ILD_SEG
XED_OPERAND_IMM0
XED_OPERAND_IMM0SIGNED
XED_OPERAND_IMM1
XED_OPERAND_IMM1_BYTES
XED_OPERAND_IMM_WIDTH
XED_OPERAND_INDEX
XED_OPERAND_INVALID
XED_OPERAND_LAST
XED_OPERAND_LAST_F2F3
XED_OPERAND_LLRC
XED_OPERAND_LOCK
XED_OPERAND_LZCNT
XED_OPERAND_MAP
XED_OPERAND_MASK
XED_OPERAND_MAX_BYTES
XED_OPERAND_MEM0
XED_OPERAND_MEM1
XED_OPERAND_MEM_WIDTH
XED_OPERAND_MOD
XED_OPERAND_MODE
XED_OPERAND_MODEP5
XED_OPERAND_MODEP55C
XED_OPERAND_MODE_FIRST_PREFIX
XED_OPERAND_MODE_SHORT_UD0
XED_OPERAND_MODRM_BYTE
XED_OPERAND_MPXMODE
XED_OPERAND_MUST_USE_EVEX
XED_OPERAND_ND
XED_OPERAND_NEEDREX
XED_OPERAND_NEED_MEMDISP
XED_OPERAND_NEED_SIB
XED_OPERAND_NELEM
XED_OPERAND_NF
XED_OPERAND_NOMINAL_OPCODE
XED_OPERAND_NOREX
XED_OPERAND_NOREX2
XED_OPERAND_NO_APX
XED_OPERAND_NO_EVEX
XED_OPERAND_NO_VEX
XED_OPERAND_NPREFIXES
XED_OPERAND_NREXES
XED_OPERAND_NSEG_PREFIXES
XED_OPERAND_OSZ
XED_OPERAND_OUTREG
XED_OPERAND_OUT_OF_BYTES
XED_OPERAND_P4
XED_OPERAND_POS_DISP
XED_OPERAND_POS_IMM
XED_OPERAND_POS_IMM1
XED_OPERAND_POS_MODRM
XED_OPERAND_POS_NOMINAL_OPCODE
XED_OPERAND_POS_SIB
XED_OPERAND_PREFIX66
XED_OPERAND_PTR
XED_OPERAND_REALMODE
XED_OPERAND_REG
XED_OPERAND_REG0
XED_OPERAND_REG1
XED_OPERAND_REG2
XED_OPERAND_REG3
XED_OPERAND_REG4
XED_OPERAND_REG5
XED_OPERAND_REG6
XED_OPERAND_REG7
XED_OPERAND_REG8
XED_OPERAND_REG9
XED_OPERAND_RELBR
XED_OPERAND_REP
XED_OPERAND_REX
XED_OPERAND_REX2
XED_OPERAND_REXB
XED_OPERAND_REXB4
XED_OPERAND_REXR
XED_OPERAND_REXR4
XED_OPERAND_REXW
XED_OPERAND_REXX
XED_OPERAND_REXX4
XED_OPERAND_RM
XED_OPERAND_ROUNDC
XED_OPERAND_SAE
XED_OPERAND_SCALE
XED_OPERAND_SCC
XED_OPERAND_SEG0
XED_OPERAND_SEG1
XED_OPERAND_SEG_OVD
XED_OPERAND_SIBBASE
XED_OPERAND_SIBINDEX
XED_OPERAND_SIBSCALE
XED_OPERAND_SKIP_OSZ
XED_OPERAND_SMODE
XED_OPERAND_SRM
XED_OPERAND_TYPE_ERROR
XED_OPERAND_TYPE_IMM
XED_OPERAND_TYPE_IMM_CONST
XED_OPERAND_TYPE_INVALID
XED_OPERAND_TYPE_LAST
XED_OPERAND_TYPE_NT_LOOKUP_FN
XED_OPERAND_TYPE_NT_LOOKUP_FN2
XED_OPERAND_TYPE_NT_LOOKUP_FN4
XED_OPERAND_TYPE_REG
XED_OPERAND_TZCNT
XED_OPERAND_UBIT
XED_OPERAND_UIMM0
XED_OPERAND_UIMM1
XED_OPERAND_USING_DEFAULT_SEGMENT0
XED_OPERAND_USING_DEFAULT_SEGMENT1
XED_OPERAND_VEXDEST3
XED_OPERAND_VEXDEST4
XED_OPERAND_VEXDEST210
XED_OPERAND_VEXVALID
XED_OPERAND_VEX_C4
XED_OPERAND_VEX_PREFIX
XED_OPERAND_VL
XED_OPERAND_VL_IGN
XED_OPERAND_WBNOINVD
XED_OPERAND_WIDTH_A16
XED_OPERAND_WIDTH_A32
XED_OPERAND_WIDTH_ASZ
XED_OPERAND_WIDTH_B
XED_OPERAND_WIDTH_BND32
XED_OPERAND_WIDTH_BND64
XED_OPERAND_WIDTH_D
XED_OPERAND_WIDTH_DQ
XED_OPERAND_WIDTH_F16
XED_OPERAND_WIDTH_F32
XED_OPERAND_WIDTH_F64
XED_OPERAND_WIDTH_F80
XED_OPERAND_WIDTH_I1
XED_OPERAND_WIDTH_I2
XED_OPERAND_WIDTH_I3
XED_OPERAND_WIDTH_I4
XED_OPERAND_WIDTH_I5
XED_OPERAND_WIDTH_I6
XED_OPERAND_WIDTH_I7
XED_OPERAND_WIDTH_I8
XED_OPERAND_WIDTH_I16
XED_OPERAND_WIDTH_I32
XED_OPERAND_WIDTH_I64
XED_OPERAND_WIDTH_INVALID
XED_OPERAND_WIDTH_LAST
XED_OPERAND_WIDTH_M64INT
XED_OPERAND_WIDTH_M64REAL
XED_OPERAND_WIDTH_M384
XED_OPERAND_WIDTH_M512
XED_OPERAND_WIDTH_MB
XED_OPERAND_WIDTH_MD
XED_OPERAND_WIDTH_MEM14
XED_OPERAND_WIDTH_MEM16
XED_OPERAND_WIDTH_MEM28
XED_OPERAND_WIDTH_MEM94
XED_OPERAND_WIDTH_MEM16INT
XED_OPERAND_WIDTH_MEM32INT
XED_OPERAND_WIDTH_MEM32REAL
XED_OPERAND_WIDTH_MEM80DEC
XED_OPERAND_WIDTH_MEM80REAL
XED_OPERAND_WIDTH_MEM108
XED_OPERAND_WIDTH_MFPXENV
XED_OPERAND_WIDTH_MPREFETCH
XED_OPERAND_WIDTH_MQ
XED_OPERAND_WIDTH_MSKW
XED_OPERAND_WIDTH_MW
XED_OPERAND_WIDTH_MXSAVE
XED_OPERAND_WIDTH_P
XED_OPERAND_WIDTH_P2
XED_OPERAND_WIDTH_PD
XED_OPERAND_WIDTH_PI
XED_OPERAND_WIDTH_PMMSZ16
XED_OPERAND_WIDTH_PMMSZ32
XED_OPERAND_WIDTH_PS
XED_OPERAND_WIDTH_PSEUDO
XED_OPERAND_WIDTH_PSEUDOX87
XED_OPERAND_WIDTH_PTR
XED_OPERAND_WIDTH_Q
XED_OPERAND_WIDTH_QQ
XED_OPERAND_WIDTH_S
XED_OPERAND_WIDTH_S64
XED_OPERAND_WIDTH_SD
XED_OPERAND_WIDTH_SI
XED_OPERAND_WIDTH_SPW
XED_OPERAND_WIDTH_SPW2
XED_OPERAND_WIDTH_SPW3
XED_OPERAND_WIDTH_SPW5
XED_OPERAND_WIDTH_SPW8
XED_OPERAND_WIDTH_SS
XED_OPERAND_WIDTH_SSZ
XED_OPERAND_WIDTH_TMEMCOL
XED_OPERAND_WIDTH_TMEMROW
XED_OPERAND_WIDTH_TV
XED_OPERAND_WIDTH_U8
XED_OPERAND_WIDTH_U16
XED_OPERAND_WIDTH_U32
XED_OPERAND_WIDTH_U64
XED_OPERAND_WIDTH_V
XED_OPERAND_WIDTH_VAR
XED_OPERAND_WIDTH_VV
XED_OPERAND_WIDTH_W
XED_OPERAND_WIDTH_WRD
XED_OPERAND_WIDTH_X128
XED_OPERAND_WIDTH_XB
XED_OPERAND_WIDTH_XD
XED_OPERAND_WIDTH_XQ
XED_OPERAND_WIDTH_XUB
XED_OPERAND_WIDTH_XUD
XED_OPERAND_WIDTH_XUQ
XED_OPERAND_WIDTH_XUW
XED_OPERAND_WIDTH_XW
XED_OPERAND_WIDTH_Y
XED_OPERAND_WIDTH_Y128
XED_OPERAND_WIDTH_YB
XED_OPERAND_WIDTH_YD
XED_OPERAND_WIDTH_YPD
XED_OPERAND_WIDTH_YPS
XED_OPERAND_WIDTH_YQ
XED_OPERAND_WIDTH_YU
XED_OPERAND_WIDTH_YUB
XED_OPERAND_WIDTH_YUD
XED_OPERAND_WIDTH_YUQ
XED_OPERAND_WIDTH_YUW
XED_OPERAND_WIDTH_YW
XED_OPERAND_WIDTH_Z
XED_OPERAND_WIDTH_Z2F16
XED_OPERAND_WIDTH_ZB
XED_OPERAND_WIDTH_ZBF16
XED_OPERAND_WIDTH_ZD
XED_OPERAND_WIDTH_ZD0
XED_OPERAND_WIDTH_ZF16
XED_OPERAND_WIDTH_ZF32
XED_OPERAND_WIDTH_ZF64
XED_OPERAND_WIDTH_ZI8
XED_OPERAND_WIDTH_ZI16
XED_OPERAND_WIDTH_ZI32
XED_OPERAND_WIDTH_ZI64
XED_OPERAND_WIDTH_ZMSKW
XED_OPERAND_WIDTH_ZQ
XED_OPERAND_WIDTH_ZU8
XED_OPERAND_WIDTH_ZU16
XED_OPERAND_WIDTH_ZU32
XED_OPERAND_WIDTH_ZU64
XED_OPERAND_WIDTH_ZU128
XED_OPERAND_WIDTH_ZUB
XED_OPERAND_WIDTH_ZUD
XED_OPERAND_WIDTH_ZUQ
XED_OPERAND_WIDTH_ZUW
XED_OPERAND_WIDTH_ZV
XED_OPERAND_WIDTH_ZW
XED_OPERAND_XTYPE_2BF16
XED_OPERAND_XTYPE_2F16
XED_OPERAND_XTYPE_2I16
XED_OPERAND_XTYPE_2U16
XED_OPERAND_XTYPE_4I8
XED_OPERAND_XTYPE_4U8
XED_OPERAND_XTYPE_B80
XED_OPERAND_XTYPE_BF16
XED_OPERAND_XTYPE_F16
XED_OPERAND_XTYPE_F32
XED_OPERAND_XTYPE_F64
XED_OPERAND_XTYPE_F80
XED_OPERAND_XTYPE_I1
XED_OPERAND_XTYPE_I8
XED_OPERAND_XTYPE_I16
XED_OPERAND_XTYPE_I32
XED_OPERAND_XTYPE_I64
XED_OPERAND_XTYPE_I128
XED_OPERAND_XTYPE_INT
XED_OPERAND_XTYPE_INVALID
XED_OPERAND_XTYPE_LAST
XED_OPERAND_XTYPE_STRUCT
XED_OPERAND_XTYPE_U8
XED_OPERAND_XTYPE_U16
XED_OPERAND_XTYPE_U32
XED_OPERAND_XTYPE_U64
XED_OPERAND_XTYPE_U128
XED_OPERAND_XTYPE_U256
XED_OPERAND_XTYPE_UINT
XED_OPERAND_XTYPE_VAR
XED_OPERAND_ZEROING
XED_OPVIS_EXPLICIT: < Shows up in operand encoding
XED_OPVIS_IMPLICIT: < Part of the opcode, but listed as an operand
XED_OPVIS_INVALID
XED_OPVIS_LAST
XED_OPVIS_SUPPRESSED: < Part of the opcode, but not typically listed as an operand
XED_REG_AH
XED_REG_AL
XED_REG_AX
XED_REG_BH
XED_REG_BL
XED_REG_BND0
XED_REG_BND1
XED_REG_BND2
XED_REG_BND3
XED_REG_BNDCFGU
XED_REG_BNDCFG_FIRST
XED_REG_BNDCFG_LAST
XED_REG_BNDSTATUS
XED_REG_BNDSTAT_FIRST
XED_REG_BNDSTAT_LAST
XED_REG_BOUND_FIRST
XED_REG_BOUND_LAST
XED_REG_BP
XED_REG_BPL
XED_REG_BX
XED_REG_CH
XED_REG_CL
XED_REG_CLASS_BNDCFG
XED_REG_CLASS_BNDSTAT
XED_REG_CLASS_BOUND
XED_REG_CLASS_CR
XED_REG_CLASS_DR
XED_REG_CLASS_FLAGS
XED_REG_CLASS_GPR
XED_REG_CLASS_GPR8
XED_REG_CLASS_GPR16
XED_REG_CLASS_GPR32
XED_REG_CLASS_GPR64
XED_REG_CLASS_INVALID
XED_REG_CLASS_IP
XED_REG_CLASS_LAST
XED_REG_CLASS_MASK
XED_REG_CLASS_MMX
XED_REG_CLASS_MSR
XED_REG_CLASS_MXCSR
XED_REG_CLASS_PSEUDO
XED_REG_CLASS_PSEUDOX87
XED_REG_CLASS_SR
XED_REG_CLASS_TMP
XED_REG_CLASS_TREG
XED_REG_CLASS_UIF
XED_REG_CLASS_X87
XED_REG_CLASS_XCR
XED_REG_CLASS_XMM
XED_REG_CLASS_YMM
XED_REG_CLASS_ZMM
XED_REG_CR0
XED_REG_CR1
XED_REG_CR2
XED_REG_CR3
XED_REG_CR4
XED_REG_CR5
XED_REG_CR6
XED_REG_CR7
XED_REG_CR8
XED_REG_CR9
XED_REG_CR10
XED_REG_CR11
XED_REG_CR12
XED_REG_CR13
XED_REG_CR14
XED_REG_CR15
XED_REG_CR_FIRST
XED_REG_CR_LAST
XED_REG_CS
XED_REG_CX
XED_REG_DFV0
XED_REG_DFV1
XED_REG_DFV2
XED_REG_DFV3
XED_REG_DFV4
XED_REG_DFV5
XED_REG_DFV6
XED_REG_DFV7
XED_REG_DFV8
XED_REG_DFV9
XED_REG_DFV10
XED_REG_DFV11
XED_REG_DFV12
XED_REG_DFV13
XED_REG_DFV14
XED_REG_DFV15
XED_REG_DH
XED_REG_DI
XED_REG_DIL
XED_REG_DL
XED_REG_DR0
XED_REG_DR1
XED_REG_DR2
XED_REG_DR3
XED_REG_DR4
XED_REG_DR5
XED_REG_DR6
XED_REG_DR7
XED_REG_DR_FIRST
XED_REG_DR_LAST
XED_REG_DS
XED_REG_DX
XED_REG_EAX
XED_REG_EBP
XED_REG_EBX
XED_REG_ECX
XED_REG_EDI
XED_REG_EDX
XED_REG_EFLAGS
XED_REG_EIP
XED_REG_ERROR
XED_REG_ES
XED_REG_ESI
XED_REG_ESP
XED_REG_FLAGS
XED_REG_FLAGS_FIRST
XED_REG_FLAGS_LAST
XED_REG_FS
XED_REG_FSBASE
XED_REG_GDTR
XED_REG_GPR8_FIRST
XED_REG_GPR8_LAST
XED_REG_GPR8h_FIRST
XED_REG_GPR8h_LAST
XED_REG_GPR16_FIRST
XED_REG_GPR16_LAST
XED_REG_GPR32_FIRST
XED_REG_GPR32_LAST
XED_REG_GPR64_FIRST
XED_REG_GPR64_LAST
XED_REG_GS
XED_REG_GSBASE
XED_REG_IA32_KERNEL_GS_BASE
XED_REG_IA32_U_CET
XED_REG_IDTR
XED_REG_INVALID
XED_REG_INVALID_FIRST
XED_REG_INVALID_LAST
XED_REG_IP
XED_REG_IP_FIRST
XED_REG_IP_LAST
XED_REG_K0
XED_REG_K1
XED_REG_K2
XED_REG_K3
XED_REG_K4
XED_REG_K5
XED_REG_K6
XED_REG_K7
XED_REG_LAST
XED_REG_LDTR
XED_REG_MASK_FIRST
XED_REG_MASK_LAST
XED_REG_MMX0
XED_REG_MMX1
XED_REG_MMX2
XED_REG_MMX3
XED_REG_MMX4
XED_REG_MMX5
XED_REG_MMX6
XED_REG_MMX7
XED_REG_MMX_FIRST
XED_REG_MMX_LAST
XED_REG_MSRS
XED_REG_MSR_FIRST
XED_REG_MSR_LAST
XED_REG_MXCSR
XED_REG_MXCSR_FIRST
XED_REG_MXCSR_LAST
XED_REG_PSEUDOX87_FIRST
XED_REG_PSEUDOX87_LAST
XED_REG_PSEUDO_FIRST
XED_REG_PSEUDO_LAST
XED_REG_R8
XED_REG_R9
XED_REG_R8B
XED_REG_R8D
XED_REG_R8W
XED_REG_R9B
XED_REG_R9D
XED_REG_R9W
XED_REG_R10
XED_REG_R11
XED_REG_R12
XED_REG_R13
XED_REG_R14
XED_REG_R15
XED_REG_R16
XED_REG_R17
XED_REG_R18
XED_REG_R19
XED_REG_R20
XED_REG_R21
XED_REG_R22
XED_REG_R23
XED_REG_R24
XED_REG_R25
XED_REG_R26
XED_REG_R27
XED_REG_R28
XED_REG_R29
XED_REG_R30
XED_REG_R31
XED_REG_R10B
XED_REG_R10D
XED_REG_R10W
XED_REG_R11B
XED_REG_R11D
XED_REG_R11W
XED_REG_R12B
XED_REG_R12D
XED_REG_R12W
XED_REG_R13B
XED_REG_R13D
XED_REG_R13W
XED_REG_R14B
XED_REG_R14D
XED_REG_R14W
XED_REG_R15B
XED_REG_R15D
XED_REG_R15W
XED_REG_R16B
XED_REG_R16D
XED_REG_R16W
XED_REG_R17B
XED_REG_R17D
XED_REG_R17W
XED_REG_R18B
XED_REG_R18D
XED_REG_R18W
XED_REG_R19B
XED_REG_R19D
XED_REG_R19W
XED_REG_R20B
XED_REG_R20D
XED_REG_R20W
XED_REG_R21B
XED_REG_R21D
XED_REG_R21W
XED_REG_R22B
XED_REG_R22D
XED_REG_R22W
XED_REG_R23B
XED_REG_R23D
XED_REG_R23W
XED_REG_R24B
XED_REG_R24D
XED_REG_R24W
XED_REG_R25B
XED_REG_R25D
XED_REG_R25W
XED_REG_R26B
XED_REG_R26D
XED_REG_R26W
XED_REG_R27B
XED_REG_R27D
XED_REG_R27W
XED_REG_R28B
XED_REG_R28D
XED_REG_R28W
XED_REG_R29B
XED_REG_R29D
XED_REG_R29W
XED_REG_R30B
XED_REG_R30D
XED_REG_R30W
XED_REG_R31B
XED_REG_R31D
XED_REG_R31W
XED_REG_RAX
XED_REG_RBP
XED_REG_RBX
XED_REG_RCX
XED_REG_RDI
XED_REG_RDX
XED_REG_RFLAGS
XED_REG_RIP
XED_REG_RSI
XED_REG_RSP
XED_REG_SI
XED_REG_SIL
XED_REG_SP
XED_REG_SPL
XED_REG_SR_FIRST
XED_REG_SR_LAST
XED_REG_SS
XED_REG_SSP
XED_REG_ST0
XED_REG_ST1
XED_REG_ST2
XED_REG_ST3
XED_REG_ST4
XED_REG_ST5
XED_REG_ST6
XED_REG_ST7
XED_REG_STACKPOP
XED_REG_STACKPUSH
XED_REG_TILECONFIG
XED_REG_TMM0
XED_REG_TMM1
XED_REG_TMM2
XED_REG_TMM3
XED_REG_TMM4
XED_REG_TMM5
XED_REG_TMM6
XED_REG_TMM7
XED_REG_TMP0
XED_REG_TMP1
XED_REG_TMP2
XED_REG_TMP3
XED_REG_TMP4
XED_REG_TMP5
XED_REG_TMP6
XED_REG_TMP7
XED_REG_TMP8
XED_REG_TMP9
XED_REG_TMP10
XED_REG_TMP11
XED_REG_TMP12
XED_REG_TMP13
XED_REG_TMP14
XED_REG_TMP15
XED_REG_TMP_FIRST
XED_REG_TMP_LAST
XED_REG_TR
XED_REG_TREG_FIRST
XED_REG_TREG_LAST
XED_REG_TSC
XED_REG_TSCAUX
XED_REG_UIF
XED_REG_UIF_FIRST
XED_REG_UIF_LAST
XED_REG_X87CONTROL
XED_REG_X87LASTCS
XED_REG_X87LASTDP
XED_REG_X87LASTDS
XED_REG_X87LASTIP
XED_REG_X87OPCODE
XED_REG_X87POP
XED_REG_X87POP2
XED_REG_X87PUSH
XED_REG_X87STATUS
XED_REG_X87TAG
XED_REG_X87_FIRST
XED_REG_X87_LAST
XED_REG_XCR0
XED_REG_XCR_FIRST
XED_REG_XCR_LAST
XED_REG_XMM0
XED_REG_XMM1
XED_REG_XMM2
XED_REG_XMM3
XED_REG_XMM4
XED_REG_XMM5
XED_REG_XMM6
XED_REG_XMM7
XED_REG_XMM8
XED_REG_XMM9
XED_REG_XMM10
XED_REG_XMM11
XED_REG_XMM12
XED_REG_XMM13
XED_REG_XMM14
XED_REG_XMM15
XED_REG_XMM16
XED_REG_XMM17
XED_REG_XMM18
XED_REG_XMM19
XED_REG_XMM20
XED_REG_XMM21
XED_REG_XMM22
XED_REG_XMM23
XED_REG_XMM24
XED_REG_XMM25
XED_REG_XMM26
XED_REG_XMM27
XED_REG_XMM28
XED_REG_XMM29
XED_REG_XMM30
XED_REG_XMM31
XED_REG_XMM_FIRST
XED_REG_XMM_LAST
XED_REG_YMM0
XED_REG_YMM1
XED_REG_YMM2
XED_REG_YMM3
XED_REG_YMM4
XED_REG_YMM5
XED_REG_YMM6
XED_REG_YMM7
XED_REG_YMM8
XED_REG_YMM9
XED_REG_YMM10
XED_REG_YMM11
XED_REG_YMM12
XED_REG_YMM13
XED_REG_YMM14
XED_REG_YMM15
XED_REG_YMM16
XED_REG_YMM17
XED_REG_YMM18
XED_REG_YMM19
XED_REG_YMM20
XED_REG_YMM21
XED_REG_YMM22
XED_REG_YMM23
XED_REG_YMM24
XED_REG_YMM25
XED_REG_YMM26
XED_REG_YMM27
XED_REG_YMM28
XED_REG_YMM29
XED_REG_YMM30
XED_REG_YMM31
XED_REG_YMM_FIRST
XED_REG_YMM_LAST
XED_REG_ZMM0
XED_REG_ZMM1
XED_REG_ZMM2
XED_REG_ZMM3
XED_REG_ZMM4
XED_REG_ZMM5
XED_REG_ZMM6
XED_REG_ZMM7
XED_REG_ZMM8
XED_REG_ZMM9
XED_REG_ZMM10
XED_REG_ZMM11
XED_REG_ZMM12
XED_REG_ZMM13
XED_REG_ZMM14
XED_REG_ZMM15
XED_REG_ZMM16
XED_REG_ZMM17
XED_REG_ZMM18
XED_REG_ZMM19
XED_REG_ZMM20
XED_REG_ZMM21
XED_REG_ZMM22
XED_REG_ZMM23
XED_REG_ZMM24
XED_REG_ZMM25
XED_REG_ZMM26
XED_REG_ZMM27
XED_REG_ZMM28
XED_REG_ZMM29
XED_REG_ZMM30
XED_REG_ZMM31
XED_REG_ZMM_FIRST
XED_REG_ZMM_LAST
XED_SYNTAX_ATT: < ATT SYSV disassembly syntax
XED_SYNTAX_INTEL: < Intel disassembly syntax
XED_SYNTAX_INVALID
XED_SYNTAX_LAST
XED_SYNTAX_XED: < XED disassembly syntax
XED_VERBOSE
XED_VERSION
XED_VERY_VERBOSE

Statics§

xed_verbose^⚠

Functions§

str2xed_address_width_enum_t^⚠: This converts strings to #xed_address_width_enum_t types. @param s A C-string. @return #xed_address_width_enum_t @ingroup ENUM
str2xed_attribute_enum_t^⚠: This converts strings to #xed_attribute_enum_t types. @param s A C-string. @return #xed_attribute_enum_t @ingroup ENUM
str2xed_category_enum_t^⚠: This converts strings to #xed_category_enum_t types. @param s A C-string. @return #xed_category_enum_t @ingroup ENUM
str2xed_chip_enum_t^⚠: This converts strings to #xed_chip_enum_t types. @param s A C-string. @return #xed_chip_enum_t @ingroup ENUM
str2xed_cpuid_group_enum_t^⚠: This converts strings to #xed_cpuid_group_enum_t types. @param s A C-string. @return #xed_cpuid_group_enum_t @ingroup ENUM
str2xed_cpuid_rec_enum_t^⚠: This converts strings to #xed_cpuid_rec_enum_t types. @param s A C-string. @return #xed_cpuid_rec_enum_t @ingroup ENUM
str2xed_error_enum_t^⚠: This converts strings to #xed_error_enum_t types. @param s A C-string. @return #xed_error_enum_t @ingroup ENUM
str2xed_exception_enum_t^⚠: This converts strings to #xed_exception_enum_t types. @param s A C-string. @return #xed_exception_enum_t @ingroup ENUM
str2xed_extension_enum_t^⚠: This converts strings to #xed_extension_enum_t types. @param s A C-string. @return #xed_extension_enum_t @ingroup ENUM
str2xed_flag_action_enum_t^⚠: This converts strings to #xed_flag_action_enum_t types. @param s A C-string. @return #xed_flag_action_enum_t @ingroup ENUM
str2xed_flag_enum_t^⚠: This converts strings to #xed_flag_enum_t types. @param s A C-string. @return #xed_flag_enum_t @ingroup ENUM
str2xed_iclass_enum_t^⚠: This converts strings to #xed_iclass_enum_t types. @param s A C-string. @return #xed_iclass_enum_t @ingroup ENUM
str2xed_iform_enum_t^⚠: This converts strings to #xed_iform_enum_t types. @param s A C-string. @return #xed_iform_enum_t @ingroup ENUM
str2xed_isa_set_enum_t^⚠: This converts strings to #xed_isa_set_enum_t types. @param s A C-string. @return #xed_isa_set_enum_t @ingroup ENUM
str2xed_machine_mode_enum_t^⚠: This converts strings to #xed_machine_mode_enum_t types. @param s A C-string. @return #xed_machine_mode_enum_t @ingroup ENUM
str2xed_nonterminal_enum_t^⚠: This converts strings to #xed_nonterminal_enum_t types. @param s A C-string. @return #xed_nonterminal_enum_t @ingroup ENUM
str2xed_operand_action_enum_t^⚠: This converts strings to #xed_operand_action_enum_t types. @param s A C-string. @return #xed_operand_action_enum_t @ingroup ENUM
str2xed_operand_convert_enum_t^⚠: This converts strings to #xed_operand_convert_enum_t types. @param s A C-string. @return #xed_operand_convert_enum_t @ingroup ENUM
str2xed_operand_element_type_enum_t^⚠: This converts strings to #xed_operand_element_type_enum_t types. @param s A C-string. @return #xed_operand_element_type_enum_t @ingroup ENUM
str2xed_operand_element_xtype_enum_t^⚠: This converts strings to #xed_operand_element_xtype_enum_t types. @param s A C-string. @return #xed_operand_element_xtype_enum_t @ingroup ENUM
str2xed_operand_enum_t^⚠: This converts strings to #xed_operand_enum_t types. @param s A C-string. @return #xed_operand_enum_t @ingroup ENUM
str2xed_operand_type_enum_t^⚠: This converts strings to #xed_operand_type_enum_t types. @param s A C-string. @return #xed_operand_type_enum_t @ingroup ENUM
str2xed_operand_visibility_enum_t^⚠: This converts strings to #xed_operand_visibility_enum_t types. @param s A C-string. @return #xed_operand_visibility_enum_t @ingroup ENUM
str2xed_operand_width_enum_t^⚠: This converts strings to #xed_operand_width_enum_t types. @param s A C-string. @return #xed_operand_width_enum_t @ingroup ENUM
str2xed_reg_class_enum_t^⚠: This converts strings to #xed_reg_class_enum_t types. @param s A C-string. @return #xed_reg_class_enum_t @ingroup ENUM
str2xed_reg_enum_t^⚠: This converts strings to #xed_reg_enum_t types. @param s A C-string. @return #xed_reg_enum_t @ingroup ENUM
str2xed_syntax_enum_t^⚠: This converts strings to #xed_syntax_enum_t types. @param s A C-string. @return #xed_syntax_enum_t @ingroup ENUM
xed3_get_generic_operand^⚠
xed3_operand_get_absbr^⚠
xed3_operand_get_agen^⚠
xed3_operand_get_amd3dnow^⚠
xed3_operand_get_asz^⚠
xed3_operand_get_base0^⚠
xed3_operand_get_base1^⚠
xed3_operand_get_bcast^⚠
xed3_operand_get_bcrc^⚠
xed3_operand_get_brdisp_width^⚠
xed3_operand_get_cet^⚠
xed3_operand_get_chip^⚠
xed3_operand_get_cldemote^⚠
xed3_operand_get_default_seg^⚠
xed3_operand_get_df32^⚠
xed3_operand_get_df64^⚠
xed3_operand_get_disp^⚠
xed3_operand_get_disp_width^⚠
xed3_operand_get_dummy^⚠
xed3_operand_get_easz^⚠
xed3_operand_get_element_size^⚠
xed3_operand_get_encode_force^⚠
xed3_operand_get_encoder_preferred^⚠
xed3_operand_get_eosz^⚠
xed3_operand_get_error^⚠
xed3_operand_get_esrc^⚠
xed3_operand_get_evvspace^⚠
xed3_operand_get_first_f2f3^⚠
xed3_operand_get_has_egpr^⚠
xed3_operand_get_has_modrm^⚠
xed3_operand_get_has_sib^⚠
xed3_operand_get_hint^⚠
xed3_operand_get_iclass^⚠
xed3_operand_get_ild_f2^⚠
xed3_operand_get_ild_f3^⚠
xed3_operand_get_ild_seg^⚠
xed3_operand_get_imm0^⚠
xed3_operand_get_imm0signed^⚠
xed3_operand_get_imm1^⚠
xed3_operand_get_imm1_bytes^⚠
xed3_operand_get_imm_width^⚠
xed3_operand_get_index^⚠
xed3_operand_get_last_f2f3^⚠
xed3_operand_get_llrc^⚠
xed3_operand_get_lock^⚠
xed3_operand_get_lzcnt^⚠
xed3_operand_get_map^⚠
xed3_operand_get_mask^⚠
xed3_operand_get_max_bytes^⚠
xed3_operand_get_mem0^⚠
xed3_operand_get_mem1^⚠
xed3_operand_get_mem_width^⚠
xed3_operand_get_mod^⚠
xed3_operand_get_mode^⚠
xed3_operand_get_mode_first_prefix^⚠
xed3_operand_get_mode_short_ud0^⚠
xed3_operand_get_modep5^⚠
xed3_operand_get_modep55c^⚠
xed3_operand_get_modrm_byte^⚠
xed3_operand_get_mpxmode^⚠
xed3_operand_get_must_use_evex^⚠
xed3_operand_get_nd^⚠
xed3_operand_get_need_memdisp^⚠
xed3_operand_get_need_sib^⚠
xed3_operand_get_needrex^⚠
xed3_operand_get_nelem^⚠
xed3_operand_get_nf^⚠
xed3_operand_get_no_apx^⚠
xed3_operand_get_no_evex^⚠
xed3_operand_get_no_vex^⚠
xed3_operand_get_nominal_opcode^⚠
xed3_operand_get_norex^⚠
xed3_operand_get_norex2^⚠
xed3_operand_get_nprefixes^⚠
xed3_operand_get_nrexes^⚠
xed3_operand_get_nseg_prefixes^⚠
xed3_operand_get_osz^⚠
xed3_operand_get_out_of_bytes^⚠
xed3_operand_get_outreg^⚠
xed3_operand_get_p4^⚠
xed3_operand_get_pos_disp^⚠
xed3_operand_get_pos_imm^⚠
xed3_operand_get_pos_imm1^⚠
xed3_operand_get_pos_modrm^⚠
xed3_operand_get_pos_nominal_opcode^⚠
xed3_operand_get_pos_sib^⚠
xed3_operand_get_prefix66^⚠
xed3_operand_get_ptr^⚠
xed3_operand_get_realmode^⚠
xed3_operand_get_reg^⚠
xed3_operand_get_reg0^⚠
xed3_operand_get_reg1^⚠
xed3_operand_get_reg2^⚠
xed3_operand_get_reg3^⚠
xed3_operand_get_reg4^⚠
xed3_operand_get_reg5^⚠
xed3_operand_get_reg6^⚠
xed3_operand_get_reg7^⚠
xed3_operand_get_reg8^⚠
xed3_operand_get_reg9^⚠
xed3_operand_get_relbr^⚠
xed3_operand_get_rep^⚠
xed3_operand_get_rex^⚠
xed3_operand_get_rex2^⚠
xed3_operand_get_rexb^⚠
xed3_operand_get_rexb4^⚠
xed3_operand_get_rexr^⚠
xed3_operand_get_rexr4^⚠
xed3_operand_get_rexw^⚠
xed3_operand_get_rexx^⚠
xed3_operand_get_rexx4^⚠
xed3_operand_get_rm^⚠
xed3_operand_get_roundc^⚠
xed3_operand_get_sae^⚠
xed3_operand_get_scale^⚠
xed3_operand_get_scc^⚠
xed3_operand_get_seg0^⚠
xed3_operand_get_seg1^⚠
xed3_operand_get_seg_ovd^⚠
xed3_operand_get_sibbase^⚠
xed3_operand_get_sibindex^⚠
xed3_operand_get_sibscale^⚠
xed3_operand_get_skip_osz^⚠
xed3_operand_get_smode^⚠
xed3_operand_get_srm^⚠
xed3_operand_get_tzcnt^⚠
xed3_operand_get_ubit^⚠
xed3_operand_get_uimm0^⚠
xed3_operand_get_uimm1^⚠
xed3_operand_get_using_default_segment0^⚠
xed3_operand_get_using_default_segment1^⚠
xed3_operand_get_vex_c4^⚠
xed3_operand_get_vex_prefix^⚠
xed3_operand_get_vexdest3^⚠
xed3_operand_get_vexdest4^⚠
xed3_operand_get_vexdest210^⚠
xed3_operand_get_vexvalid^⚠
xed3_operand_get_vl^⚠
xed3_operand_get_vl_ign^⚠
xed3_operand_get_wbnoinvd^⚠
xed3_operand_get_zeroing^⚠
xed3_operand_set_absbr^⚠
xed3_operand_set_agen^⚠
xed3_operand_set_amd3dnow^⚠
xed3_operand_set_asz^⚠
xed3_operand_set_base0^⚠
xed3_operand_set_base1^⚠
xed3_operand_set_bcast^⚠
xed3_operand_set_bcrc^⚠
xed3_operand_set_brdisp_width^⚠
xed3_operand_set_cet^⚠
xed3_operand_set_chip^⚠
xed3_operand_set_cldemote^⚠
xed3_operand_set_default_seg^⚠
xed3_operand_set_df32^⚠
xed3_operand_set_df64^⚠
xed3_operand_set_disp^⚠
xed3_operand_set_disp_width^⚠
xed3_operand_set_dummy^⚠
xed3_operand_set_easz^⚠
xed3_operand_set_element_size^⚠
xed3_operand_set_encode_force^⚠
xed3_operand_set_encoder_preferred^⚠
xed3_operand_set_eosz^⚠
xed3_operand_set_error^⚠
xed3_operand_set_esrc^⚠
xed3_operand_set_evvspace^⚠
xed3_operand_set_first_f2f3^⚠
xed3_operand_set_has_egpr^⚠
xed3_operand_set_has_modrm^⚠
xed3_operand_set_has_sib^⚠
xed3_operand_set_hint^⚠
xed3_operand_set_iclass^⚠
xed3_operand_set_ild_f2^⚠
xed3_operand_set_ild_f3^⚠
xed3_operand_set_ild_seg^⚠
xed3_operand_set_imm0^⚠
xed3_operand_set_imm0signed^⚠
xed3_operand_set_imm1^⚠
xed3_operand_set_imm1_bytes^⚠
xed3_operand_set_imm_width^⚠
xed3_operand_set_index^⚠
xed3_operand_set_last_f2f3^⚠
xed3_operand_set_llrc^⚠
xed3_operand_set_lock^⚠
xed3_operand_set_lzcnt^⚠
xed3_operand_set_map^⚠
xed3_operand_set_mask^⚠
xed3_operand_set_max_bytes^⚠
xed3_operand_set_mem0^⚠
xed3_operand_set_mem1^⚠
xed3_operand_set_mem_width^⚠
xed3_operand_set_mod^⚠
xed3_operand_set_mode^⚠
xed3_operand_set_mode_first_prefix^⚠
xed3_operand_set_mode_short_ud0^⚠
xed3_operand_set_modep5^⚠
xed3_operand_set_modep55c^⚠
xed3_operand_set_modrm_byte^⚠
xed3_operand_set_mpxmode^⚠
xed3_operand_set_must_use_evex^⚠
xed3_operand_set_nd^⚠
xed3_operand_set_need_memdisp^⚠
xed3_operand_set_need_sib^⚠
xed3_operand_set_needrex^⚠
xed3_operand_set_nelem^⚠
xed3_operand_set_nf^⚠
xed3_operand_set_no_apx^⚠
xed3_operand_set_no_evex^⚠
xed3_operand_set_no_vex^⚠
xed3_operand_set_nominal_opcode^⚠
xed3_operand_set_norex^⚠
xed3_operand_set_norex2^⚠
xed3_operand_set_nprefixes^⚠
xed3_operand_set_nrexes^⚠
xed3_operand_set_nseg_prefixes^⚠
xed3_operand_set_osz^⚠
xed3_operand_set_out_of_bytes^⚠
xed3_operand_set_outreg^⚠
xed3_operand_set_p4^⚠
xed3_operand_set_pos_disp^⚠
xed3_operand_set_pos_imm^⚠
xed3_operand_set_pos_imm1^⚠
xed3_operand_set_pos_modrm^⚠
xed3_operand_set_pos_nominal_opcode^⚠
xed3_operand_set_pos_sib^⚠
xed3_operand_set_prefix66^⚠
xed3_operand_set_ptr^⚠
xed3_operand_set_realmode^⚠
xed3_operand_set_reg^⚠
xed3_operand_set_reg0^⚠
xed3_operand_set_reg1^⚠
xed3_operand_set_reg2^⚠
xed3_operand_set_reg3^⚠
xed3_operand_set_reg4^⚠
xed3_operand_set_reg5^⚠
xed3_operand_set_reg6^⚠
xed3_operand_set_reg7^⚠
xed3_operand_set_reg8^⚠
xed3_operand_set_reg9^⚠
xed3_operand_set_relbr^⚠
xed3_operand_set_rep^⚠
xed3_operand_set_rex^⚠
xed3_operand_set_rex2^⚠
xed3_operand_set_rexb^⚠
xed3_operand_set_rexb4^⚠
xed3_operand_set_rexr^⚠
xed3_operand_set_rexr4^⚠
xed3_operand_set_rexw^⚠
xed3_operand_set_rexx^⚠
xed3_operand_set_rexx4^⚠
xed3_operand_set_rm^⚠
xed3_operand_set_roundc^⚠
xed3_operand_set_sae^⚠
xed3_operand_set_scale^⚠
xed3_operand_set_scc^⚠
xed3_operand_set_seg0^⚠
xed3_operand_set_seg1^⚠
xed3_operand_set_seg_ovd^⚠
xed3_operand_set_sibbase^⚠
xed3_operand_set_sibindex^⚠
xed3_operand_set_sibscale^⚠
xed3_operand_set_skip_osz^⚠
xed3_operand_set_smode^⚠
xed3_operand_set_srm^⚠
xed3_operand_set_tzcnt^⚠
xed3_operand_set_ubit^⚠
xed3_operand_set_uimm0^⚠
xed3_operand_set_uimm1^⚠
xed3_operand_set_using_default_segment0^⚠
xed3_operand_set_using_default_segment1^⚠
xed3_operand_set_vex_c4^⚠
xed3_operand_set_vex_prefix^⚠
xed3_operand_set_vexdest3^⚠
xed3_operand_set_vexdest4^⚠
xed3_operand_set_vexdest210^⚠
xed3_operand_set_vexvalid^⚠
xed3_operand_set_vl^⚠
xed3_operand_set_vl_ign^⚠
xed3_operand_set_wbnoinvd^⚠
xed3_operand_set_zeroing^⚠
xed3_set_generic_operand^⚠
xed_absbr^⚠: @ingroup ENCHL an absolute branch displacement operand @param brdisp The branch displacement @param width_bits The width of the displacement in bits. @returns xed_encoder_operand_t An operand.
xed_addr^⚠: @ingroup ENCHL This is to specify effective address size different than the default. For things with base or index regs, XED picks it up from the registers. But for things that have implicit memops, or no base or index reg, we must allow the user to set the address width directly. @param x The #xed_encoder_instruction_t being filled in. @param width_bits The intended effective address size in bits. Values: 16, 32 or 64.
xed_address_width_enum_t2str^⚠: This converts strings to #xed_address_width_enum_t types. @param p An enumeration element of type xed_address_width_enum_t. @return string @ingroup ENUM
xed_address_width_enum_t_last^⚠: Returns the last element of the enumeration @return xed_address_width_enum_t The last element of the enumeration. @ingroup ENUM
xed_agen^⚠: Using the registered callbacks, compute the memory address for a specified memop in a decoded instruction. memop_index can have the value 0 for XED_OPERAND_MEM0, XED_OPERAND_AGEN, or 1 for XED_OPERAND_MEM1. Any other value results in an error being returned. The context parameter which is passed to the registered callbacks can be used to identify which thread’s state is being referenced. The context parameter can also be used to specify which element of a vector register should be returned for gather an scatter operations. @ingroup AGEN
xed_agen_register_callback^⚠: Initialize the callback functions. Tell XED what to call when using #xed_agen. @ingroup AGEN
xed_attribute^⚠: @ingroup DEC Return the i’th global attribute in a linear sequence, independent of any instruction. This is used for scanning and printing all attributes.
xed_attribute_enum_t2str^⚠: This converts strings to #xed_attribute_enum_t types. @param p An enumeration element of type xed_attribute_enum_t. @return string @ingroup ENUM
xed_attribute_enum_t_last^⚠: Returns the last element of the enumeration @return xed_attribute_enum_t The last element of the enumeration. @ingroup ENUM
xed_attribute_max^⚠: @ingroup DEC Return the maximum number of defined attributes, independent of any instruction.
xed_category_enum_t2str^⚠: This converts strings to #xed_category_enum_t types. @param p An enumeration element of type xed_category_enum_t. @return string @ingroup ENUM
xed_category_enum_t_last^⚠: Returns the last element of the enumeration @return xed_category_enum_t The last element of the enumeration. @ingroup ENUM
xed_chip_enum_t2str^⚠: This converts strings to #xed_chip_enum_t types. @param p An enumeration element of type xed_chip_enum_t. @return string @ingroup ENUM
xed_chip_enum_t_last^⚠: Returns the last element of the enumeration @return xed_chip_enum_t The last element of the enumeration. @ingroup ENUM
xed_classify_amx^⚠: @ingroup DEC True for AMX instructions
xed_classify_apx^⚠: @ingroup DEC @brief True for APX instructions. includes instructions with EGPRs, REX2 and encodings that are treated as illegal on non-APX systems
xed_classify_avx^⚠: @ingroup DEC True for AVX/AVX2 SIMD VEX-encoded operations. Does not include BMI/BMI2 instructions.
xed_classify_avx512^⚠: @ingroup DEC True for AVX512 (EVEX-encoded) SIMD and (VEX encoded) K-mask instructions
xed_classify_avx512_maskop^⚠: @ingroup DEC True for AVX512 (VEX-encoded) K-mask operations
xed_classify_sse^⚠: @ingroup DEC True for SSE/SSE2/etc. SIMD operations. Includes AES and PCLMULQDQ
xed_convert_to_encoder_request^⚠: @ingroup ENCHL convert a #xed_encoder_instruction_t to a #xed_encoder_request_t for encoding
xed_cpuid_group_enum_t2str^⚠: This converts strings to #xed_cpuid_group_enum_t types. @param p An enumeration element of type xed_cpuid_group_enum_t. @return string @ingroup ENUM
xed_cpuid_group_enum_t_last^⚠: Returns the last element of the enumeration @return xed_cpuid_group_enum_t The last element of the enumeration. @ingroup ENUM
xed_cpuid_rec_enum_t2str^⚠: This converts strings to #xed_cpuid_rec_enum_t types. @param p An enumeration element of type xed_cpuid_rec_enum_t. @return string @ingroup ENUM
xed_cpuid_rec_enum_t_last^⚠: Returns the last element of the enumeration @return xed_cpuid_rec_enum_t The last element of the enumeration. @ingroup ENUM
xed_decode^⚠: This is the main interface to the decoder. @param xedd the decoded instruction of type #xed_decoded_inst_t . Mode/state sent in via xedd; See the #xed_state_t @param itext the pointer to the array of instruction text bytes @param bytes the length of the itext input array. 1 to 15 bytes, anything more is ignored. @return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or failure. Note failure can be due to not enough bytes in the input array.
xed_decode_with_features^⚠: @ingroup DEC See #xed_decode(). This version of the decode API adds a CPUID feature vector to support restricting decode based on both a specified chip via #xed_decoded_inst_set_input_chip() and a modify-able cpuid feature vector obtained from #xed_get_chip_features().
xed_decoded_inst_avx512_dest_elements^⚠: Returns the maximum number elements processed for an AVX512 vector instruction. Scalars report 1 element. @ingroup DEC
xed_decoded_inst_conditionally_writes_registers^⚠: @ingroup DEC
xed_decoded_inst_dump^⚠: @ingroup PRINT Print out all the information about the decoded instruction to the buffer buf whose length is maximally buflen. This is for debugging.
xed_decoded_inst_dump_xed_format^⚠: @ingroup PRINT Print the instruction information in a verbose format. This is for debugging. @param p a #xed_decoded_inst_t for a decoded instruction @param buf a buffer to write the disassembly in to. @param buflen maximum length of the disassembly buffer @param runtime_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. @return Returns 0 if the disassembly fails, 1 otherwise.
xed_decoded_inst_get_attribute^⚠: @ingroup DEC Returns 1 if the attribute is defined for this instruction.
xed_decoded_inst_get_attributes^⚠: @ingroup DEC Returns the attribute bitvector
xed_decoded_inst_get_base_reg^⚠: @ingroup DEC
xed_decoded_inst_get_branch_displacement^⚠: @ingroup DEC
xed_decoded_inst_get_branch_displacement_width^⚠: @ingroup DEC Result in BYTES
xed_decoded_inst_get_branch_displacement_width_bits^⚠: @ingroup DEC Result in BITS
xed_decoded_inst_get_byte^⚠: @ingroup DEC Read itext byte.
xed_decoded_inst_get_category^⚠: @ingroup DEC Return the instruction #xed_category_enum_t enumeration
xed_decoded_inst_get_dfv_reg^⚠: @ingroup DEC Return DFV register enumeration if one of the instruction’s operands is a “default flags values” pseudo-register and invalid register enumeration otherwise
xed_decoded_inst_get_extension^⚠: @ingroup DEC Return the instruction #xed_extension_enum_t enumeration
xed_decoded_inst_get_iclass^⚠: @ingroup DEC Return the instruction #xed_iclass_enum_t enumeration.
xed_decoded_inst_get_iform_enum^⚠: @ingroup DEC Return the instruction iform enum of type #xed_iform_enum_t .
xed_decoded_inst_get_iform_enum_dispatch^⚠: @ingroup DEC Return the instruction zero-based iform number based on masking the corresponding #xed_iform_enum_t. This value is suitable for dispatching. The maximum value for a particular iclass is provided by #xed_iform_max_per_iclass() .
xed_decoded_inst_get_immediate_is_signed^⚠: @ingroup DEC Return true if the first immediate (IMM0) is signed
xed_decoded_inst_get_immediate_width^⚠: @ingroup DEC Return the immediate width in BYTES.
xed_decoded_inst_get_immediate_width_bits^⚠: @ingroup DEC Return the immediate width in BITS.
xed_decoded_inst_get_index_reg^⚠
xed_decoded_inst_get_input_chip^⚠: Return the user-specified #xed_chip_enum_t chip name, or XED_CHIP_INVALID if not set. @ingroup DEC
xed_decoded_inst_get_isa_set^⚠: @ingroup DEC Return the instruction #xed_isa_set_enum_t enumeration
xed_decoded_inst_get_length^⚠: @ingroup DEC Return the length of the decoded instruction in bytes.
xed_decoded_inst_get_machine_mode_bits^⚠: @ingroup DEC Returns 16/32/64 indicating the machine mode with in bits. This is derived from the input mode information.
xed_decoded_inst_get_memop_address_width^⚠: @ingroup DEC
xed_decoded_inst_get_memory_displacement^⚠: @ingroup DEC
xed_decoded_inst_get_memory_displacement_width^⚠: @ingroup DEC Result in BYTES
xed_decoded_inst_get_memory_displacement_width_bits^⚠: @ingroup DEC Result in BITS
xed_decoded_inst_get_memory_operand_length^⚠: returns bytes @ingroup DEC
xed_decoded_inst_get_modrm^⚠: @ingroup DEC Returns the modrm byte
xed_decoded_inst_get_nprefixes^⚠: @ingroup DEC Returns the number of legacy prefixes.
xed_decoded_inst_get_operand_width^⚠: Returns the operand width in bits: 8/16/32/64. This is different than the #xed_operand_values_get_effective_operand_width() which only returns 16/32/64. This factors in the BYTEOP attribute when computing its return value. This function provides a information for that is only useful for (scalable) GPR-operations. Individual operands have more specific information available from #xed_decoded_inst_operand_element_size_bits() @ingroup DEC
xed_decoded_inst_get_reg^⚠: @ingroup DEC Return the specified register operand. The specifier is of type #xed_operand_enum_t .
xed_decoded_inst_get_rflags_info^⚠: See the comment on xed_decoded_inst_uses_rflags(). This can return 0 if the flags are really not used by this instruction. @ingroup DEC
xed_decoded_inst_get_scale^⚠: @ingroup DEC
xed_decoded_inst_get_second_immediate^⚠: @ingroup DEC Return the second immediate.
xed_decoded_inst_get_seg_reg^⚠: @ingroup DEC
xed_decoded_inst_get_signed_immediate^⚠: @ingroup DEC
xed_decoded_inst_get_stack_address_mode_bits^⚠: @ingroup DEC Returns 16/32/64 indicating the stack addressing mode with in bits. This is derived from the input mode information.
xed_decoded_inst_get_unsigned_immediate^⚠: @ingroup DEC
xed_decoded_inst_get_user_data^⚠: @ingroup DEC Return a user data field for arbitrary use by the user after decoding.
xed_decoded_inst_has_mpx_prefix^⚠: @ingroup DEC Returns 1 if the instruction has mpx prefix.
xed_decoded_inst_inst^⚠: @ingroup DEC Return the #xed_inst_t structure for this instruction. This is the route to the basic operands form information.
xed_decoded_inst_is_apx_zu^⚠: @ingroup DEC @brief Return non-zero value for APX-Promtoed zero-upper instructions (ZU).
xed_decoded_inst_is_broadcast^⚠: @ingroup DEC Return 1 for broadcast instructions or AVX512 load-op instructions using the broadcast feature 0 otherwise. Logical OR of #xed_decoded_inst_is_broadcast_instruction() and #xed_decoded_inst_uses_embedded_broadcast().
xed_decoded_inst_is_broadcast_instruction^⚠: @ingroup DEC Return 1 for broadcast instruction. (NOT including AVX512 load-op instructions) 0 otherwise. Just a category check.
xed_decoded_inst_is_prefetch^⚠: @ingroup DEC Returns true if the instruction is a prefetch
xed_decoded_inst_is_xacquire^⚠: @ingroup DEC Returns 1 if the instruction is xacquire.
xed_decoded_inst_is_xrelease^⚠: @ingroup DEC Returns 1 if the instruction is xrelease.
xed_decoded_inst_masked_vector_operation^⚠: @ingroup DEC Returns 1 iff the instruction uses destination-masking. This is 0 for blend operations that use their mask field as a control.
xed_decoded_inst_masking^⚠: Returns true if the instruction uses write-masking @ingroup DEC
xed_decoded_inst_mem_read^⚠: @ingroup DEC
xed_decoded_inst_mem_written^⚠: @ingroup DEC
xed_decoded_inst_mem_written_only^⚠: @ingroup DEC
xed_decoded_inst_merging^⚠: Returns true if the instruction uses write-masking with merging @ingroup DEC
xed_decoded_inst_noperands^⚠: Return the number of operands @ingroup DEC
xed_decoded_inst_number_of_memory_operands^⚠: @ingroup DEC
xed_decoded_inst_operand_action^⚠: Interpret the operand action in light of AVX512 masking and zeroing/merging. If masking and merging are used together, the dest operand may also be read. If masking and merging are used together, the elemnents of dest operand register may be conditionally written (so that input values live on in the output register). @ingroup DEC
xed_decoded_inst_operand_element_size_bits^⚠: Return the size of an element in bits (for SSE and AVX operands) @ingroup DEC
xed_decoded_inst_operand_element_type^⚠: Return the type of an element of type #xed_operand_element_type_enum_t (for SSE and AVX operands) @ingroup DEC
xed_decoded_inst_operand_elements^⚠: Return the number of element in the operand (for SSE and AVX operands) @ingroup DEC
xed_decoded_inst_operand_length^⚠: Deprecated – returns the length in bytes of the operand_index’th operand. Use #xed_decoded_inst_operand_length_bits() instead. @ingroup DEC
xed_decoded_inst_operand_length_bits^⚠: Return the length in bits of the operand_index’th operand. @ingroup DEC
xed_decoded_inst_operands^⚠: @ingroup DEC Obtain a non-constant pointer to the operands
xed_decoded_inst_operands_const^⚠: @ingroup DEC Obtain a constant pointer to the operands
xed_decoded_inst_set_branch_displacement^⚠: @ingroup DEC Set the branch displacement using a BYTE length
xed_decoded_inst_set_branch_displacement_bits^⚠: @ingroup DEC Set the branch displacement a BITS length
xed_decoded_inst_set_immediate_signed^⚠: @ingroup DEC Set the signed immediate a BYTE length
xed_decoded_inst_set_immediate_signed_bits^⚠: @ingroup DEC Set the signed immediate a BITS length
xed_decoded_inst_set_immediate_unsigned^⚠: @ingroup DEC Set the unsigned immediate a BYTE length
xed_decoded_inst_set_immediate_unsigned_bits^⚠: @ingroup DEC Set the unsigned immediate a BITS length
xed_decoded_inst_set_input_chip^⚠: Set a user-specified #xed_chip_enum_t chip name for restricting decode @ingroup DEC
xed_decoded_inst_set_memory_displacement^⚠: @ingroup DEC Set the memory displacement using a BYTE length
xed_decoded_inst_set_memory_displacement_bits^⚠: @ingroup DEC Set the memory displacement a BITS length
xed_decoded_inst_set_mode^⚠: @ingroup DEC Set the machine mode and stack addressing width directly. This is NOT a full initialization; Call #xed_decoded_inst_zero() before using this if you want a clean slate.
xed_decoded_inst_set_scale^⚠: @ingroup DEC
xed_decoded_inst_set_user_data^⚠: @ingroup DEC Modify the user data field.
xed_decoded_inst_uses_embedded_broadcast^⚠: @ingroup DEC Return 1 for AVX512 load-op instructions using the broadcast feature, 0 otherwise.
xed_decoded_inst_uses_rflags^⚠: This returns 1 if the flags are read or written. This will return 0 otherwise. This will return 0 if the flags are really not used by this instruction. For some shifts/rotates, XED puts a flags operand in the operand array before it knows if the flags are used because of mode-dependent masking effects on the immediate. @ingroup DEC
xed_decoded_inst_valid^⚠: @ingroup DEC Return true if the instruction is valid
xed_decoded_inst_valid_for_chip^⚠: Indicate if this decoded instruction is valid for the specified #xed_chip_enum_t chip @ingroup DEC
xed_decoded_inst_vector_length_bits^⚠: @ingroup DEC Returns 128, 256 or 512 for operations in the VEX, EVEX (or XOP) encoding space and returns 0 for (most) nonvector operations. This usually the content of the VEX.L or EVEX.LL field, reinterpreted. Some GPR instructions (like the BMI1/BMI2) are encoded in the VEX space and return non-zero values from this API.
xed_decoded_inst_zero^⚠: @ingroup DEC Zero the decode structure completely. Re-initializes all operands.
xed_decoded_inst_zero_keep_mode^⚠: @ingroup DEC Zero the decode structure, but preserve the existing machine state/mode information. Re-initializes all operands.
xed_decoded_inst_zero_keep_mode_from_operands^⚠: @ingroup DEC Zero the decode structure, but copy the existing machine state/mode information from the supplied operands pointer. Same as #xed_decoded_inst_zero_keep_mode.
xed_decoded_inst_zero_set_mode^⚠: @ingroup DEC Zero the decode structure, but set the machine state/mode information. Re-initializes all operands.
xed_decoded_inst_zeroing^⚠: Returns true if the instruction uses write-masking with zeroing @ingroup DEC
xed_disp^⚠: @ingroup ENCHL a memory displacement (not for branches) @param displacement The value of the displacement @param displacement_bits The width of the displacement in bits. Typically 8 or 32. @returns #xed_enc_displacement_t
xed_encode^⚠: This is the main interface to the encoder. The array should be at most 15 bytes long. The ilen parameter should indicate this length. If the array is too short, the encoder may fail to encode the request. Failure is indicated by a return value of type #xed_error_enum_t that is not equal to #XED_ERROR_NONE. Otherwise, #XED_ERROR_NONE is returned and the length of the encoded instruction is returned in olen.
xed_encode_nop^⚠: This function will attempt to encode a NOP of exactly ilen bytes. If such a NOP is not encodeable, then false will be returned.
xed_encode_request_print^⚠: @ingroup ENC
xed_encoder_request_get_iclass^⚠: @ingroup ENC
xed_encoder_request_get_operand_order^⚠: @ingroup ENC Retrieve the name of the n’th operand in the operand order.
xed_encoder_request_init_from_decode^⚠: @ingroup ENC Converts an decoder request to a valid encoder request.
xed_encoder_request_operand_order_entries^⚠: @ingroup ENC Retrieve the number of entries in the encoder operand order array @return The number of entries in the encoder operand order array
xed_encoder_request_operands^⚠: @ingroup ENC
xed_encoder_request_operands_const^⚠: @ingroup ENC
xed_encoder_request_set_absbr^⚠: @ingroup ENC
xed_encoder_request_set_agen^⚠: @ingroup ENC
xed_encoder_request_set_base0^⚠: @ingroup ENC
xed_encoder_request_set_base1^⚠: @ingroup ENC
xed_encoder_request_set_branch_displacement^⚠: @ingroup ENC
xed_encoder_request_set_effective_address_size^⚠: @ingroup ENC
xed_encoder_request_set_effective_operand_width^⚠: @ingroup ENC
xed_encoder_request_set_iclass^⚠: @ingroup ENC
xed_encoder_request_set_index^⚠: @ingroup ENC
xed_encoder_request_set_mem0^⚠: @ingroup ENC
xed_encoder_request_set_mem1^⚠: @ingroup ENC
xed_encoder_request_set_memory_displacement^⚠: @ingroup ENC
xed_encoder_request_set_memory_operand_length^⚠: @ingroup ENC
xed_encoder_request_set_operand_order^⚠: @ingroup ENC Specify the name as the n’th operand in the operand order.
xed_encoder_request_set_ptr^⚠: @ingroup ENC
xed_encoder_request_set_reg^⚠: @ingroup ENC
xed_encoder_request_set_relbr^⚠: @ingroup ENC
xed_encoder_request_set_scale^⚠: @ingroup ENC
xed_encoder_request_set_seg0^⚠: @ingroup ENC
xed_encoder_request_set_seg1^⚠: @ingroup ENC
xed_encoder_request_set_simm^⚠: @ingroup ENC same storage as uimm0
xed_encoder_request_set_uimm0^⚠: @ingroup ENC Set the uimm0 using a BYTE width.
xed_encoder_request_set_uimm0_bits^⚠: @ingroup ENC Set the uimm0 using a BIT width.
xed_encoder_request_set_uimm1^⚠: @ingroup ENC
xed_encoder_request_zero^⚠: @ingroup ENC
xed_encoder_request_zero_operand_order^⚠: @ingroup ENC clear the operand order array @param[in] p xed_encoder_request_t
xed_encoder_request_zero_set_mode^⚠: @ingroup ENC
xed_error_enum_t2str^⚠: This converts strings to #xed_error_enum_t types. @param p An enumeration element of type xed_error_enum_t. @return string @ingroup ENUM
xed_error_enum_t_last^⚠: Returns the last element of the enumeration @return xed_error_enum_t The last element of the enumeration. @ingroup ENUM
xed_exception_enum_t2str^⚠: This converts strings to #xed_exception_enum_t types. @param p An enumeration element of type xed_exception_enum_t. @return string @ingroup ENUM
xed_exception_enum_t_last^⚠: Returns the last element of the enumeration @return xed_exception_enum_t The last element of the enumeration. @ingroup ENUM
xed_extension_enum_t2str^⚠: This converts strings to #xed_extension_enum_t types. @param p An enumeration element of type xed_extension_enum_t. @return string @ingroup ENUM
xed_extension_enum_t_last^⚠: Returns the last element of the enumeration @return xed_extension_enum_t The last element of the enumeration. @ingroup ENUM
xed_flag_action_action_invalid^⚠: @ingroup FLAGS returns true if the specified action is invalid. Only the 2nd flag might be invalid.
xed_flag_action_enum_t2str^⚠: This converts strings to #xed_flag_action_enum_t types. @param p An enumeration element of type xed_flag_action_enum_t. @return string @ingroup ENUM
xed_flag_action_enum_t_last^⚠: Returns the last element of the enumeration @return xed_flag_action_enum_t The last element of the enumeration. @ingroup ENUM
xed_flag_action_get_action^⚠: @ingroup FLAGS return the action
xed_flag_action_get_flag_name^⚠: @ingroup FLAGS get the name of the flag
xed_flag_action_print^⚠: @ingroup FLAGS print the flag & actions
xed_flag_action_read_action^⚠: @ingroup FLAGS test to see if the specific action is a read
xed_flag_action_read_flag^⚠: @ingroup FLAGS returns true if either action is a read
xed_flag_action_write_action^⚠: @ingroup FLAGS test to see if a specific action is a write
xed_flag_action_writes_flag^⚠: @ingroup FLAGS returns true if either action is a write
xed_flag_dfv_get_default_flags_values^⚠: @ingroup FLAGS extracts the default flags values from XED DFV pseudo-register to a given xed_flag_dfv_t pointer If the given DFV enumeration is invalid, the function returns 0
xed_flag_enum_t2str^⚠: This converts strings to #xed_flag_enum_t types. @param p An enumeration element of type xed_flag_enum_t. @return string @ingroup ENUM
xed_flag_enum_t_last^⚠: Returns the last element of the enumeration @return xed_flag_enum_t The last element of the enumeration. @ingroup ENUM
xed_flag_set_is_subset_of^⚠: @ingroup FLAGS returns true if this object has a subset of the flags of the “other” object.
xed_flag_set_mask^⚠: @ingroup FLAGS Return the flags as a mask
xed_flag_set_print^⚠: @ingroup FLAGS print the flag set in the supplied buffer
xed_format_context^⚠: Disassemble the decoded instruction using the specified syntax. The output buffer must be at least 25 bytes long. Returns true if disassembly proceeded without errors. @param syntax a #xed_syntax_enum_t the specifies the disassembly format @param xedd a #xed_decoded_inst_t for a decoded instruction @param out_buffer a buffer to write the disassembly in to. @param buffer_len maximum length of the disassembly buffer @param runtime_instruction_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. @param context A void* used only for the call back routine for symbolic disassembly if one is provided. Can be zero. @param symbolic_callback A function pointer for obtaining symbolic disassembly. Can be zero. @return Returns 0 if the disassembly fails, 1 otherwise. @ingroup PRINT
xed_format_generic^⚠: @ingroup PRINT Disassemble the instruction information to a buffer. See the #xed_print_info_t for the required public fields of the argument. This is the preferred method of doing disassembly. The output buffer must be at least 25 bytes long. @param pi a #xed_print_info_t @return Returns 0 if the disassembly fails, 1 otherwise.
xed_format_set_options^⚠: Optionally, customize the disassembly formatting options by passing in a #xed_format_options_t structure. @ingroup PRINT
xed_get_byte^⚠
xed_get_chip_features^⚠: fill in the contents of p with the vector of chip features.
xed_get_copyright^⚠: @ingroup INIT Returns a copyright string.
xed_get_cpuid_group_enum_for_isa_set^⚠: @ingroup CPUID @brief Returns the name of the i’th cpuid group associated with the given isa-set. This function is called repeatedly, with i = 0 until reaching XED_MAX_CPUID_GROUPS_PER_ISA_SET or when the return value is XED_CPUID_GROUP_INVALID. An ISA-SET is supported by a chip if CPUID match is found for a single CPUID group (OR relationship between groups).
xed_get_cpuid_rec^⚠: @ingroup CPUID @brief provides the details of the CPUID specification, if the enumeration value is not sufficient. stores the values of the CPUID record in the given pointer p @returns xed_bool_t 1=success , 0=failure
xed_get_cpuid_rec_enum_for_group^⚠: @ingroup CPUID @brief Returns the name of the i’th cpuid record associated with the given cpuid group. This function is called repeatedly, with i = 0 until reaching XED_MAX_CPUID_RECS_PER_GROUP or when the return value is XED_CPUID_REC_INVALID. A cpuid group is satisfied if all of its cpuid records are set (AND relationship between records).
xed_get_largest_enclosing_register^⚠: Returns the largest enclosing register for any kind of register; This is mostly useful for GPRs. (64b mode assumed) @ingroup REGINTFC
xed_get_largest_enclosing_register32^⚠: Returns the largest enclosing register for any kind of register; This is mostly useful for GPRs in 32b mode. @ingroup REGINTFC
xed_get_register_width_bits^⚠: Returns the width, in bits, of the named register. 32b mode @ingroup REGINTFC
xed_get_register_width_bits64^⚠: Returns the width, in bits, of the named register. 64b mode. @ingroup REGINTFC
xed_get_version^⚠: @ingroup INIT Returns a string representing XED svn commit revision and time stamp.
xed_gpr_reg_class^⚠: Returns the specific width GPR reg class (like XED_REG_CLASS_GPR32 or XED_REG_CLASS_GPR64) for a given GPR register. Or XED_REG_INVALID if not a GPR. @ingroup REGINTFC
xed_iclass_enum_t2str^⚠: This converts strings to #xed_iclass_enum_t types. @param p An enumeration element of type xed_iclass_enum_t. @return string @ingroup ENUM
xed_iclass_enum_t_last^⚠: Returns the last element of the enumeration @return xed_iclass_enum_t The last element of the enumeration. @ingroup ENUM
xed_iform_enum_t2str^⚠: This converts strings to #xed_iform_enum_t types. @param p An enumeration element of type xed_iform_enum_t. @return string @ingroup ENUM
xed_iform_enum_t_last^⚠: Returns the last element of the enumeration @return xed_iform_enum_t The last element of the enumeration. @ingroup ENUM
xed_iform_first_per_iclass^⚠: @ingroup IFORM Return the first of the iforms for a particular iclass. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iform_map^⚠: @ingroup IFORM Map the #xed_iform_enum_t to a pointer to a #xed_iform_info_t which indicates the #xed_iclass_enum_t, the #xed_category_enum_t and the #xed_extension_enum_t for the iform. Returns 0 if the iform is not a valid iform.
xed_iform_max_per_iclass^⚠: @ingroup IFORM Return the maximum number of iforms for a particular iclass. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iform_to_category^⚠: @ingroup IFORM Return the category for a given iform. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iform_to_extension^⚠: @ingroup IFORM Return the extension for a given iform. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iform_to_iclass^⚠: @ingroup IFORM Return the iclass for a given iform. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iform_to_iclass_string_att^⚠: @ingroup IFORM Return a pointer to a character string of the iclass. This translates the internal disambiguated names to the more ambiguous names that people like to see. This returns the ATT SYSV-syntax name.
xed_iform_to_iclass_string_intel^⚠: @ingroup IFORM Return a pointer to a character string of the iclass. This translates the internal disambiguated names to the more ambiguous names that people like to see. This returns the Intel-syntax name.
xed_iform_to_isa_set^⚠: @ingroup IFORM Return the isa_set for a given iform. This function returns valid data as soon as global data is initialized. (This function does not require a decoded instruction as input).
xed_iformfl_enum_t_last^⚠: Returns the last element of the enumeration @return xed_iformfl_enum_t The last element of the enumeration. @ingroup ENUM
xed_ild_decode^⚠: This function just does instruction length decoding. It does not return a fully decoded instruction. @param xedd the decoded instruction of type #xed_decoded_inst_t . Mode/state sent in via xedd; See the #xed_state_t . @param itext the pointer to the array of instruction text bytes @param bytes the length of the itext input array. 1 to 15 bytes, anything more is ignored. @return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or failure. Only two failure codes are valid for this function: #XED_ERROR_BUFFER_TOO_SHORT and #XED_ERROR_GENERAL_ERROR. In general this function cannot tell if the instruction is valid or not. For valid instructions, XED can figure out if enough bytes were provided to decode the instruction. If not enough were provided, XED returns #XED_ERROR_BUFFER_TOO_SHORT. From this function, the #XED_ERROR_GENERAL_ERROR is an indication that XED could not decode the instruction’s length because the instruction was so invalid that even its length may across implmentations.
xed_imm0^⚠: @ingroup ENCHL a first immediate operand (known as IMM0) @param v An immdediate operand. @param width_bits The immediate width in bits. @returns xed_encoder_operand_t An operand.
xed_imm1^⚠: @ingroup ENCHL The 2nd immediate operand (known as IMM1) for rare instructions that require it. @param v The 2nd immdediate (byte-width) operand @returns xed_encoder_operand_t An operand.
xed_init_print_info^⚠: @ingroup PRINT
xed_inst^⚠: @ingroup ENCHL instruction with an array of operands. The maximum number is XED_ENCODER_OPERANDS_MAX. The array’s contents are copied. @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param number_of_operands length of the subsequent array @param operand_array An array of #xed_encoder_operand_t objects
xed_inst0^⚠: @ingroup ENCHL instruction with no operands @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits
xed_inst1^⚠: @ingroup ENCHL instruction with one operand @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param op0 the operand
xed_inst2^⚠: @ingroup ENCHL instruction with two operands @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param op0 the 1st operand @param op1 the 2nd operand
xed_inst3^⚠: @ingroup ENCHL instruction with three operands @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param op0 the 1st operand @param op1 the 2nd operand @param op2 the 3rd operand
xed_inst4^⚠: @ingroup ENCHL instruction with four operands @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param op0 the 1st operand @param op1 the 2nd operand @param op2 the 3rd operand @param op3 the 4th operand
xed_inst5^⚠: @ingroup ENCHL instruction with five operands @param inst The #xed_encoder_instruction_t to be filled in @param mode The xed_state_t including the machine mode and stack address width. @param iclass The #xed_iclass_enum_t @param effective_operand_width in bits @param op0 the 1st operand @param op1 the 2nd operand @param op2 the 3rd operand @param op3 the 4th operand @param op4 the 5th operand
xed_inst_category^⚠
xed_inst_cpl^⚠: @ingroup DEC xed_inst_cpl() is DEPRECATED. Please use “xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)” instead. Return the current privilege level (CPL) required for execution, 0 or 3. If the value is zero, then the instruction can only execute in ring 0.
xed_inst_exception^⚠: @ingroup DEC Return #xed_exception_enum_t if present for the specified instruction. This is currently only used for SSE and AVX instructions.
xed_inst_extension^⚠
xed_inst_flag_info_index^⚠
xed_inst_get_attribute^⚠: @ingroup DEC Scan for the attribute attr and return 1 if it is found, 0 otherwise.
xed_inst_get_attributes^⚠: @ingroup DEC Return the attributes bit vector
xed_inst_iclass^⚠
xed_inst_iform_enum^⚠
xed_inst_isa_set^⚠
xed_inst_noperands^⚠: @ingroup DEC Number of instruction operands
xed_inst_operand^⚠: @ingroup DEC Obtain a pointer to an individual operand
xed_inst_table_base^⚠: @ingroup DEC Return the base of instruction table.
xed_internal_assert^⚠
xed_isa_set_enum_t2str^⚠: This converts strings to #xed_isa_set_enum_t types. @param p An enumeration element of type xed_isa_set_enum_t. @return string @ingroup ENUM
xed_isa_set_enum_t_last^⚠: Returns the last element of the enumeration @return xed_isa_set_enum_t The last element of the enumeration. @ingroup ENUM
xed_isa_set_is_valid_for_chip^⚠: @ingroup ISASET return 1 if the isa_set is part included in the specified chip, 0 otherwise.
xed_itoa^⚠
xed_itoa_bin^⚠: Convert the input value f into its binary representation as a string and store it in buf. @param buf Pointer to the character array where the binary representation will be stored. @param f Input value to be converted. @param bits_to_print Number of bits to print (limited to 64 bits). @param buflen Length of the buf array. @return The number of characters actually copied (excluding the null terminator).
xed_itoa_hex^⚠: defaults to lowercase
xed_itoa_hex_ul^⚠
xed_itoa_hex_zeros^⚠: defaults to lowercase
xed_machine_mode_enum_t2str^⚠: This converts strings to #xed_machine_mode_enum_t types. @param p An enumeration element of type xed_machine_mode_enum_t. @return string @ingroup ENUM
xed_machine_mode_enum_t_last^⚠: Returns the last element of the enumeration @return xed_machine_mode_enum_t The last element of the enumeration. @ingroup ENUM
xed_make_int64^⚠
xed_make_uint64^⚠
xed_mem_b^⚠: @ingroup ENCHL memory operand - base only @param base The base register @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_bd^⚠: @ingroup ENCHL memory operand - base and displacement only @param base The base register @param disp The displacement @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_bisd^⚠: @ingroup ENCHL memory operand - base, index, scale, displacement @param base The base register @param index The index register @param scale The scale for the index register value @param disp The displacement @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_gb^⚠: @ingroup ENCHL memory operand - segment and base only @param seg The segment override register @param base The base register @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_gbd^⚠: @ingroup ENCHL memory operand - segment, base and displacement only @param seg The segment override register @param base The base register @param disp The displacement @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_gbisd^⚠: @ingroup ENCHL memory operand - segment, base, index, scale, and displacement @param seg The segment override register @param base The base register @param index The index register @param scale The scale for the index register value @param disp The displacement @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_mem_gd^⚠: @ingroup ENCHL memory operand - segment and displacement only @param seg The segment override register @param disp The displacement @param width_bits The length of the memory reference in bits. @returns xed_encoder_operand_t An operand.
xed_modify_chip_features^⚠: present = 1 to turn the feature on. present=0 to remove the feature.
xed_nonterminal_enum_t2str^⚠: This converts strings to #xed_nonterminal_enum_t types. @param p An enumeration element of type xed_nonterminal_enum_t. @return string @ingroup ENUM
xed_nonterminal_enum_t_last^⚠: Returns the last element of the enumeration @return xed_nonterminal_enum_t The last element of the enumeration. @ingroup ENUM
xed_norep_map^⚠: @ingroup DEC Take an #xed_iclass_enum_t value for an instruction with a REP/REPNE/REPE prefix and return the corresponding #xed_iclass_enum_t without that prefix. If the input instruction does not have a REP/REPNE/REPE prefix, this function returns XED_ICLASS_INVALID.
xed_operand_action_conditional_read^⚠
xed_operand_action_conditional_write^⚠
xed_operand_action_enum_t2str^⚠: This converts strings to #xed_operand_action_enum_t types. @param p An enumeration element of type xed_operand_action_enum_t. @return string @ingroup ENUM
xed_operand_action_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_action_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_action_read^⚠
xed_operand_action_read_and_written^⚠
xed_operand_action_read_only^⚠
xed_operand_action_written^⚠
xed_operand_action_written_only^⚠
xed_operand_conditional_read^⚠: @ingroup DEC If the operand has a conditional read (may also write)
xed_operand_conditional_write^⚠: @ingroup DEC If the operand has a conditional write (may also read)
xed_operand_convert_enum_t2str^⚠: This converts strings to #xed_operand_convert_enum_t types. @param p An enumeration element of type xed_operand_convert_enum_t. @return string @ingroup ENUM
xed_operand_convert_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_convert_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_element_type_enum_t2str^⚠: This converts strings to #xed_operand_element_type_enum_t types. @param p An enumeration element of type xed_operand_element_type_enum_t. @return string @ingroup ENUM
xed_operand_element_type_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_element_type_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_element_xtype_enum_t2str^⚠: This converts strings to #xed_operand_element_xtype_enum_t types. @param p An enumeration element of type xed_operand_element_xtype_enum_t. @return string @ingroup ENUM
xed_operand_element_xtype_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_element_xtype_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_enum_t2str^⚠: This converts strings to #xed_operand_enum_t types. @param p An enumeration element of type xed_operand_enum_t. @return string @ingroup ENUM
xed_operand_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_imm^⚠: @ingroup DEC @param p an operand template, #xed_operand_t. These operands represent branch displacements, memory displacements and various immediates
xed_operand_is_memory_addressing_register^⚠: @ingroup DEC Tests the enum for inclusion in XED_OPERAND_{BASE0,BASE1,INDEX,SEG0,SEG1} @param name the operand name, type #xed_operand_enum_t @return 1 if the operand name is for a memory addressing register operand, 0 otherwise. See also #xed_operand_is_register .
xed_operand_is_register^⚠: @ingroup DEC Tests the enum for inclusion in XED_OPERAND_REG0 through XED_OPERAND_REG9. @param name the operand name, type #xed_operand_enum_t @return 1 if the operand name is REG0…REG9, 0 otherwise.
xed_operand_name^⚠: @ingroup DEC
xed_operand_nonterminal_name^⚠: @ingroup DEC
xed_operand_operand_visibility^⚠: @ingroup DEC
xed_operand_print^⚠: @ingroup DEC Print the operand p into the buffer buf, of length buflen. @param p an operand template, #xed_operand_t. @param buf buffer that gets filled in @param buflen maximum buffer length
xed_operand_read^⚠: @ingroup DEC If the operand is read, including conditional reads
xed_operand_read_and_written^⚠: @ingroup DEC If the operand is read-and-written, conditional reads and conditional writes
xed_operand_read_only^⚠: @ingroup DEC If the operand is read-only, including conditional reads
xed_operand_reg^⚠: @ingroup DEC Careful with this one – use #xed_decoded_inst_get_reg()! This one is probably not what you think it is. It is only used for hard-coded registers implicit in the instruction encoding. Most likely you want to get the #xed_operand_enum_t and then look up the instruction using #xed_decoded_inst_get_reg(). The hard-coded registers are also available that way. @param p an operand template, #xed_operand_t. @return the implicit or suppressed registers, type #xed_reg_enum_t
xed_operand_rw^⚠: @ingroup DEC DEPRECATED: Returns the raw R/W action. There are many cases for conditional reads and writes. See #xed_decoded_inst_operand_action().
xed_operand_template_is_register^⚠: @ingroup DEC Careful with this one; See #xed_operand_is_register(). @param p an operand template, #xed_operand_t. @return 1 if the operand template represents are register-type operand.
xed_operand_type^⚠: @ingroup DEC @return The #xed_operand_type_enum_t of the operand template. This is probably not what you want.
xed_operand_type_enum_t2str^⚠: This converts strings to #xed_operand_type_enum_t types. @param p An enumeration element of type xed_operand_type_enum_t. @return string @ingroup ENUM
xed_operand_type_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_type_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_values_accesses_memory^⚠: @ingroup OPERANDS
xed_operand_values_branch_not_taken_hint^⚠: @ingroup OPERANDS Returns true if 0x2E prefix on Jcc
xed_operand_values_branch_taken_hint^⚠: @ingroup OPERANDS Returns true if 0x3E prefix on Jcc
xed_operand_values_cet_no_track^⚠: @ingroup OPERANDS Returns true for indirect call/jmp with 0x3E prefix (if the legacy prefix rules are obeyed)
xed_operand_values_clear_rep^⚠: @ingroup OPERANDS DO NOT USE - DEPRECATED. The correct way to do remove a rep prefix is by changing the iclass
xed_operand_values_dump^⚠: @ingroup OPERANDS Dump all the information about the operands to buf.
xed_operand_values_get_atomic^⚠: @ingroup OPERANDS Returns true if the memory operation has atomic read-modify-write semantics. An XCHG accessing memory is atomic with or without a LOCK prefix.
xed_operand_values_get_base_reg^⚠: @ingroup OPERANDS
xed_operand_values_get_branch_displacement_byte^⚠: @ingroup OPERANDS
xed_operand_values_get_branch_displacement_int64^⚠: @ingroup OPERANDS
xed_operand_values_get_branch_displacement_length^⚠: @ingroup OPERANDS Return the branch displacement width in bytes
xed_operand_values_get_branch_displacement_length_bits^⚠: @ingroup OPERANDS Return the branch displacement width in bits
xed_operand_values_get_displacement_for_memop^⚠: @ingroup OPERANDS Deprecated. Compatibility function for XED0. See has_memory_displacement().
xed_operand_values_get_effective_address_width^⚠: @ingroup OPERANDS Returns The effective address width in bits: 16/32/64.
xed_operand_values_get_effective_operand_width^⚠: @ingroup OPERANDS Returns The effective operand width in bits: 16/32/64. Note this is not the same as the width of the operand which can vary! For 8 bit operations, the effective operand width is the machine mode’s default width. If you also want to identify byte operations use the higher level function #xed_decoded_inst_get_operand_width() .
xed_operand_values_get_iclass^⚠: @ingroup OPERANDS
xed_operand_values_get_immediate_byte^⚠: @ingroup OPERANDS Return the i’th byte of the immediate
xed_operand_values_get_immediate_int64^⚠: @ingroup OPERANDS
xed_operand_values_get_immediate_is_signed^⚠: @ingroup OPERANDS Return true if the first immediate (IMM0) is signed
xed_operand_values_get_immediate_uint64^⚠: @ingroup OPERANDS
xed_operand_values_get_index_reg^⚠: @ingroup OPERANDS
xed_operand_values_get_long_mode^⚠: @ingroup OPERANDS
xed_operand_values_get_memory_displacement_byte^⚠: @ingroup OPERANDS
xed_operand_values_get_memory_displacement_int64^⚠: Returns the potentially scaled value of the memory displacement. Certain AVX512 memory displacements are scaled before they are used. @ingroup OPERANDS
xed_operand_values_get_memory_displacement_int64_raw^⚠: Returns the unscaled (raw) memory displacement. Certain AVX512 memory displacements are scaled before they are used. @ingroup OPERANDS
xed_operand_values_get_memory_displacement_length^⚠: @ingroup OPERANDS Return the memory displacement width in BYTES
xed_operand_values_get_memory_displacement_length_bits^⚠: @ingroup OPERANDS Return the memory displacement width in BITS
xed_operand_values_get_memory_displacement_length_bits_raw^⚠: @ingroup OPERANDS Return the raw memory displacement width in BITS(ignores scaling)
xed_operand_values_get_memory_operand_length^⚠: return bytes @ingroup OPERANDS
xed_operand_values_get_pp_vex_prefix^⚠: @ingroup OPERANDS Return the [VEX,EVEX].PP encoding value (2 bits)
xed_operand_values_get_real_mode^⚠: @ingroup OPERANDS
xed_operand_values_get_scale^⚠: @ingroup OPERANDS
xed_operand_values_get_second_immediate^⚠: @ingroup OPERANDS
xed_operand_values_get_seg_reg^⚠: @ingroup OPERANDS
xed_operand_values_get_stack_address_width^⚠: @ingroup OPERANDS Returns The stack address width in bits: 16/32/64.
xed_operand_values_has_66_prefix^⚠: @ingroup OPERANDS This includes any 66 prefix that shows up even if it is ignored.
xed_operand_values_has_address_size_prefix^⚠: @ingroup OPERANDS This indicates the presence of a 67 prefix.
xed_operand_values_has_branch_displacement^⚠: @ingroup OPERANDS True if there is a branch displacement
xed_operand_values_has_disp^⚠: @ingroup OPERANDS ALIAS for has_displacement(). Deprecated. See has_memory_displacement() and has_branch_displacement().
xed_operand_values_has_displacement^⚠: @ingroup OPERANDS True if there is a memory or branch displacement
xed_operand_values_has_immediate^⚠: @ingroup OPERANDS Return true if there is an immediate operand
xed_operand_values_has_lock_prefix^⚠: @ingroup OPERANDS Returns true if the memory operation has a valid lock prefix.
xed_operand_values_has_memory_displacement^⚠: @ingroup OPERANDS True if there is a memory displacement
xed_operand_values_has_modrm_byte^⚠: @ingroup OPERANDS Returns true if the instruction has a MODRM byte.
xed_operand_values_has_operand_size_prefix^⚠: @ingroup OPERANDS This does not include the cases when the 66 prefix is used an opcode-refining prefix for multibyte opcodes.
xed_operand_values_has_real_rep^⚠: @ingroup OPERANDS True if the instruction has a real REP prefix. This returns false if there is no F2/F3 prefix or the F2/F3 prefix is used to refine the opcode as in some SSE operations.
xed_operand_values_has_rep_prefix^⚠: @ingroup OPERANDS True if the instruction as a F3 REP prefix (used for opcode refining, for rep for string operations, or ignored).
xed_operand_values_has_repne_prefix^⚠: @ingroup OPERANDS True if the instruction as a F2 REP prefix (used for opcode refining, for rep for string operations, or ignored).
xed_operand_values_has_rexw_prefix^⚠: @ingroup OPERANDS This instruction has a REX prefix with the W bit set.
xed_operand_values_has_segment_prefix^⚠: @ingroup OPERANDS
xed_operand_values_has_sib_byte^⚠: @ingroup OPERANDS Returns true if the instruction has a SIB byte.
xed_operand_values_init^⚠: @ingroup OPERANDS Initializes operand structure
xed_operand_values_init_keep_mode^⚠: @ingroup OPERANDS Initializes dst operand structure but preserves the existing MODE/SMODE values from the src operand structure.
xed_operand_values_init_set_mode^⚠: @ingroup OPERANDS Initializes the operand storage and sets mode values.
xed_operand_values_is_nop^⚠: @ingroup OPERANDS
xed_operand_values_is_prefetch^⚠: @ingroup OPERANDS
xed_operand_values_lockable^⚠: @ingroup OPERANDS Returns true if the instruction could be re-encoded to have a lock prefix but does not have one currently.
xed_operand_values_mandatory_66_prefix^⚠: @ingroup OPERANDS This is exclusive to cases whereby the 66 prefix is mandatory.
xed_operand_values_memop_without_modrm^⚠: @ingroup OPERANDS Returns true if the instruction access memory but without using a MODRM byte limiting its addressing modes.
xed_operand_values_number_of_memory_operands^⚠: @ingroup OPERANDS
xed_operand_values_print_short^⚠: @ingroup OPERANDS More tersely dump all the information about the operands to buf.
xed_operand_values_segment_prefix^⚠: @ingroup OPERANDS Return the segment prefix, if any, as a #xed_reg_enum_t value.
xed_operand_values_set_absbr^⚠: @ingroup OPERANDS Indicate that we have an absolute branch.
xed_operand_values_set_base_reg^⚠: @ingroup OPERANDS
xed_operand_values_set_branch_displacement^⚠: @ingroup OPERANDS Set the branch displacement using a BYTES length
xed_operand_values_set_branch_displacement_bits^⚠: @ingroup OPERANDS Set the branch displacement using a BITS length
xed_operand_values_set_effective_address_width^⚠: @ingroup OPERANDS width is bits 16, 32, 64
xed_operand_values_set_effective_operand_width^⚠: @ingroup OPERANDS width is bits 8, 16, 32, 64
xed_operand_values_set_iclass^⚠: @ingroup OPERANDS
xed_operand_values_set_immediate_signed^⚠: @ingroup OPERANDS Set the signed immediate using a BYTES length
xed_operand_values_set_immediate_signed_bits^⚠: @ingroup OPERANDS Set the signed immediate using a BITS length
xed_operand_values_set_immediate_unsigned^⚠: @ingroup OPERANDS Set the unsigned immediate using a BYTE length.
xed_operand_values_set_immediate_unsigned_bits^⚠: @ingroup OPERANDS Set the unsigned immediate using a BIT length.
xed_operand_values_set_index_reg^⚠: @ingroup OPERANDS
xed_operand_values_set_lock^⚠: @ingroup OPERANDS
xed_operand_values_set_memory_displacement^⚠: @ingroup OPERANDS Set the memory displacement using a BYTES length
xed_operand_values_set_memory_displacement_bits^⚠: @ingroup OPERANDS Set the memory displacement using a BITS length
xed_operand_values_set_memory_operand_length^⚠: takes bytes, not bits, as an argument @ingroup OPERANDS
xed_operand_values_set_mode^⚠: @ingroup OPERANDS Set the mode values
xed_operand_values_set_operand_reg^⚠: @ingroup OPERANDS Set the operand storage field entry named ‘operand_name’ to the register value specified by ‘reg_name’.
xed_operand_values_set_relbr^⚠: @ingroup OPERANDS Indicate that we have a relative branch.
xed_operand_values_set_scale^⚠: @ingroup OPERANDS
xed_operand_values_set_seg_reg^⚠: @ingroup OPERANDS
xed_operand_values_using_default_segment^⚠: @ingroup OPERANDS Indicates if the default segment is being used. @param[in] p the pointer to the #xed_operand_values_t structure. @param[in] i 0 or 1, indicating which memory operation. @return true if the memory operation is using the default segment for the associated addressing mode base register.
xed_operand_values_zero_branch_displacement^⚠: @ingroup OPERANDS
xed_operand_values_zero_immediate^⚠: @ingroup OPERANDS
xed_operand_values_zero_memory_displacement^⚠: @ingroup OPERANDS
xed_operand_values_zero_segment_override^⚠: @ingroup OPERANDS
xed_operand_visibility_enum_t2str^⚠: This converts strings to #xed_operand_visibility_enum_t types. @param p An enumeration element of type xed_operand_visibility_enum_t. @return string @ingroup ENUM
xed_operand_visibility_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_visibility_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_width^⚠: @ingroup DEC
xed_operand_width_bits^⚠: @ingroup DEC @param p an operand template, #xed_operand_t. @param eosz effective operand size of the instruction, 1 | 2 | 3 for 16 | 32 | 64 bits respectively. 0 is invalid. @return the actual width of operand in bits. See xed_decoded_inst_operand_length_bits() for a more general solution.
xed_operand_width_enum_t2str^⚠: This converts strings to #xed_operand_width_enum_t types. @param p An enumeration element of type xed_operand_width_enum_t. @return string @ingroup ENUM
xed_operand_width_enum_t_last^⚠: Returns the last element of the enumeration @return xed_operand_width_enum_t The last element of the enumeration. @ingroup ENUM
xed_operand_written^⚠: @ingroup DEC If the operand is written, including conditional writes
xed_operand_written_only^⚠: @ingroup DEC If the operand is written-only, including conditional writes
xed_operand_xtype^⚠: @ingroup DEC @return The #xed_operand_element_xtype_enum_t of the operand template. This is probably not what you want.
xed_other^⚠: @ingroup ENCHL an operand storage field name and value
xed_patch_brdisp^⚠: Replace a relative/absolute branch displacement. The widths of original displacement and replacement must match. @param xedd A decoded instruction. @param itext The corresponding encoder output, byte array. @param disp A xed_encoder_operand_t object describing the new displacement. @returns xed_bool_t 1=success, 0=failure @ingroup ENCHLPATCH
xed_patch_disp^⚠: Replace a memory displacement. The widths of original displacement and replacement must match. @param xedd A decoded instruction. @param itext The corresponding encoder output, byte array. @param disp A xed_enc_displacement_t object describing the new displacement. @returns xed_bool_t 1=success, 0=failure @ingroup ENCHLPATCH
xed_patch_imm0^⚠: Replace an imm0 immediate value. The widths of original immediate and replacement must match. @param xedd A decoded instruction. @param itext The corresponding encoder output, byte array. @param imm0 A xed_encoder_operand_t object describing the new immediate. @returns xed_bool_t 1=success, 0=failure @ingroup ENCHLPATCH
xed_ptr^⚠: @ingroup ENCHL a relative displacement for a PTR operand – the subsequent imm0 holds the 16b selector @param brdisp The displacement for a far pointer operand @param width_bits The width of the far pointr displacement in bits. @returns xed_encoder_operand_t An operand.
xed_reg^⚠: @ingroup ENCHL a register operand @param reg A #xed_reg_enum_t register operand @returns xed_encoder_operand_t An operand.
xed_reg_class^⚠: Returns the register class of the given input register. @ingroup REGINTFC
xed_reg_class_enum_t2str^⚠: This converts strings to #xed_reg_class_enum_t types. @param p An enumeration element of type xed_reg_class_enum_t. @return string @ingroup ENUM
xed_reg_class_enum_t_last^⚠: Returns the last element of the enumeration @return xed_reg_class_enum_t The last element of the enumeration. @ingroup ENUM
xed_reg_enum_t2str^⚠: This converts strings to #xed_reg_enum_t types. @param p An enumeration element of type xed_reg_enum_t. @return string @ingroup ENUM
xed_reg_enum_t_last^⚠: Returns the last element of the enumeration @return xed_reg_enum_t The last element of the enumeration. @ingroup ENUM
xed_register_abort_function^⚠: @ingroup INIT This is for registering a function to be called during XED’s assert processing. If you do not register an abort function, then the system’s abort function will be called. If your supplied function returns, then abort() will still be called.
xed_relbr^⚠: @ingroup ENCHL a relative branch displacement operand @param brdisp The branch displacement @param width_bits The width of the displacement in bits. Typically 8 or 32. @returns xed_encoder_operand_t An operand.
xed_rep^⚠: @ingroup ENCHL To add a REP (0xF3) prefix. @param x The #xed_encoder_instruction_t being filled in.
xed_rep_map^⚠: @ingroup DEC Take an #xed_iclass_enum_t value without a REP prefix and return the corresponding #xed_iclass_enum_t with a REP prefix. If the input instruction cannot have a REP prefix, this function returns XED_ICLASS_INVALID.
xed_rep_remove^⚠: @ingroup DEC Take an instruction with a REP/REPE/REPNE prefix and return the corresponding xed_iclass_enum_t without that prefix. The return value differs from the other functions in this group: If the input iclass does not have REP/REPNE/REPE prefix, the function returns the original instruction.
xed_repe_map^⚠: @ingroup DEC Take an #xed_iclass_enum_t value without a REPE prefix and return the corresponding #xed_iclass_enum_t with a REPE prefix. If the input instruction cannot have have a REPE prefix, this function returns XED_ICLASS_INVALID.
xed_repne^⚠: @ingroup ENCHL To add a REPNE (0xF2) prefix. @param x The #xed_encoder_instruction_t being filled in.
xed_repne_map^⚠: @ingroup DEC Take an #xed_iclass_enum_t value without a REPNE prefix and return the corresponding #xed_iclass_enum_t with a REPNE prefix. If the input instruction cannot have a REPNE prefix, this function returns XED_ICLASS_INVALID.
xed_seg0^⚠: @ingroup ENCHL seg reg override for implicit suppressed memory ops
xed_seg1^⚠: @ingroup ENCHL seg reg override for implicit suppressed memory ops
xed_set_log_file^⚠: Set the FILE* for XED’s log msgs. This takes a FILE* as a void* because some software defines their own FILE* types creating conflicts.
xed_set_verbosity^⚠: Set the verbosity level for XED
xed_shortest_width_signed^⚠: returns the number of bytes required to store the SIGNED number x given a mask of legal lengths. For the legal_widths argument, bit 0 implies 1 byte is a legal return width, bit 1 implies that 2 bytes is a legal return width, bit 2 implies that 4 bytes is a legal return width. This returns 8 (indicating 8B) if none of the provided legal widths applies.
xed_shortest_width_unsigned^⚠: returns the number of bytes required to store the UNSIGNED number x given a mask of legal lengths. For the legal_widths argument, bit 0 implies 1 byte is a legal return width, bit 1 implies that 2 bytes is a legal return width, bit 2 implies that 4 bytes is a legal return width. This returns 8 (indicating 8B) if none of the provided legal widths applies.
xed_sign_extend8_16^⚠
xed_sign_extend8_32^⚠
xed_sign_extend8_64^⚠
xed_sign_extend16_32^⚠
xed_sign_extend16_64^⚠
xed_sign_extend32_64^⚠
xed_sign_extend_arbitrary_to_32^⚠: arbitrary sign extension from a qty of “bits” length to 32b
xed_sign_extend_arbitrary_to_64^⚠: arbitrary sign extension from a qty of “bits” length to 64b
xed_simm0^⚠: @ingroup ENCHL an 32b signed immediate operand @param v An signed immdediate operand. @param width_bits The immediate width in bits. @returns xed_encoder_operand_t An operand.
xed_simple_flag_get_flag_action^⚠: @ingroup FLAGS return the specific flag-action. Very detailed low level information
xed_simple_flag_get_may_write^⚠: @ingroup FLAGS Indicates the flags are only conditionally written. Usually MAY-writes of the flags instructions that are dependent on a REP count.
xed_simple_flag_get_must_write^⚠: @ingroup FLAGS the flags always written
xed_simple_flag_get_nflags^⚠: @ingroup FLAGS returns the number of flag-actions
xed_simple_flag_get_read_flag_set^⚠: @ingroup FLAGS return union of bits for read flags
xed_simple_flag_get_undefined_flag_set^⚠: @ingroup FLAGS return union of bits for undefined flags
xed_simple_flag_get_written_flag_set^⚠: @ingroup FLAGS return union of bits for written flags
xed_simple_flag_print^⚠: @ingroup FLAGS print the flags
xed_simple_flag_reads_flags^⚠: @ingroup FLAGS boolean test to see if flags are read, scans the flags
xed_simple_flag_writes_flags^⚠: @ingroup FLAGS boolean test to see if flags are written, scans the flags
xed_state_get_address_width^⚠: return the address width @ingroup INIT
xed_state_get_machine_mode^⚠: return the machine mode @ingroup INIT
xed_state_get_stack_address_width^⚠: Return the STACK address width @ingroup INIT
xed_state_init^⚠: Constructor. DEPRECATED: use #xed_state_init2(). The mode, and addresses widths are enumerations that specify the number of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine modes, you must specify valid addressing widths.
xed_state_init2^⚠: Constructor. The mode, and addresses widths are enumerations that specify the number of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine modes, you must specify valid addressing widths.
xed_state_long64_mode^⚠: true iff the machine is in LONG_64 mode @ingroup INIT
xed_state_mode_width_16^⚠: @ingroup INIT
xed_state_mode_width_32^⚠: @ingroup INIT
xed_state_print^⚠: @ingroup INIT
xed_state_real_mode^⚠: @ingroup INIT
xed_state_set_machine_mode^⚠: Set the machine mode which corresponds to the default data operand size @ingroup INIT
xed_state_set_stack_address_width^⚠: set the STACK address width @ingroup INIT
xed_state_zero^⚠: clear the xed_state_t @ingroup INIT
xed_strcat^⚠
xed_strcpy^⚠
xed_strlen^⚠
xed_strncat^⚠: returns the number of bytes remaining for the next use of #xed_strncpy() or #xed_strncat() .
xed_strncpy^⚠: returns the number of bytes remaining for the next use of #xed_strncpy() or #xed_strncat() .
xed_syntax_enum_t2str^⚠: This converts strings to #xed_syntax_enum_t types. @param p An enumeration element of type xed_syntax_enum_t. @return string @ingroup ENUM
xed_syntax_enum_t_last^⚠: Returns the last element of the enumeration @return xed_syntax_enum_t The last element of the enumeration. @ingroup ENUM
xed_tables_init^⚠: @ingroup INIT This is the call to initialize the XED encode and decode tables. It must be called once before using XED.
xed_zero_extend8_16^⚠
xed_zero_extend8_32^⚠
xed_zero_extend8_64^⚠
xed_zero_extend16_32^⚠
xed_zero_extend16_64^⚠
xed_zero_extend32_64^⚠

Type Aliases§

xed_addr_t
xed_address_width_enum_t
xed_attribute_enum_t
xed_bits_t
xed_bool_t
xed_category_enum_t
xed_chip_enum_t
xed_cpuid_group_enum_t
xed_cpuid_rec_enum_t
xed_decoded_inst_t: @ingroup DEC The main container for instructions. After decode, it holds an array of operands with derived information from decode and also valid #xed_inst_t pointer which describes the operand templates and the operand order. See @ref DEC for API documentation.
xed_disassembly_callback_fn_t: @param address The input address for which we want symbolic name and offset @param symbol_buffer A buffer to hold the symbol name. The callback function should fill this in and terminate with a null byte. @param buffer_length The maximum length of the symbol_buffer including then null @param offset A pointer to a xed_uint64_t to hold the offset from the provided symbol. @param context This void* pointer passed to the disassembler’s new interface so that the caller can identify the proper context against which to resolve the symbols. The disassembler passes this value to the callback. The legacy formatters that do not have context will pass zero for this parameter. @return 0 on failure, 1 on success.
xed_encoder_iforms_t
xed_encoder_operand_type_t
xed_encoder_request_s: @ingroup ENC
xed_encoder_request_t: @ingroup ENC
xed_error_enum_t
xed_exception_enum_t
xed_extension_enum_t
xed_flag_action_enum_t
xed_flag_action_t: @ingroup FLAGS Associated with each flag field there can be one action.
xed_flag_dfv_t: @ingroup FLAGS a struct representing an instruction’s default flags values
xed_flag_enum_t
xed_flag_set_t: @ingroup FLAGS a union of flags bits
xed_iclass_enum_t
xed_iform_enum_t
xed_iform_info_t: @ingroup IFORM Statically available information about iforms. Values are returned by #xed_iform_map().
xed_iformfl_enum_t
xed_inst_t: @ingroup DEC constant information about a decoded instruction form, including the pointer to the constant operand properties #xed_operand_t for this instruction form.
xed_int_t
xed_isa_set_enum_t
xed_machine_mode_enum_t
xed_nonterminal_enum_t
xed_operand_action_enum_t
xed_operand_convert_enum_t
xed_operand_element_type_enum_t
xed_operand_element_xtype_enum_t
xed_operand_enum_t
xed_operand_extractor_fn_t
xed_operand_storage_t
xed_operand_t: @ingroup DEC Constant information about an individual generic operand, like an operand template, describing the operand properties. See @ref DEC for API information.
xed_operand_type_enum_t
xed_operand_values_t: @ingroup DEC The main container for instructions. After decode, it holds an array of operands with derived information from decode and also valid #xed_inst_t pointer which describes the operand templates and the operand order. See @ref DEC for API documentation.
xed_operand_visibility_enum_t
xed_operand_width_enum_t
xed_reg_class_enum_t
xed_reg_enum_t
xed_register_callback_fn_t: A function for obtaining register values. 32b return values should be zero extended to 64b. The error value is set to nonzero if the callback experiences some sort of problem. @ingroup AGEN
xed_segment_base_callback_fn_t: A function for obtaining the segment base values. 32b return values should be zero extended zero extended to 64b. The error value is set to nonzero if the callback experiences some sort of problem. @ingroup AGEN
xed_simple_flag_t: @ingroup FLAGS A collection of #xed_flag_action_t’s and unions of read and written flags
xed_state_t: Encapsulates machine modes for decoder/encoder requests. It specifies the machine operating mode as a #xed_machine_mode_enum_t for decoding and encoding. The machine mode corresponds to the default data operand width for that mode. For all modes other than the 64b long mode (XED_MACHINE_MODE_LONG_64), a default addressing width, and a stack addressing width must be supplied of type #xed_address_width_enum_t . @ingroup INIT
xed_syntax_enum_t
xed_uint_t
xed_user_abort_function_t

Unions§

xed_decoded_inst_s__bindgen_ty_1
xed_decoded_inst_s__bindgen_ty_2
xed_encoder_operand_t__bindgen_ty_1
xed_encoder_prefixes_t
xed_flag_dfv_s: @ingroup FLAGS a struct representing an instruction’s default flags values
xed_flag_set_s: @ingroup FLAGS a union of flags bits
xed_ild_vars_t
xed_operand_s__bindgen_ty_1
xed_union16_t
xed_union32_t
xed_union64_t

Crate xed_sysCopy item path

§Features

Structs§

Constants§

Statics§

Functions§

Type Aliases§

Unions§

Crate xed_sys