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§xc2bit: A library for working with Xilinx Coolrunner-II bitstreams

xc2bit is a library for reading and writing bitstreams for the Xilinx Coolrunner-II family of CPLD devices.

This project is the result of a reverse-engineering effort involving a combination of imaging physical CPLD devices and black-box reverse-engineering of generated .jed files. It is not an official project of Xilinx, Inc. and is not affiliated or endorsed by Xilinx, Inc.

Logically, a Coolrunner-II CPLD contains the following major blocks: function blocks (occasionally abbreviated to FBs), a global interconnect (occasionally referred to as the ZIA or the AIM), and input/output blocks (occasionally abbreviated to IOBs). Function blocks are further divided into the PLA (programmable logic array, a matrix of AND and OR gates) and macrocells. In the Coolrunner-II architecture, macrocells also contain an XOR gate and a register. The global interconnect accepts inputs from IOBs and function blocks and connects these inputs into the PLA of each function block. IOBs also have direct connections to a corresponding macrocell in a function block. (The reverse is not always true - on larger devices, there are macrocells that are not connected to IOBs.) As a special exception, the smallest 32-macrocell devices also have one single input-only pin that is connected directly into the global interconnect and does not have a corresponding macrocell.

Structs§

FuseArray: Struct representing a 2-dimensional fuse array and handles converting xy-coordinates into a single linear index. The x-axis is horizontal and the y-axis is vertical. The origin is at the top-left corner. (This is the standard “computer graphics” coordinate scheme.)
XC2Bitstream: Toplevel struct representing an entire Coolrunner-II bitstream
XC2BitstreamFB: Represents a collection of all the parts that make up one function block
XC2ClockDiv: Represents the configuration of the programmable clock divider in devices with 128 macrocells or more. This is hard-wired onto the GCK2 clock pin.
XC2DeviceSpeedPackage: Device type, speed grade, and package all in one struct
XC2ExtraIBuf: Represents the one additional special input-only pin on 32-macrocell devices.
XC2GlobalNets: Represents the configuration of the global nets. Coolrunner-II parts have various global control signals that have dedicated low-skew paths.
XC2MCLargeIOB: Represents an I/O pin on “large” (128 and greater macrocell) devices.
XC2MCSmallIOB: Represents an I/O pin on “small” (32 and 64 macrocell) devices.
XC2Macrocell: Represents a macrocell.
XC2PLAAndTerm: Represents one single AND term in the PLA. Each AND term can perform an AND function on any subset of its inputs and the complement of those inputs. The index for each input is the corresponding ZIA row.
XC2PLAOrTerm: Represents one single OR term in the PLA. Each OR term can perform an OR function on any subset of its inputs. The index for each input is the index of the corresponding AND term in the same PLA.

Enums§

XC2BitError: Errors that can occur when parsing a bitstream
XC2BitstreamBits: The actual bitstream bits for each possible Coolrunner-II part
XC2ClockDivRatio: Possible clock divide ratios for the programmable clock divider
XC2Device: Coolrunner-II devices
XC2IOBIbufMode: Input mode selection on larger parts with VREF
XC2IOBOBufMode: Mode selection for the I/O pin’s output buffer. See the Xilinx Coolrunner-II documentation for more information.
XC2IOBZIAMode: Mux selection for the ZIA input from this I/O pin’s input. The ZIA input can be chosen to come from either the input pin directly or from the output of the register in the macrocell corresponding to this I/O pin. The latter is used to allow for buried combinatorial feedback in a macrocell without “wasting” the register.
XC2MCFeedbackMode: Mux selection for the ZIA input from this macrocell. The ZIA input can be chosen to come from either the XOR gate or from the output of the register.
XC2MCRegClkSrc: Clock source for the register in a macrocell
XC2MCRegMode: Mode of the register in a macrocell.
XC2MCRegResetSrc: Reset source for the register in a macrocell
XC2MCRegSetSrc: Set source for the register in a macrocell
XC2MCXorMode: Mux selection for the “not from OR gate” input to the XOR gate. The XOR gate in a macrocell contains two inputs, the output of the corresponding OR term from the PLA and a specific dedicated AND term from the PLA.
XC2Package: Possible physical packages
XC2Speed: Possible speed grades
XC2ZIAInput: Represents one output of the ZIA. The ZIA is divided into rows, and each row can independently select a choice to connect to each function block. The ZIA has inputs from every part of the chip and can additionally output a constant zero or one. This represents one such output (as opposed to all outputs in a given row)

Constants§

ANDTERMS_PER_FB: The number of AND gates in each PLA. This is also the number of inputs into each OR gate in the PLA. This is an unchangeable property of the architecture of the CPLD.
CTC: The index of the special CTC product term
CTE: The index of the special CTE product term
CTR: The index of the special CTR product term
CTS: The index of the special CTS product term
INPUTS_PER_ANDTERM: The number of inputs from the ZIA interconnect into the AND gate section of each PLA. This is an unchangeable property of the architecture of the CPLD.
MCS_PER_FB: The number of macrocells in each function block. This is also the number of OR gates in each PLA. This is an unchangeable property of the architecture of the CPLD.
NUM_BUFG_CLK: The number of BUFG sites for clock signals in the device. This is an unchangeable property of the architecture of the CPLD.
NUM_BUFG_GSR: The number of BUFG sites for set/reset signals in the device. This is an unchangeable property of the architecture of the CPLD.
NUM_BUFG_GTS: The number of BUFG sites for tristate signals in the device. This is an unchangeable property of the architecture of the CPLD.

Statics§

ZIA_MAP_32: A map of the connections that exist within the ZIA for 32-macrocell parts
ZIA_MAP_64: A map of the connections that exist within the ZIA for 64-macrocell parts
ZIA_MAP_128: A map of the connections that exist within the ZIA for 128-macrocell parts
ZIA_MAP_256: A map of the connections that exist within the ZIA for 256-macrocell parts
ZIA_MAP_384: A map of the connections that exist within the ZIA for 384-macrocell parts
ZIA_MAP_512: A map of the connections that exist within the ZIA for 512-macrocell parts

Functions§

fb_mc_num_to_iob_num: Function to map from a function block and macrocell number to the internal numbering scheme for I/O pins.
get_cdrst: Returns the function block and macrocell index of the global clock divider reset signal CDRST for the given device
get_device_structure: This function calls the passed-in callbacks to provide information about the structure of the CPLD. node_callback is called to “create” a new node, wire_callback is called to “create” a new wire, and connection_callback is called to connect one port on a node to a wire. The arguments to the callbacks are:
get_dge: Returns the function block and macrocell index of the global DataGATE enable signal DGE for the given device
get_gck: Returns the function block and macrocell index of the global clock signal GCKn for the given device
get_gsr: Returns the function block and macrocell index of the global set/reset signal GSR for the given device
get_gts: Returns the function block and macrocell index of the global tristate signal GTSn for the given device
get_pta: Returns the special PTA product term given a macrocell index
get_ptb: Returns the special PTB product term given a macrocell index
get_ptc: Returns the special PTC product term given a macrocell index
iob_num_to_fb_mc_num: Function to map from the internal numbering scheme for I/O pins to a function block and macrocell number.
zia_table_get_row: Helper function that returns a reference to one row of the ZIA map.