x86_64_assembler/encoder/
mod.rs

1#![doc = include_str!("readme.md")]
2
3use crate::instruction::Instruction;
4use gaia_types::{helpers::Architecture, Result};
5
6mod arithmetic;
7mod branch;
8mod helpers;
9mod misc;
10mod mov;
11mod sse;
12mod stack;
13
14/// 指令编码器，用于将指令编码为字节码
15#[derive(Debug, Clone)]
16pub struct InstructionEncoder {
17    architecture: Architecture,
18}
19
20impl InstructionEncoder {
21    /// 创建新的指令编码器
22    pub fn new(architecture: Architecture) -> Self {
23        Self { architecture }
24    }
25
26    /// 编码指令为字节码
27    pub fn encode(&self, instruction: &Instruction) -> Result<Vec<u8>> {
28        match instruction {
29            Instruction::Mov { dst, src } => self.encode_mov(dst, src),
30            Instruction::Push { op } => self.encode_push(op),
31            Instruction::Pop { dst } => self.encode_pop(dst),
32            Instruction::Add { dst, src } => self.encode_add(dst, src),
33            Instruction::Sub { dst, src } => self.encode_sub(dst, src),
34            Instruction::Call { target } => self.encode_call(target),
35            Instruction::Lea { dst, displacement, rip_relative } => self.encode_lea(dst, *displacement, *rip_relative),
36            Instruction::Ret => Ok(vec![0xC3]),
37            Instruction::Nop => Ok(vec![0x90]),
38            Instruction::Cmp { dst, src } => self.encode_cmp(dst, src),
39            Instruction::Jmp { target } => self.encode_jmp(target),
40            Instruction::Jcc { cond, target } => self.encode_jcc(cond, target),
41            Instruction::Jnz { target } => self.encode_jnz(target),
42            Instruction::Jz { target } => self.encode_jz(target),
43            Instruction::Dec { op } => self.encode_dec(op),
44            Instruction::Inc { op } => self.encode_inc(op),
45            Instruction::Movss { dst, src } => self.encode_movss(dst, src),
46            Instruction::Addss { dst, src } => self.encode_addss(dst, src),
47            Instruction::Subss { dst, src } => self.encode_subss(dst, src),
48            Instruction::Mulss { dst, src } => self.encode_mulss(dst, src),
49            Instruction::Divss { dst, src } => self.encode_divss(dst, src),
50            Instruction::Maxss { dst, src } => self.encode_maxss(dst, src),
51            Instruction::Xor { dst, src } => self.encode_xor(dst, src),
52            Instruction::Xorps { dst, src } => self.encode_xorps(dst, src),
53            Instruction::Imul { dst, src } => self.encode_imul(dst, src),
54            Instruction::Mul { src } => self.encode_unary_op(src, 4, "MUL"),
55            Instruction::Div { src } => self.encode_unary_op(src, 6, "DIV"),
56            Instruction::Idiv { src } => self.encode_unary_op(src, 7, "IDIV"),
57            Instruction::Cqo => Ok(vec![0x48, 0x99]),
58            Instruction::And { dst, src } => self.encode_and(dst, src),
59            Instruction::Or { dst, src } => self.encode_or(dst, src),
60            Instruction::Not { op } => self.encode_unary_op(op, 2, "NOT"),
61            Instruction::Neg { op } => self.encode_unary_op(op, 3, "NEG"),
62            Instruction::Shl { dst, src } => self.encode_shift(dst, src, 4, "SHL"),
63            Instruction::Shr { dst, src } => self.encode_shift(dst, src, 5, "SHR"),
64            Instruction::Test { dst, src } => self.encode_test(dst, src),
65            Instruction::Setcc { cond, dst } => self.encode_setcc_with_cond(cond, dst),
66            Instruction::Sete { dst } => self.encode_setcc(dst, 0x94, "SETE"),
67            Instruction::Setne { dst } => self.encode_setcc(dst, 0x95, "SETNE"),
68            Instruction::Setl { dst } => self.encode_setcc(dst, 0x9C, "SETL"),
69            Instruction::Setle { dst } => self.encode_setcc(dst, 0x9D, "SETLE"),
70            Instruction::Setg { dst } => self.encode_setcc(dst, 0x9F, "SETG"),
71            Instruction::Setge { dst } => self.encode_setcc(dst, 0x9E, "SETGE"),
72            Instruction::Movsx { dst, src, size } => self.encode_movsx(dst, src, *size),
73            Instruction::Movzx { dst, src, size } => self.encode_movzx(dst, src, *size),
74            Instruction::Label(_) => Ok(vec![]),
75        }
76    }
77}
x86_64_assembler/encoder/mod.rs

x86_64_assembler/encoder/
mod.rs
