Register information and driver to program xAPIC, X2APIC and I/O APIC
Data structures and functions used by 16-bit mode.
Data structures and functions used by 32-bit mode.
Data structures and functions used by IA-32e but not Protected Mode.
Functions to read and write control registers. See Intel Vol. 3a Section 2.5, especially Figure 2-7.
Support for the CPUID instructions.
A short-cut to the architecture (bits32 or bits64) this crate was compiled for.
Functions to read and write debug registers.
Functions and data-structures for working with descriptor tables.
Intel fence instructions
I/O port functionality.
Shared interrupt description and set-up code.
bits*::irq modules for arch-specific portions.
MSR value list and function to read and write them.
Instructions to generate random bits directly from the hardware (RDRAND and RDSEED).
Functionality to manipulate segment registers, build segement descriptors and selectors.
Helpers to program the task state segment. See Intel 3a, Chapter 7
Functions to read time stamp counters on x86.
Functions to flush the translation lookaside buffer (TLB).
Data structures and definitions used by Virtual Machine Extensions.
“Dereferences” the fs register at
“Dereferences” the gs register at
Generate a software interrupt. This is a macro argument needs to be an immediate.
x86 Protection levels