Crate ws63_pac 

Peripheral access API for WS63 microcontrollers (generated using svd2rust v0.37.1 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

pub use self::gpio0 as gpio1;

pub use self::gpio0 as gpio2;

pub use self::uart0 as uart1;

pub use self::uart0 as uart2;

pub use self::i2c0 as i2c1;

pub use self::spi0 as spi1;

pub use self::dma as sdma;

pub use self::gpio0 as ulp_gpio;

Modules

bt_em_ctl

Bluetooth exchange-memory control used while changing shared RAM ownership

cldo_crg

CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets

cmu

Clock management unit registers used by WS63 clock and PLL setup

dma

DMA controller with 4 channels

efuse

eFuse controller (OTP, v151)

fama_remap

SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection

generic

Common register and bit access and modify traits

glb_ctl_m

Main core global control - BCPU/MCPU reset status, chip reset, AON CRG

gpio0

GPIO controller for GPIO[7:0]

i2c0

I2C0 master controller

i2s

I2S/SIO synchronous audio interface (v151)

interrupt

Interrupt numbers, priority levels, and HART IDs.

io_config

IO multiplexing and pad control

km

Key Management - KLAD key derivation, keyslot locking, RKP root key protection

lsadc

Low-speed ADC controller (12-bit SAR, 6 channels, v154)

pke

Public Key Engine - modular arithmetic accelerator

pwm

PWM controller with 8 channels

rf_wb_ctl

SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control

riscv_patch

RISC-V instruction patch controller used to redirect mask-ROM entry points to application-provided fixes

rtc

Real-time clock (48-bit free-running counter, v100)

sfc_cfg

SPI Flash Controller configuration

share_mem_ctl

SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer

spacc

Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC

spi0

SPI0 master/slave controller (SSI v151)

sys_ctl0

System Control 0 - reset status, clock control, PLL config

sys_ctl1

System Control 1 - Interrupt Controller

tcxo

TCXO 64-bit free-running counter (v150)

timer

Timer module with 3 independent 32-bit timers (v150)

trng

True Random Number Generator

tsensor

Temperature sensor controller (v151)

uart0

UART0 - Universal Asynchronous Receiver/Transmitter

wdt

Watchdog timer (v151)

Structs

Peripherals

All the peripherals.

Constants

NVIC_PRIO_BITS

Number available in the NVIC for configuring priority

Type Aliases

BtEmCtl

Bluetooth exchange-memory control used while changing shared RAM ownership

CldoCrg

CLDO Clock and Reset Generator - clock enables, dividers, clock selects, soft resets

Cmu

Clock management unit registers used by WS63 clock and PLL setup

Dma

DMA controller with 4 channels

Efuse

eFuse controller (OTP, v151)

FamaRemap

SYS_CTL2 sub-block: Flash Address Map Remap - up to 12 regions for boot-time address redirection

GlbCtlM

Main core global control - BCPU/MCPU reset status, chip reset, AON CRG

Gpio0

GPIO controller for GPIO[7:0]

Gpio1

GPIO controller for GPIO[15:8]

Gpio2

GPIO controller for GPIO[18:16] — only 3 bits used; bits [7:3] are reserved and unused.

I2c0

I2C0 master controller

I2c1

I2C1 master controller

I2s

I2S/SIO synchronous audio interface (v151)

IoConfig

IO multiplexing and pad control

Km

Key Management - KLAD key derivation, keyslot locking, RKP root key protection

Lsadc

Low-speed ADC controller (12-bit SAR, 6 channels, v154)

Pke

Public Key Engine - modular arithmetic accelerator

Pwm

PWM controller with 8 channels

RfWbCtl

SYS_CTL2 sub-block: RF Wideband Control Register Block - WL/BT RF analog interface control

RiscvPatch

RISC-V instruction patch controller used to redirect mask-ROM entry points to application-provided fixes

Rtc

Real-time clock (48-bit free-running counter, v100)

Sdma

Secure DMA controller (4 channels, same layout as MDMA v151). Channels logically mapped as 8-11.

SfcCfg

SPI Flash Controller configuration

ShareMemCtl

SYS_CTL2 sub-block: Shared Memory Control - RAM config, RX/TX DMA descriptor rings for WiFi PHY↔Packet buffer

Spacc

Security accelerator - AES/SM4/LEA/TDES symmetric crypto, HASH/HMAC

Spi0

SPI0 master/slave controller (SSI v151)

Spi1

SPI1/QSPI controller (SSI v151)

SysCtl0

System Control 0 - reset status, clock control, PLL config

SysCtl1

System Control 1 - Interrupt Controller

Tcxo

TCXO 64-bit free-running counter (v150)

Timer

Timer module with 3 independent 32-bit timers (v150)

Trng

True Random Number Generator

Tsensor

Temperature sensor controller (v151)

Uart0

UART0 - Universal Asynchronous Receiver/Transmitter

Uart1

UART1 with flow control support

Uart2

UART2 with flow control support

UlpGpio

Ultra-low-power GPIO controller (8 pins, GPIO[107:114]). Same register layout as GPIO0.

Wdt

Watchdog timer (v151)