Type Alias DivL 

pub type DivL = Reg<DivLSpec>;

DIV_L (rw) register accessor: Baud rate divider low byte (write only when UART_CTL[div_en]=1 or UART not busy)

You can read this register and get div_l::R. You can reset, write, write_with_zero this register using div_l::W. You can also modify this register. See API.

For information about available fields see div_l module

Aliased Type

pub struct DivL { /* private fields */ }