[][src]Type Definition wip_s32k144::pdb1::CHDLY2

type CHDLY2 = Reg<u32, _CHDLY2>;

Channel n Delay 2 register

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see chdly2 module

Trait Implementations

impl Readable for CHDLY2[src]

read() method returns chdly2::R reader structure

impl ResetValue for CHDLY2[src]

Register CH%sDLY2 reset()'s with value 0

type Type = u32

Register size

impl Writable for CHDLY2[src]

write(|w| ..) method takes chdly2::W writer structure