w7500x_pac/crg/
pwm5clk_pvsr.rs

1#[doc = "Register `PWM5CLK_PVSR` reader"]
2pub struct R(crate::R<PWM5CLK_PVSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PWM5CLK_PVSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PWM5CLK_PVSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PWM5CLK_PVSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PWM5CLK_PVSR` writer"]
17pub struct W(crate::W<PWM5CLK_PVSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PWM5CLK_PVSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PWM5CLK_PVSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PWM5CLK_PVSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "PWMnCLK prescale value select bits\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum PCPS_A {
41    #[doc = "0: 1/1"]
42    BYPASS = 0,
43    #[doc = "1: 1/2"]
44    HALF = 1,
45    #[doc = "2: 1/4"]
46    BY4 = 2,
47    #[doc = "3: 1/8"]
48    BY8 = 3,
49    #[doc = "4: 1/16"]
50    BY16 = 4,
51    #[doc = "5: 1/32"]
52    BY32 = 5,
53    #[doc = "6: 1/64"]
54    BY64 = 6,
55    #[doc = "7: 1/128"]
56    BY128 = 7,
57}
58impl From<PCPS_A> for u8 {
59    #[inline(always)]
60    fn from(variant: PCPS_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `PCPS` reader - PWMnCLK prescale value select bits"]
65pub struct PCPS_R(crate::FieldReader<u8>);
66impl PCPS_R {
67    #[inline(always)]
68    pub(crate) fn new(bits: u8) -> Self {
69        PCPS_R(crate::FieldReader::new(bits))
70    }
71    #[doc = r"Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> PCPS_A {
74        match self.bits {
75            0 => PCPS_A::BYPASS,
76            1 => PCPS_A::HALF,
77            2 => PCPS_A::BY4,
78            3 => PCPS_A::BY8,
79            4 => PCPS_A::BY16,
80            5 => PCPS_A::BY32,
81            6 => PCPS_A::BY64,
82            7 => PCPS_A::BY128,
83            _ => unreachable!(),
84        }
85    }
86    #[doc = "Checks if the value of the field is `BYPASS`"]
87    #[inline(always)]
88    pub fn is_bypass(&self) -> bool {
89        **self == PCPS_A::BYPASS
90    }
91    #[doc = "Checks if the value of the field is `HALF`"]
92    #[inline(always)]
93    pub fn is_half(&self) -> bool {
94        **self == PCPS_A::HALF
95    }
96    #[doc = "Checks if the value of the field is `BY4`"]
97    #[inline(always)]
98    pub fn is_by4(&self) -> bool {
99        **self == PCPS_A::BY4
100    }
101    #[doc = "Checks if the value of the field is `BY8`"]
102    #[inline(always)]
103    pub fn is_by8(&self) -> bool {
104        **self == PCPS_A::BY8
105    }
106    #[doc = "Checks if the value of the field is `BY16`"]
107    #[inline(always)]
108    pub fn is_by16(&self) -> bool {
109        **self == PCPS_A::BY16
110    }
111    #[doc = "Checks if the value of the field is `BY32`"]
112    #[inline(always)]
113    pub fn is_by32(&self) -> bool {
114        **self == PCPS_A::BY32
115    }
116    #[doc = "Checks if the value of the field is `BY64`"]
117    #[inline(always)]
118    pub fn is_by64(&self) -> bool {
119        **self == PCPS_A::BY64
120    }
121    #[doc = "Checks if the value of the field is `BY128`"]
122    #[inline(always)]
123    pub fn is_by128(&self) -> bool {
124        **self == PCPS_A::BY128
125    }
126}
127impl core::ops::Deref for PCPS_R {
128    type Target = crate::FieldReader<u8>;
129    #[inline(always)]
130    fn deref(&self) -> &Self::Target {
131        &self.0
132    }
133}
134#[doc = "Field `PCPS` writer - PWMnCLK prescale value select bits"]
135pub struct PCPS_W<'a> {
136    w: &'a mut W,
137}
138impl<'a> PCPS_W<'a> {
139    #[doc = r"Writes `variant` to the field"]
140    #[inline(always)]
141    pub fn variant(self, variant: PCPS_A) -> &'a mut W {
142        self.bits(variant.into())
143    }
144    #[doc = "1/1"]
145    #[inline(always)]
146    pub fn bypass(self) -> &'a mut W {
147        self.variant(PCPS_A::BYPASS)
148    }
149    #[doc = "1/2"]
150    #[inline(always)]
151    pub fn half(self) -> &'a mut W {
152        self.variant(PCPS_A::HALF)
153    }
154    #[doc = "1/4"]
155    #[inline(always)]
156    pub fn by4(self) -> &'a mut W {
157        self.variant(PCPS_A::BY4)
158    }
159    #[doc = "1/8"]
160    #[inline(always)]
161    pub fn by8(self) -> &'a mut W {
162        self.variant(PCPS_A::BY8)
163    }
164    #[doc = "1/16"]
165    #[inline(always)]
166    pub fn by16(self) -> &'a mut W {
167        self.variant(PCPS_A::BY16)
168    }
169    #[doc = "1/32"]
170    #[inline(always)]
171    pub fn by32(self) -> &'a mut W {
172        self.variant(PCPS_A::BY32)
173    }
174    #[doc = "1/64"]
175    #[inline(always)]
176    pub fn by64(self) -> &'a mut W {
177        self.variant(PCPS_A::BY64)
178    }
179    #[doc = "1/128"]
180    #[inline(always)]
181    pub fn by128(self) -> &'a mut W {
182        self.variant(PCPS_A::BY128)
183    }
184    #[doc = r"Writes raw bits to the field"]
185    #[inline(always)]
186    pub fn bits(self, value: u8) -> &'a mut W {
187        self.w.bits = (self.w.bits & !7) | (value as u32 & 7);
188        self.w
189    }
190}
191impl R {
192    #[doc = "Bits 0:2 - PWMnCLK prescale value select bits"]
193    #[inline(always)]
194    pub fn pcps(&self) -> PCPS_R {
195        PCPS_R::new((self.bits & 7) as u8)
196    }
197}
198impl W {
199    #[doc = "Bits 0:2 - PWMnCLK prescale value select bits"]
200    #[inline(always)]
201    pub fn pcps(&mut self) -> PCPS_W {
202        PCPS_W { w: self }
203    }
204    #[doc = "Writes raw bits to the register."]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.0.bits(bits);
208        self
209    }
210}
211#[doc = "PWM5CLK prescale value select register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwm5clk_pvsr](index.html) module"]
212pub struct PWM5CLK_PVSR_SPEC;
213impl crate::RegisterSpec for PWM5CLK_PVSR_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [pwm5clk_pvsr::R](R) reader structure"]
217impl crate::Readable for PWM5CLK_PVSR_SPEC {
218    type Reader = R;
219}
220#[doc = "`write(|w| ..)` method takes [pwm5clk_pvsr::W](W) writer structure"]
221impl crate::Writable for PWM5CLK_PVSR_SPEC {
222    type Writer = W;
223}
224#[doc = "`reset()` method sets PWM5CLK_PVSR to value 0"]
225impl crate::Resettable for PWM5CLK_PVSR_SPEC {
226    #[inline(always)]
227    fn reset_value() -> Self::Ux {
228        0
229    }
230}
w7500x_pac/crg/pwm5clk_pvsr.rs

w7500x_pac/crg/
pwm5clk_pvsr.rs
