Enum w5500_ll::Reg

#[repr(u16)]
pub enum Reg {
    MR,
    GAR0,
    GAR1,
    GAR2,
    GAR3,
    SUBR0,
    SUBR1,
    SUBR2,
    SUBR3,
    SHAR0,
    SHAR1,
    SHAR2,
    SHAR3,
    SHAR4,
    SHAR5,
    SIPR0,
    SIPR1,
    SIPR2,
    SIPR3,
    INTLEVEL0,
    INTLEVEL1,
    IR,
    IMR,
    SIR,
    SIMR,
    RTR0,
    RTR1,
    RCR,
    PTIMER,
    PMAGIC,
    PHAR0,
    PHAR1,
    PHAR2,
    PHAR3,
    PHAR4,
    PHAR5,
    PSID0,
    PSID1,
    PMRU0,
    PMRU1,
    UIPR0,
    UIPR1,
    UIPR2,
    UIPR3,
    UPORTR0,
    UPORTR1,
    PHYCFGR,
    VERSIONR,
}

W5500 common register addresses.

Variants

MR

Address of the MR register.

GAR0

Address of the GAR register, index 0.

GAR1

Address of the GAR register, index 1.

GAR2

Address of the GAR register, index 2.

GAR3

Address of the GAR register, index 3.

SUBR0

Address of the SUBR register, index 0.

SUBR1

Address of the SUBR register, index 1.

SUBR2

Address of the SUBR register, index 2.

SUBR3

Address of the SUBR register, index 3.

SHAR0

Address of the SHAR register, index 0.

SHAR1

Address of the SHAR register, index 1.

SHAR2

Address of the SHAR register, index 2.

SHAR3

Address of the SHAR register, index 3.

SHAR4

Address of the SHAR register, index 4.

SHAR5

Address of the SHAR register, index 5.

SIPR0

Address of the SIPR register, index 0.

SIPR1

Address of the SIPR register, index 1.

SIPR2

Address of the SIPR register, index 2.

SIPR3

Address of the SIPR register, index 3.

INTLEVEL0

Address of the INTLEVEL register, index 0.

INTLEVEL1

Address of the INTLEVEL register, index 1.

IR

Address of the IR register.

IMR

Address of the IMR register.

SIR

Address of the SIR register.

SIMR

Address of the SIMR register.

RTR0

Address of the RTR register, index 0.

RTR1

Address of the RTR register, index 1.

RCR

Address of the RCR register.

PTIMER

Address of the PTIMER register.

PMAGIC

Address of the PMAGIC register.

PHAR0

Address of the PHAR register, index 0.

PHAR1

Address of the PHAR register, index 1.

PHAR2

Address of the PHAR register, index 2.

PHAR3

Address of the PHAR register, index 3.

PHAR4

Address of the PHAR register, index 4.

PHAR5

Address of the PHAR register, index 5.

PSID0

Address of the PSID register, index 0.

PSID1

Address of the PSID register, index 1.

PMRU0

Address of the PMRU register, index 0.

PMRU1

Address of the PMRU register, index 1.

UIPR0

Address of the UIPR register, index 0.

UIPR1

Address of the UIPR register, index 1.

UIPR2

Address of the UIPR register, index 2.

UIPR3

Address of the UIPR register, index 3.

UPORTR0

Address of the UPORTR register, index 0.

UPORTR1

Address of the UPORTR register, index 1.

PHYCFGR

Address of the PHYCFGR register.

VERSIONR

Address of the VERSIONR register.

Implementations

impl Reg

pub const fn addr(self) -> u16

Get the address of the register.

Example

use w5500_ll::Reg;

assert_eq!(Reg::VERSIONR.addr(), 0x0039);

pub const fn is_ro(self) -> bool

Returns true if the register is read-only.

Example

use w5500_ll::Reg;

assert!(Reg::VERSIONR.is_ro());
assert!(!Reg::MR.is_ro());

Trait Implementations

impl Clone for Reg

fn clone(&self) -> Reg

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Reg

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<Reg> for u16

fn from(reg: Reg) -> Self

Performs the conversion.

impl PartialEq<Reg> for Reg

fn eq(&self, other: &Reg) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl TryFrom<u16> for Reg

type Error = u16

The type returned in the event of a conversion error.

fn try_from(val: u16) -> Result<Self, Self::Error>

Performs the conversion.

impl Copy for Reg

impl Eq for Reg

impl StructuralEq for Reg

impl StructuralPartialEq for Reg