vorago_shared_periphs/
pins.rs

1use crate::sysconfig::reset_peripheral_for_cycles;
2
3pub use crate::gpio::{Pin, PinId, PinIdProvider, Port};
4
5use crate::PeripheralSelect;
6use crate::sealed::Sealed;
7#[cfg(feature = "vor1x")]
8use va108xx as pac;
9#[cfg(feature = "vor4x")]
10use va416xx as pac;
11
12pub trait PinMarker: Sealed {
13    const ID: PinId;
14}
15
16macro_rules! pin_id {
17    ($Id:ident, $Port:path, $num:literal) => {
18        // Need paste macro to use ident in doc attribute
19        paste::paste! {
20            #[doc = "Pin ID representing pin " $Id]
21            #[derive(Debug)]
22            pub enum $Id {}
23
24            impl $crate::sealed::Sealed for $Id {}
25            impl PinIdProvider for $Id {
26                const ID: PinId = PinId::new_unchecked($Port, $num);
27            }
28
29            impl PinMarker for Pin<$Id> {
30                const ID: PinId = $Id::ID;
31            }
32        }
33    };
34}
35
36impl<I: PinIdProvider + Sealed> Sealed for Pin<I> {}
37
38pin_id!(Pa0, Port::A, 0);
39pin_id!(Pa1, Port::A, 1);
40pin_id!(Pa2, Port::A, 2);
41pin_id!(Pa3, Port::A, 3);
42pin_id!(Pa4, Port::A, 4);
43pin_id!(Pa5, Port::A, 5);
44pin_id!(Pa6, Port::A, 6);
45pin_id!(Pa7, Port::A, 7);
46pin_id!(Pa8, Port::A, 8);
47pin_id!(Pa9, Port::A, 9);
48pin_id!(Pa10, Port::A, 10);
49pin_id!(Pa11, Port::A, 11);
50pin_id!(Pa12, Port::A, 12);
51pin_id!(Pa13, Port::A, 13);
52pin_id!(Pa14, Port::A, 14);
53pin_id!(Pa15, Port::A, 15);
54#[cfg(feature = "vor1x")]
55pin_id!(Pa16, Port::A, 16);
56#[cfg(feature = "vor1x")]
57pin_id!(Pa17, Port::A, 17);
58#[cfg(feature = "vor1x")]
59pin_id!(Pa18, Port::A, 18);
60#[cfg(feature = "vor1x")]
61pin_id!(Pa19, Port::A, 19);
62#[cfg(feature = "vor1x")]
63pin_id!(Pa20, Port::A, 20);
64#[cfg(feature = "vor1x")]
65pin_id!(Pa21, Port::A, 21);
66#[cfg(feature = "vor1x")]
67pin_id!(Pa22, Port::A, 22);
68#[cfg(feature = "vor1x")]
69pin_id!(Pa23, Port::A, 23);
70#[cfg(feature = "vor1x")]
71pin_id!(Pa24, Port::A, 24);
72#[cfg(feature = "vor1x")]
73pin_id!(Pa25, Port::A, 25);
74#[cfg(feature = "vor1x")]
75pin_id!(Pa26, Port::A, 26);
76#[cfg(feature = "vor1x")]
77#[cfg(feature = "vor1x")]
78pin_id!(Pa27, Port::A, 27);
79#[cfg(feature = "vor1x")]
80pin_id!(Pa28, Port::A, 28);
81#[cfg(feature = "vor1x")]
82pin_id!(Pa29, Port::A, 29);
83#[cfg(feature = "vor1x")]
84pin_id!(Pa30, Port::A, 30);
85#[cfg(feature = "vor1x")]
86pin_id!(Pa31, Port::A, 31);
87
88pin_id!(Pb0, Port::B, 0);
89pin_id!(Pb1, Port::B, 1);
90pin_id!(Pb2, Port::B, 2);
91pin_id!(Pb3, Port::B, 3);
92pin_id!(Pb4, Port::B, 4);
93#[cfg(not(feature = "va41628"))]
94pin_id!(Pb5, Port::B, 5);
95#[cfg(not(feature = "va41628"))]
96pin_id!(Pb6, Port::B, 6);
97#[cfg(not(feature = "va41628"))]
98pin_id!(Pb7, Port::B, 7);
99#[cfg(not(feature = "va41628"))]
100pin_id!(Pb8, Port::B, 8);
101#[cfg(not(feature = "va41628"))]
102pin_id!(Pb9, Port::B, 9);
103#[cfg(not(feature = "va41628"))]
104pin_id!(Pb10, Port::B, 10);
105#[cfg(not(feature = "va41628"))]
106pin_id!(Pb11, Port::B, 11);
107pin_id!(Pb12, Port::B, 12);
108pin_id!(Pb13, Port::B, 13);
109pin_id!(Pb14, Port::B, 14);
110pin_id!(Pb15, Port::B, 15);
111#[cfg(feature = "vor1x")]
112pin_id!(Pb16, Port::B, 16);
113#[cfg(feature = "vor1x")]
114pin_id!(Pb17, Port::B, 17);
115#[cfg(feature = "vor1x")]
116pin_id!(Pb18, Port::B, 18);
117#[cfg(feature = "vor1x")]
118pin_id!(Pb19, Port::B, 19);
119#[cfg(feature = "vor1x")]
120pin_id!(Pb20, Port::B, 20);
121#[cfg(feature = "vor1x")]
122pin_id!(Pb21, Port::B, 21);
123#[cfg(feature = "vor1x")]
124pin_id!(Pb22, Port::B, 22);
125#[cfg(feature = "vor1x")]
126pin_id!(Pb23, Port::B, 23);
127
128cfg_if::cfg_if! {
129    if #[cfg(feature = "vor4x")] {
130        pin_id!(Pc0, Port::C, 0);
131        pin_id!(Pc1, Port::C, 1);
132        pin_id!(Pc2, Port::C, 2);
133        pin_id!(Pc3, Port::C, 3);
134        pin_id!(Pc4, Port::C, 4);
135        pin_id!(Pc5, Port::C, 5);
136        pin_id!(Pc6, Port::C, 6);
137        pin_id!(Pc7, Port::C, 7);
138        pin_id!(Pc8, Port::C, 8);
139        pin_id!(Pc9, Port::C, 9);
140        pin_id!(Pc10, Port::C, 10);
141        pin_id!(Pc11, Port::C, 11);
142        pin_id!(Pc12, Port::C, 12);
143        #[cfg(not(feature = "va41628"))]
144        pin_id!(Pc13, Port::C, 13);
145        pin_id!(Pc14, Port::C, 14);
146        #[cfg(not(feature = "va41628"))]
147        pin_id!(Pc15, Port::C, 15);
148
149        #[cfg(not(feature = "va41628"))]
150        pin_id!(Pd0, Port::D, 0);
151        #[cfg(not(feature = "va41628"))]
152        pin_id!(Pd1, Port::D, 1);
153        #[cfg(not(feature = "va41628"))]
154        pin_id!(Pd2, Port::D, 2);
155        #[cfg(not(feature = "va41628"))]
156        pin_id!(Pd3, Port::D, 3);
157        #[cfg(not(feature = "va41628"))]
158        pin_id!(Pd4, Port::D, 4);
159        #[cfg(not(feature = "va41628"))]
160        pin_id!(Pd5, Port::D, 5);
161        #[cfg(not(feature = "va41628"))]
162        pin_id!(Pd6, Port::D, 6);
163        #[cfg(not(feature = "va41628"))]
164        pin_id!(Pd7, Port::D, 7);
165        #[cfg(not(feature = "va41628"))]
166        pin_id!(Pd8, Port::D, 8);
167        #[cfg(not(feature = "va41628"))]
168        pin_id!(Pd9, Port::D, 9);
169        pin_id!(Pd10, Port::D, 10);
170        pin_id!(Pd11, Port::D, 11);
171        pin_id!(Pd12, Port::D, 12);
172        pin_id!(Pd13, Port::D, 13);
173        pin_id!(Pd14, Port::D, 14);
174        pin_id!(Pd15, Port::D, 15);
175
176        pin_id!(Pe0, Port::E, 0);
177        pin_id!(Pe1, Port::E, 1);
178        pin_id!(Pe2, Port::E, 2);
179        pin_id!(Pe3, Port::E, 3);
180        pin_id!(Pe4, Port::E, 4);
181        pin_id!(Pe5, Port::E, 5);
182        pin_id!(Pe6, Port::E, 6);
183        pin_id!(Pe7, Port::E, 7);
184        pin_id!(Pe8, Port::E, 8);
185        pin_id!(Pe9, Port::E, 9);
186        #[cfg(not(feature = "va41628"))]
187        pin_id!(Pe10, Port::E, 10);
188        #[cfg(not(feature = "va41628"))]
189        pin_id!(Pe11, Port::E, 11);
190        pin_id!(Pe12, Port::E, 12);
191        pin_id!(Pe13, Port::E, 13);
192        pin_id!(Pe14, Port::E, 14);
193        pin_id!(Pe15, Port::E, 15);
194
195        pin_id!(Pf0, Port::F, 0);
196        pin_id!(Pf1, Port::F, 1);
197        #[cfg(not(feature = "va41628"))]
198        pin_id!(Pf2, Port::F, 2);
199        #[cfg(not(feature = "va41628"))]
200        pin_id!(Pf3, Port::F, 3);
201        #[cfg(not(feature = "va41628"))]
202        pin_id!(Pf4, Port::F, 4);
203        #[cfg(not(feature = "va41628"))]
204        pin_id!(Pf5, Port::F, 5);
205        #[cfg(not(feature = "va41628"))]
206        pin_id!(Pf6, Port::F, 6);
207        #[cfg(not(feature = "va41628"))]
208        pin_id!(Pf7, Port::F, 7);
209        #[cfg(not(feature = "va41628"))]
210        pin_id!(Pf8, Port::F, 8);
211        pin_id!(Pf9, Port::F, 9);
212        #[cfg(not(feature = "va41628"))]
213        pin_id!(Pf10, Port::F, 10);
214        pin_id!(Pf11, Port::F, 11);
215        pin_id!(Pf12, Port::F, 12);
216        pin_id!(Pf13, Port::F, 13);
217        pin_id!(Pf14, Port::F, 14);
218        pin_id!(Pf15, Port::F, 15);
219
220        pin_id!(Pg0, Port::G, 0);
221        pin_id!(Pg1, Port::G, 1);
222        pin_id!(Pg2, Port::G, 2);
223        pin_id!(Pg3, Port::G, 3);
224        pin_id!(Pg4, Port::G, 4);
225        pin_id!(Pg5, Port::G, 5);
226        pin_id!(Pg6, Port::G, 6);
227        pin_id!(Pg7, Port::G, 7);
228    }
229}
230
231/// Resource management singleton for GPIO PORT A.
232pub struct PinsA {
233    pub pa0: Pin<Pa0>,
234    pub pa1: Pin<Pa1>,
235    pub pa2: Pin<Pa2>,
236    pub pa3: Pin<Pa3>,
237    pub pa4: Pin<Pa4>,
238    pub pa5: Pin<Pa5>,
239    pub pa6: Pin<Pa6>,
240    pub pa7: Pin<Pa7>,
241    pub pa8: Pin<Pa8>,
242    pub pa9: Pin<Pa9>,
243    pub pa10: Pin<Pa10>,
244    pub pa11: Pin<Pa11>,
245    pub pa12: Pin<Pa12>,
246    pub pa13: Pin<Pa13>,
247    pub pa14: Pin<Pa14>,
248    pub pa15: Pin<Pa15>,
249    #[cfg(feature = "vor1x")]
250    pub pa16: Pin<Pa16>,
251    #[cfg(feature = "vor1x")]
252    pub pa17: Pin<Pa17>,
253    #[cfg(feature = "vor1x")]
254    pub pa18: Pin<Pa18>,
255    #[cfg(feature = "vor1x")]
256    pub pa19: Pin<Pa19>,
257    #[cfg(feature = "vor1x")]
258    pub pa20: Pin<Pa20>,
259    #[cfg(feature = "vor1x")]
260    pub pa21: Pin<Pa21>,
261    #[cfg(feature = "vor1x")]
262    pub pa22: Pin<Pa22>,
263    #[cfg(feature = "vor1x")]
264    pub pa23: Pin<Pa23>,
265    #[cfg(feature = "vor1x")]
266    pub pa24: Pin<Pa24>,
267    #[cfg(feature = "vor1x")]
268    pub pa25: Pin<Pa25>,
269    #[cfg(feature = "vor1x")]
270    pub pa26: Pin<Pa26>,
271    #[cfg(feature = "vor1x")]
272    pub pa27: Pin<Pa27>,
273    #[cfg(feature = "vor1x")]
274    pub pa28: Pin<Pa28>,
275    #[cfg(feature = "vor1x")]
276    pub pa29: Pin<Pa29>,
277    #[cfg(feature = "vor1x")]
278    pub pa30: Pin<Pa30>,
279    #[cfg(feature = "vor1x")]
280    pub pa31: Pin<Pa31>,
281}
282
283impl PinsA {
284    pub fn new(_port_a: pac::Porta) -> Self {
285        let syscfg = unsafe { pac::Sysconfig::steal() };
286        reset_peripheral_for_cycles(PeripheralSelect::PortA, 2);
287        syscfg.peripheral_clk_enable().modify(|_, w| {
288            w.porta().set_bit();
289            #[cfg(feature = "vor1x")]
290            w.gpio().set_bit();
291            w.ioconfig().set_bit()
292        });
293        Self {
294            pa0: Pin::__new(),
295            pa1: Pin::__new(),
296            pa2: Pin::__new(),
297            pa3: Pin::__new(),
298            pa4: Pin::__new(),
299            pa5: Pin::__new(),
300            pa6: Pin::__new(),
301            pa7: Pin::__new(),
302            pa8: Pin::__new(),
303            pa9: Pin::__new(),
304            pa10: Pin::__new(),
305            pa11: Pin::__new(),
306            pa12: Pin::__new(),
307            pa13: Pin::__new(),
308            pa14: Pin::__new(),
309            pa15: Pin::__new(),
310            #[cfg(feature = "vor1x")]
311            pa16: Pin::__new(),
312            #[cfg(feature = "vor1x")]
313            pa17: Pin::__new(),
314            #[cfg(feature = "vor1x")]
315            pa18: Pin::__new(),
316            #[cfg(feature = "vor1x")]
317            pa19: Pin::__new(),
318            #[cfg(feature = "vor1x")]
319            pa20: Pin::__new(),
320            #[cfg(feature = "vor1x")]
321            pa21: Pin::__new(),
322            #[cfg(feature = "vor1x")]
323            pa22: Pin::__new(),
324            #[cfg(feature = "vor1x")]
325            pa23: Pin::__new(),
326            #[cfg(feature = "vor1x")]
327            pa24: Pin::__new(),
328            #[cfg(feature = "vor1x")]
329            pa25: Pin::__new(),
330            #[cfg(feature = "vor1x")]
331            pa26: Pin::__new(),
332            #[cfg(feature = "vor1x")]
333            pa27: Pin::__new(),
334            #[cfg(feature = "vor1x")]
335            pa28: Pin::__new(),
336            #[cfg(feature = "vor1x")]
337            pa29: Pin::__new(),
338            #[cfg(feature = "vor1x")]
339            pa30: Pin::__new(),
340            #[cfg(feature = "vor1x")]
341            pa31: Pin::__new(),
342        }
343    }
344}
345
346/// Resource management singleton for GPIO PORT B.
347pub struct PinsB {
348    pub pb0: Pin<Pb0>,
349    pub pb1: Pin<Pb1>,
350    pub pb2: Pin<Pb2>,
351    pub pb3: Pin<Pb3>,
352    pub pb4: Pin<Pb4>,
353    #[cfg(not(feature = "va41628"))]
354    pub pb5: Pin<Pb5>,
355    #[cfg(not(feature = "va41628"))]
356    pub pb6: Pin<Pb6>,
357    #[cfg(not(feature = "va41628"))]
358    pub pb7: Pin<Pb7>,
359    #[cfg(not(feature = "va41628"))]
360    pub pb8: Pin<Pb8>,
361    #[cfg(not(feature = "va41628"))]
362    pub pb9: Pin<Pb9>,
363    #[cfg(not(feature = "va41628"))]
364    pub pb10: Pin<Pb10>,
365    #[cfg(not(feature = "va41628"))]
366    pub pb11: Pin<Pb11>,
367    pub pb12: Pin<Pb12>,
368    pub pb13: Pin<Pb13>,
369    pub pb14: Pin<Pb14>,
370    pub pb15: Pin<Pb15>,
371    #[cfg(feature = "vor1x")]
372    pub pb16: Pin<Pb16>,
373    #[cfg(feature = "vor1x")]
374    pub pb17: Pin<Pb17>,
375    #[cfg(feature = "vor1x")]
376    pub pb18: Pin<Pb18>,
377    #[cfg(feature = "vor1x")]
378    pub pb19: Pin<Pb19>,
379    #[cfg(feature = "vor1x")]
380    pub pb20: Pin<Pb20>,
381    #[cfg(feature = "vor1x")]
382    pub pb21: Pin<Pb21>,
383    #[cfg(feature = "vor1x")]
384    pub pb22: Pin<Pb22>,
385    #[cfg(feature = "vor1x")]
386    pub pb23: Pin<Pb23>,
387}
388
389impl PinsB {
390    pub fn new(_port_b: pac::Portb) -> Self {
391        let syscfg = unsafe { pac::Sysconfig::steal() };
392        reset_peripheral_for_cycles(PeripheralSelect::PortB, 2);
393        syscfg.peripheral_clk_enable().modify(|_, w| {
394            w.portb().set_bit();
395            #[cfg(feature = "vor1x")]
396            w.gpio().set_bit();
397            w.ioconfig().set_bit()
398        });
399        Self {
400            pb0: Pin::__new(),
401            pb1: Pin::__new(),
402            pb2: Pin::__new(),
403            pb3: Pin::__new(),
404            pb4: Pin::__new(),
405            #[cfg(not(feature = "va41628"))]
406            pb5: Pin::__new(),
407            #[cfg(not(feature = "va41628"))]
408            pb6: Pin::__new(),
409            #[cfg(not(feature = "va41628"))]
410            pb7: Pin::__new(),
411            #[cfg(not(feature = "va41628"))]
412            pb8: Pin::__new(),
413            #[cfg(not(feature = "va41628"))]
414            pb9: Pin::__new(),
415            #[cfg(not(feature = "va41628"))]
416            pb10: Pin::__new(),
417            #[cfg(not(feature = "va41628"))]
418            pb11: Pin::__new(),
419            pb12: Pin::__new(),
420            pb13: Pin::__new(),
421            pb14: Pin::__new(),
422            pb15: Pin::__new(),
423            #[cfg(feature = "vor1x")]
424            pb16: Pin::__new(),
425            #[cfg(feature = "vor1x")]
426            pb17: Pin::__new(),
427            #[cfg(feature = "vor1x")]
428            pb18: Pin::__new(),
429            #[cfg(feature = "vor1x")]
430            pb19: Pin::__new(),
431            #[cfg(feature = "vor1x")]
432            pb20: Pin::__new(),
433            #[cfg(feature = "vor1x")]
434            pb21: Pin::__new(),
435            #[cfg(feature = "vor1x")]
436            pb22: Pin::__new(),
437            #[cfg(feature = "vor1x")]
438            pb23: Pin::__new(),
439        }
440    }
441}
442
443cfg_if::cfg_if! {
444    if #[cfg(feature = "vor4x")] {
445        /// Resource management singleton for GPIO PORT C.
446        pub struct PinsC {
447            pub pc0: Pin<Pc0>,
448            pub pc1: Pin<Pc1>,
449            pub pc2: Pin<Pc2>,
450            pub pc3: Pin<Pc3>,
451            pub pc4: Pin<Pc4>,
452            pub pc5: Pin<Pc5>,
453            pub pc6: Pin<Pc6>,
454            pub pc7: Pin<Pc7>,
455            pub pc8: Pin<Pc8>,
456            pub pc9: Pin<Pc9>,
457            pub pc10: Pin<Pc10>,
458            pub pc11: Pin<Pc11>,
459            pub pc12: Pin<Pc12>,
460            #[cfg(not(feature = "va41628"))]
461            pub pc13: Pin<Pc13>,
462            pub pc14: Pin<Pc14>,
463            #[cfg(not(feature = "va41628"))]
464            pub pc15: Pin<Pc15>,
465        }
466
467        impl PinsC {
468            pub fn new(_port_c: pac::Portc) -> Self {
469                let syscfg = unsafe { pac::Sysconfig::steal() };
470                reset_peripheral_for_cycles(PeripheralSelect::PortC, 2);
471                syscfg.peripheral_clk_enable().modify(|_, w| {
472                    w.portc().set_bit();
473                    w.ioconfig().set_bit()
474                });
475                Self {
476                    pc0: Pin::__new(),
477                    pc1: Pin::__new(),
478                    pc2: Pin::__new(),
479                    pc3: Pin::__new(),
480                    pc4: Pin::__new(),
481                    pc5: Pin::__new(),
482                    pc6: Pin::__new(),
483                    pc7: Pin::__new(),
484                    pc8: Pin::__new(),
485                    pc9: Pin::__new(),
486                    pc10: Pin::__new(),
487                    pc11: Pin::__new(),
488                    pc12: Pin::__new(),
489            #[cfg(not(feature = "va41628"))]
490                    pc13: Pin::__new(),
491                    pc14: Pin::__new(),
492            #[cfg(not(feature = "va41628"))]
493                    pc15: Pin::__new(),
494                }
495            }
496        }
497
498        /// Resource management singleton for GPIO PORT D.
499        pub struct PinsD {
500            #[cfg(not(feature = "va41628"))]
501            pub pd0: Pin<Pd0>,
502            #[cfg(not(feature = "va41628"))]
503            pub pd1: Pin<Pd1>,
504            #[cfg(not(feature = "va41628"))]
505            pub pd2: Pin<Pd2>,
506            #[cfg(not(feature = "va41628"))]
507            pub pd3: Pin<Pd3>,
508            #[cfg(not(feature = "va41628"))]
509            pub pd4: Pin<Pd4>,
510            #[cfg(not(feature = "va41628"))]
511            pub pd5: Pin<Pd5>,
512            #[cfg(not(feature = "va41628"))]
513            pub pd6: Pin<Pd6>,
514            #[cfg(not(feature = "va41628"))]
515            pub pd7: Pin<Pd7>,
516            #[cfg(not(feature = "va41628"))]
517            pub pd8: Pin<Pd8>,
518            #[cfg(not(feature = "va41628"))]
519            pub pd9: Pin<Pd9>,
520            pub pd10: Pin<Pd10>,
521            pub pd11: Pin<Pd11>,
522            pub pd12: Pin<Pd12>,
523            pub pd13: Pin<Pd13>,
524            pub pd14: Pin<Pd14>,
525            pub pd15: Pin<Pd15>,
526        }
527
528        impl PinsD {
529            pub fn new(_port_d: pac::Portd) -> Self {
530                let syscfg = unsafe { pac::Sysconfig::steal() };
531                reset_peripheral_for_cycles(PeripheralSelect::PortD, 2);
532                syscfg.peripheral_clk_enable().modify(|_, w| {
533                    w.portd().set_bit();
534                    w.ioconfig().set_bit()
535                });
536                Self {
537                    #[cfg(not(feature = "va41628"))]
538                    pd0: Pin::__new(),
539                    #[cfg(not(feature = "va41628"))]
540                    pd1: Pin::__new(),
541                    #[cfg(not(feature = "va41628"))]
542                    pd2: Pin::__new(),
543                    #[cfg(not(feature = "va41628"))]
544                    pd3: Pin::__new(),
545                    #[cfg(not(feature = "va41628"))]
546                    pd4: Pin::__new(),
547                    #[cfg(not(feature = "va41628"))]
548                    pd5: Pin::__new(),
549                    #[cfg(not(feature = "va41628"))]
550                    pd6: Pin::__new(),
551                    #[cfg(not(feature = "va41628"))]
552                    pd7: Pin::__new(),
553                    #[cfg(not(feature = "va41628"))]
554                    pd8: Pin::__new(),
555                    #[cfg(not(feature = "va41628"))]
556                    pd9: Pin::__new(),
557                    pd10: Pin::__new(),
558                    pd11: Pin::__new(),
559                    pd12: Pin::__new(),
560                    pd13: Pin::__new(),
561                    pd14: Pin::__new(),
562                    pd15: Pin::__new(),
563                }
564            }
565        }
566
567        /// Resource management singleton for GPIO PORT E.
568        pub struct PinsE {
569            pub pe0: Pin<Pe0>,
570            pub pe1: Pin<Pe1>,
571            pub pe2: Pin<Pe2>,
572            pub pe3: Pin<Pe3>,
573            pub pe4: Pin<Pe4>,
574            pub pe5: Pin<Pe5>,
575            pub pe6: Pin<Pe6>,
576            pub pe7: Pin<Pe7>,
577            pub pe8: Pin<Pe8>,
578            pub pe9: Pin<Pe9>,
579            #[cfg(not(feature = "va41628"))]
580            pub pe10: Pin<Pe10>,
581            #[cfg(not(feature = "va41628"))]
582            pub pe11: Pin<Pe11>,
583            pub pe12: Pin<Pe12>,
584            pub pe13: Pin<Pe13>,
585            pub pe14: Pin<Pe14>,
586            pub pe15: Pin<Pe15>,
587        }
588
589        impl PinsE {
590            pub fn new(_port_e: pac::Porte) -> Self {
591                let syscfg = unsafe { pac::Sysconfig::steal() };
592                reset_peripheral_for_cycles(PeripheralSelect::PortE, 2);
593                syscfg.peripheral_clk_enable().modify(|_, w| {
594                    w.porte().set_bit();
595                    w.ioconfig().set_bit()
596                });
597                Self {
598                    pe0: Pin::__new(),
599                    pe1: Pin::__new(),
600                    pe2: Pin::__new(),
601                    pe3: Pin::__new(),
602                    pe4: Pin::__new(),
603                    pe5: Pin::__new(),
604                    pe6: Pin::__new(),
605                    pe7: Pin::__new(),
606                    pe8: Pin::__new(),
607                    pe9: Pin::__new(),
608                    #[cfg(not(feature = "va41628"))]
609                    pe10: Pin::__new(),
610                    #[cfg(not(feature = "va41628"))]
611                    pe11: Pin::__new(),
612                    pe12: Pin::__new(),
613                    pe13: Pin::__new(),
614                    pe14: Pin::__new(),
615                    pe15: Pin::__new(),
616                }
617            }
618        }
619
620        /// Resource management singleton for GPIO PORT F.
621        pub struct PinsF {
622            pub pf0: Pin<Pf0>,
623            pub pf1: Pin<Pf1>,
624            #[cfg(not(feature = "va41628"))]
625            pub pf2: Pin<Pf2>,
626            #[cfg(not(feature = "va41628"))]
627            pub pf3: Pin<Pf3>,
628            #[cfg(not(feature = "va41628"))]
629            pub pf4: Pin<Pf4>,
630            #[cfg(not(feature = "va41628"))]
631            pub pf5: Pin<Pf5>,
632            #[cfg(not(feature = "va41628"))]
633            pub pf6: Pin<Pf6>,
634            #[cfg(not(feature = "va41628"))]
635            pub pf7: Pin<Pf7>,
636            #[cfg(not(feature = "va41628"))]
637            pub pf8: Pin<Pf8>,
638            pub pf9: Pin<Pf9>,
639            #[cfg(not(feature = "va41628"))]
640            pub pf10: Pin<Pf10>,
641            pub pf11: Pin<Pf11>,
642            pub pf12: Pin<Pf12>,
643            pub pf13: Pin<Pf13>,
644            pub pf14: Pin<Pf14>,
645            pub pf15: Pin<Pf15>,
646        }
647
648        impl PinsF {
649            pub fn new(_port_f: pac::Portf) -> Self {
650                let syscfg = unsafe { pac::Sysconfig::steal() };
651                reset_peripheral_for_cycles(PeripheralSelect::PortF, 2);
652                syscfg.peripheral_clk_enable().modify(|_, w| {
653                    w.portf().set_bit();
654                    w.ioconfig().set_bit()
655                });
656                Self {
657                    pf0: Pin::__new(),
658                    pf1: Pin::__new(),
659                    #[cfg(not(feature = "va41628"))]
660                    pf2: Pin::__new(),
661                    #[cfg(not(feature = "va41628"))]
662                    pf3: Pin::__new(),
663                    #[cfg(not(feature = "va41628"))]
664                    pf4: Pin::__new(),
665                    #[cfg(not(feature = "va41628"))]
666                    pf5: Pin::__new(),
667                    #[cfg(not(feature = "va41628"))]
668                    pf6: Pin::__new(),
669                    #[cfg(not(feature = "va41628"))]
670                    pf7: Pin::__new(),
671                    #[cfg(not(feature = "va41628"))]
672                    pf8: Pin::__new(),
673                    pf9: Pin::__new(),
674                    #[cfg(not(feature = "va41628"))]
675                    pf10: Pin::__new(),
676                    pf11: Pin::__new(),
677                    pf12: Pin::__new(),
678                    pf13: Pin::__new(),
679                    pf14: Pin::__new(),
680                    pf15: Pin::__new(),
681                }
682            }
683        }
684
685        /// Resource management singleton for GPIO PORT G.
686        pub struct PinsG {
687            pub pg0: Pin<Pg0>,
688            pub pg1: Pin<Pg1>,
689            pub pg2: Pin<Pg2>,
690            pub pg3: Pin<Pg3>,
691            pub pg4: Pin<Pg4>,
692            pub pg5: Pin<Pg5>,
693            pub pg6: Pin<Pg6>,
694            pub pg7: Pin<Pg7>,
695        }
696
697        impl PinsG {
698            pub fn new(_port_g: pac::Portg) -> Self {
699                let syscfg = unsafe { pac::Sysconfig::steal() };
700                reset_peripheral_for_cycles(PeripheralSelect::PortG, 2);
701                syscfg.peripheral_clk_enable().modify(|_, w| {
702                    w.portg().set_bit();
703                    w.ioconfig().set_bit()
704                });
705                Self {
706                    pg0: Pin::__new(),
707                    pg1: Pin::__new(),
708                    pg2: Pin::__new(),
709                    pg3: Pin::__new(),
710                    pg4: Pin::__new(),
711                    pg5: Pin::__new(),
712                    pg6: Pin::__new(),
713                    pg7: Pin::__new(),
714                }
715            }
716        }
717    }
718}
vorago_shared_periphs/pins.rs

vorago_shared_periphs/
pins.rs
