vorago_shared_hal/gpio/
regs.rs

1use crate::Port;
2
3cfg_if::cfg_if! {
4    if #[cfg(feature = "vor1x")] {
5        /// PORT A base address.
6        pub const GPIO_0_BASE: usize = 0x5000_0000;
7        /// PORT B base address.
8        pub const GPIO_1_BASE: usize = 0x5000_1000;
9    } else if #[cfg(feature = "vor4x")] {
10        /// PORT A base address.
11        pub const GPIO_0_BASE: usize = 0x4001_2000;
12        /// PORT B base address.
13        pub const GPIO_1_BASE: usize = 0x4001_2400;
14        /// PORT C base address.
15        pub const GPIO_2_BASE: usize = 0x4001_2800;
16        /// PORT D base address.
17        pub const GPIO_3_BASE: usize = 0x4001_2C00;
18        /// PORT E base address.
19        pub const GPIO_4_BASE: usize = 0x4001_3000;
20        /// PORT F base address.
21        pub const GPIO_5_BASE: usize = 0x4001_3400;
22        /// PORT G base address.
23        pub const GPIO_6_BASE: usize = 0x4001_3800;
24    }
25}
26
27#[derive(derive_mmio::Mmio)]
28#[mmio(no_ctors)]
29#[repr(C)]
30pub struct Gpio {
31    #[mmio(PureRead)]
32    data_in: u32,
33    #[mmio(PureRead)]
34    data_in_raw: u32,
35    data_out: u32,
36    data_out_raw: u32,
37    #[mmio(Write)]
38    set_out: u32,
39    #[mmio(Write)]
40    clr_out: u32,
41    #[mmio(Write)]
42    tog_out: u32,
43    data_mask: u32,
44    /// Direction bits. 1 for output, 0 for input.
45    dir: u32,
46    pulse: u32,
47    pulsebase: u32,
48    delay1: u32,
49    delay2: u32,
50    irq_sen: u32,
51    irq_edge: u32,
52    irq_evt: u32,
53    irq_enable: u32,
54    /// Raw interrupt status. This register is not latched and may not indicated edge sensitive
55    /// events.
56    #[mmio(PureRead)]
57    irq_raw: u32,
58    /// Read-only register which shows enabled and active interrupts. Called IRQ_end by Vorago.
59    #[mmio(PureRead)]
60    irq_status: u32,
61    // Reading this register clears it.
62    #[mmio(Read)]
63    edge_status: u32,
64
65    #[cfg(feature = "vor1x")]
66    _reserved: [u32; 0x3eb],
67    #[cfg(feature = "vor4x")]
68    _reserved: [u32; 0xeb],
69
70    /// Peripheral ID. Vorago 1x reset value: 0x0040_07e1. Vorago 4x reset value: 0x0210_07E9.
71    perid: u32,
72}
73
74cfg_if::cfg_if! {
75    if #[cfg(feature = "vor1x")] {
76        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x1000);
77    } else if #[cfg(feature = "vor4x")] {
78        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x400);
79    }
80}
81
82impl Gpio {
83    const fn new_mmio_at(base: usize) -> MmioGpio<'static> {
84        MmioGpio {
85            ptr: base as *mut _,
86            phantom: core::marker::PhantomData,
87        }
88    }
89
90    pub const fn new_mmio(port: Port) -> MmioGpio<'static> {
91        match port {
92            Port::A => Self::new_mmio_at(GPIO_0_BASE),
93            Port::B => Self::new_mmio_at(GPIO_1_BASE),
94            #[cfg(feature = "vor4x")]
95            Port::C => Self::new_mmio_at(GPIO_2_BASE),
96            #[cfg(feature = "vor4x")]
97            Port::D => Self::new_mmio_at(GPIO_3_BASE),
98            #[cfg(feature = "vor4x")]
99            Port::E => Self::new_mmio_at(GPIO_4_BASE),
100            #[cfg(feature = "vor4x")]
101            Port::F => Self::new_mmio_at(GPIO_5_BASE),
102            #[cfg(feature = "vor4x")]
103            Port::G => Self::new_mmio_at(GPIO_6_BASE),
104        }
105    }
106}
107
108impl MmioGpio<'_> {
109    pub fn port(&self) -> Port {
110        match unsafe { self.ptr() } as usize {
111            GPIO_0_BASE => Port::A,
112            GPIO_1_BASE => Port::B,
113            #[cfg(feature = "vor4x")]
114            GPIO_2_BASE => Port::C,
115            #[cfg(feature = "vor4x")]
116            GPIO_3_BASE => Port::D,
117            #[cfg(feature = "vor4x")]
118            GPIO_4_BASE => Port::E,
119            #[cfg(feature = "vor4x")]
120            GPIO_5_BASE => Port::F,
121            #[cfg(feature = "vor4x")]
122            GPIO_6_BASE => Port::G,
123            // Constructors were disabled, so this should really not happen.
124            _ => panic!("unexpected base address of GPIO register block"),
125        }
126    }
127}
vorago_shared_hal/gpio/regs.rs

vorago_shared_hal/gpio/
regs.rs
