vorago_shared_hal/
sysconfig.rs

1#[cfg(feature = "vor1x")]
2use va108xx as pac;
3#[cfg(feature = "vor4x")]
4use va416xx as pac;
5
6#[inline]
7pub fn enable_peripheral_clock(clock: crate::PeripheralSelect) {
8    let syscfg = unsafe { pac::Sysconfig::steal() };
9    syscfg
10        .peripheral_clk_enable()
11        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
12}
13
14#[inline]
15pub fn disable_peripheral_clock(clock: crate::PeripheralSelect) {
16    let syscfg = unsafe { pac::Sysconfig::steal() };
17    syscfg
18        .peripheral_clk_enable()
19        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
20}
21
22#[inline]
23pub fn assert_peripheral_reset(periph_sel: crate::PeripheralSelect) {
24    let syscfg = unsafe { pac::Sysconfig::steal() };
25    syscfg
26        .peripheral_reset()
27        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
28}
29
30#[inline]
31pub fn deassert_peripheral_reset(periph_sel: crate::PeripheralSelect) {
32    let syscfg = unsafe { pac::Sysconfig::steal() };
33    syscfg
34        .peripheral_reset()
35        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
36}
37
38#[inline]
39pub fn reset_peripheral_for_cycles(periph_sel: crate::PeripheralSelect, cycles: usize) {
40    assert_peripheral_reset(periph_sel);
41    cortex_m::asm::delay(cycles as u32);
42    deassert_peripheral_reset(periph_sel);
43}
vorago_shared_hal/sysconfig.rs

vorago_shared_hal/
sysconfig.rs
