vorago_shared_hal/gpio/
regs.rs

1use crate::Port;
2
3cfg_if::cfg_if! {
4    if #[cfg(feature = "vor1x")] {
5        /// PORT A base address.
6        pub const GPIO_0_BASE: usize = 0x5000_0000;
7        /// PORT B base address.
8        pub const GPIO_1_BASE: usize = 0x5000_1000;
9    } else if #[cfg(feature = "vor4x")] {
10        /// PORT A base address.
11        pub const GPIO_0_BASE: usize = 0x4001_2000;
12        /// PORT B base address.
13        pub const GPIO_1_BASE: usize = 0x4001_2400;
14        /// PORT C base address.
15        pub const GPIO_2_BASE: usize = 0x4001_2800;
16        /// PORT D base address.
17        pub const GPIO_3_BASE: usize = 0x4001_2C00;
18        /// PORT E base address.
19        pub const GPIO_4_BASE: usize = 0x4001_3000;
20        /// PORT F base address.
21        pub const GPIO_5_BASE: usize = 0x4001_3400;
22        /// PORT G base address.
23        pub const GPIO_6_BASE: usize = 0x4001_3800;
24    }
25}
26
27#[derive(derive_mmio::Mmio)]
28#[mmio(no_ctors)]
29#[repr(C)]
30pub struct Gpio {
31    #[mmio(PureRead)]
32    data_in: u32,
33    #[mmio(PureRead)]
34    data_in_raw: u32,
35    data_out: u32,
36    data_out_raw: u32,
37    #[mmio(Write)]
38    set_out: u32,
39    #[mmio(Write)]
40    clr_out: u32,
41    #[mmio(Write)]
42    tog_out: u32,
43    data_mask: u32,
44    /// Direction bits. 1 for output, 0 for input.
45    dir: u32,
46    pulse: u32,
47    pulsebase: u32,
48    delay1: u32,
49    delay2: u32,
50    irq_sen: u32,
51    irq_edge: u32,
52    irq_evt: u32,
53    irq_enable: u32,
54    /// Raw interrupt status. This register is not latched and may not indicated edge sensitive
55    /// events.
56    #[mmio(PureRead)]
57    irq_raw: u32,
58    /// Read-only register which shows enabled and active interrupts. Called IRQ_end by Vorago.
59    #[mmio(PureRead)]
60    irq_status: u32,
61    #[mmio(PureRead)]
62    edge_status: u32,
63
64    #[cfg(feature = "vor1x")]
65    _reserved: [u32; 0x3eb],
66    #[cfg(feature = "vor4x")]
67    _reserved: [u32; 0xeb],
68
69    /// Peripheral ID. Vorago 1x reset value: 0x0040_07e1. Vorago 4x reset value: 0x0210_07E9.
70    perid: u32,
71}
72
73cfg_if::cfg_if! {
74    if #[cfg(feature = "vor1x")] {
75        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x1000);
76    } else if #[cfg(feature = "vor4x")] {
77        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x400);
78    }
79}
80
81impl Gpio {
82    const fn new_mmio_at(base: usize) -> MmioGpio<'static> {
83        MmioGpio {
84            ptr: base as *mut _,
85            phantom: core::marker::PhantomData,
86        }
87    }
88
89    pub const fn new_mmio(port: Port) -> MmioGpio<'static> {
90        match port {
91            Port::A => Self::new_mmio_at(GPIO_0_BASE),
92            Port::B => Self::new_mmio_at(GPIO_1_BASE),
93            #[cfg(feature = "vor4x")]
94            Port::C => Self::new_mmio_at(GPIO_2_BASE),
95            #[cfg(feature = "vor4x")]
96            Port::D => Self::new_mmio_at(GPIO_3_BASE),
97            #[cfg(feature = "vor4x")]
98            Port::E => Self::new_mmio_at(GPIO_4_BASE),
99            #[cfg(feature = "vor4x")]
100            Port::F => Self::new_mmio_at(GPIO_5_BASE),
101            #[cfg(feature = "vor4x")]
102            Port::G => Self::new_mmio_at(GPIO_6_BASE),
103        }
104    }
105}
106
107impl MmioGpio<'_> {
108    pub fn port(&self) -> Port {
109        match unsafe { self.ptr() } as usize {
110            GPIO_0_BASE => Port::A,
111            GPIO_1_BASE => Port::B,
112            #[cfg(feature = "vor4x")]
113            GPIO_2_BASE => Port::C,
114            #[cfg(feature = "vor4x")]
115            GPIO_3_BASE => Port::D,
116            #[cfg(feature = "vor4x")]
117            GPIO_4_BASE => Port::E,
118            #[cfg(feature = "vor4x")]
119            GPIO_5_BASE => Port::F,
120            #[cfg(feature = "vor4x")]
121            GPIO_6_BASE => Port::G,
122            // Constructors were disabled, so this should really not happen.
123            _ => panic!("unexpected base address of GPIO register block"),
124        }
125    }
126}
vorago_shared_hal/gpio/regs.rs

vorago_shared_hal/gpio/
regs.rs
