vorago_shared_hal/
pins.rs

1use crate::sysconfig::reset_peripheral_for_cycles;
2
3pub use crate::gpio::{DynPinId, Port};
4
5use crate::PeripheralSelect;
6use crate::sealed::Sealed;
7#[cfg(feature = "vor1x")]
8use va108xx as pac;
9#[cfg(feature = "vor4x")]
10use va416xx as pac;
11
12/// Trait implemented by data structures associated with pin identification.
13pub trait PinId {
14    const ID: crate::gpio::ll::DynPinId;
15}
16
17pub trait AnyPin: Sealed {
18    const ID: DynPinId;
19}
20
21/// Primary Pin structure for the physical pins exposed by Vorago MCUs.
22///
23/// This pin structure is only used for resource management and does not do anything on its
24/// own.
25pub struct Pin<Id: PinId> {
26    phantom: core::marker::PhantomData<Id>,
27}
28
29impl<Id: PinId + Sealed> AnyPin for Pin<Id> {
30    const ID: DynPinId = Id::ID;
31}
32
33impl<I: PinId> Pin<I> {
34    #[allow(clippy::new_without_default)]
35    #[doc(hidden)]
36    pub const fn __new() -> Self {
37        Self {
38            phantom: core::marker::PhantomData,
39        }
40    }
41
42    /// Create a new pin instance.
43    ///
44    /// # Safety
45    ///
46    /// This circumvents ownership rules of the HAL and allows creating multiple instances
47    /// of the same pin.
48    pub const unsafe fn steal() -> Self {
49        Self::__new()
50    }
51}
52
53macro_rules! pin_id {
54    ($Id:ident, $Port:path, $num:literal) => {
55        // Need paste macro to use ident in doc attribute
56        paste::paste! {
57            #[doc = "Pin ID representing pin " $Id]
58            #[derive(Debug)]
59            pub enum $Id {}
60
61            impl $crate::sealed::Sealed for $Id {}
62            impl PinId for $Id {
63                const ID: DynPinId = DynPinId::new_unchecked($Port, $num);
64            }
65        }
66    };
67}
68
69impl<I: PinId + Sealed> Sealed for Pin<I> {}
70
71pin_id!(Pa0, Port::A, 0);
72pin_id!(Pa1, Port::A, 1);
73pin_id!(Pa2, Port::A, 2);
74pin_id!(Pa3, Port::A, 3);
75pin_id!(Pa4, Port::A, 4);
76pin_id!(Pa5, Port::A, 5);
77pin_id!(Pa6, Port::A, 6);
78pin_id!(Pa7, Port::A, 7);
79pin_id!(Pa8, Port::A, 8);
80pin_id!(Pa9, Port::A, 9);
81pin_id!(Pa10, Port::A, 10);
82pin_id!(Pa11, Port::A, 11);
83pin_id!(Pa12, Port::A, 12);
84pin_id!(Pa13, Port::A, 13);
85pin_id!(Pa14, Port::A, 14);
86pin_id!(Pa15, Port::A, 15);
87#[cfg(feature = "vor1x")]
88pin_id!(Pa16, Port::A, 16);
89#[cfg(feature = "vor1x")]
90pin_id!(Pa17, Port::A, 17);
91#[cfg(feature = "vor1x")]
92pin_id!(Pa18, Port::A, 18);
93#[cfg(feature = "vor1x")]
94pin_id!(Pa19, Port::A, 19);
95#[cfg(feature = "vor1x")]
96pin_id!(Pa20, Port::A, 20);
97#[cfg(feature = "vor1x")]
98pin_id!(Pa21, Port::A, 21);
99#[cfg(feature = "vor1x")]
100pin_id!(Pa22, Port::A, 22);
101#[cfg(feature = "vor1x")]
102pin_id!(Pa23, Port::A, 23);
103#[cfg(feature = "vor1x")]
104pin_id!(Pa24, Port::A, 24);
105#[cfg(feature = "vor1x")]
106pin_id!(Pa25, Port::A, 25);
107#[cfg(feature = "vor1x")]
108pin_id!(Pa26, Port::A, 26);
109#[cfg(feature = "vor1x")]
110#[cfg(feature = "vor1x")]
111pin_id!(Pa27, Port::A, 27);
112#[cfg(feature = "vor1x")]
113pin_id!(Pa28, Port::A, 28);
114#[cfg(feature = "vor1x")]
115pin_id!(Pa29, Port::A, 29);
116#[cfg(feature = "vor1x")]
117pin_id!(Pa30, Port::A, 30);
118#[cfg(feature = "vor1x")]
119pin_id!(Pa31, Port::A, 31);
120
121pin_id!(Pb0, Port::B, 0);
122pin_id!(Pb1, Port::B, 1);
123pin_id!(Pb2, Port::B, 2);
124pin_id!(Pb3, Port::B, 3);
125pin_id!(Pb4, Port::B, 4);
126#[cfg(not(feature = "va41628"))]
127pin_id!(Pb5, Port::B, 5);
128#[cfg(not(feature = "va41628"))]
129pin_id!(Pb6, Port::B, 6);
130#[cfg(not(feature = "va41628"))]
131pin_id!(Pb7, Port::B, 7);
132#[cfg(not(feature = "va41628"))]
133pin_id!(Pb8, Port::B, 8);
134#[cfg(not(feature = "va41628"))]
135pin_id!(Pb9, Port::B, 9);
136#[cfg(not(feature = "va41628"))]
137pin_id!(Pb10, Port::B, 10);
138#[cfg(not(feature = "va41628"))]
139pin_id!(Pb11, Port::B, 11);
140pin_id!(Pb12, Port::B, 12);
141pin_id!(Pb13, Port::B, 13);
142pin_id!(Pb14, Port::B, 14);
143pin_id!(Pb15, Port::B, 15);
144#[cfg(feature = "vor1x")]
145pin_id!(Pb16, Port::B, 16);
146#[cfg(feature = "vor1x")]
147pin_id!(Pb17, Port::B, 17);
148#[cfg(feature = "vor1x")]
149pin_id!(Pb18, Port::B, 18);
150#[cfg(feature = "vor1x")]
151pin_id!(Pb19, Port::B, 19);
152#[cfg(feature = "vor1x")]
153pin_id!(Pb20, Port::B, 20);
154#[cfg(feature = "vor1x")]
155pin_id!(Pb21, Port::B, 21);
156#[cfg(feature = "vor1x")]
157pin_id!(Pb22, Port::B, 22);
158#[cfg(feature = "vor1x")]
159pin_id!(Pb23, Port::B, 23);
160
161cfg_if::cfg_if! {
162    if #[cfg(feature = "vor4x")] {
163        pin_id!(Pc0, Port::C, 0);
164        pin_id!(Pc1, Port::C, 1);
165        pin_id!(Pc2, Port::C, 2);
166        pin_id!(Pc3, Port::C, 3);
167        pin_id!(Pc4, Port::C, 4);
168        pin_id!(Pc5, Port::C, 5);
169        pin_id!(Pc6, Port::C, 6);
170        pin_id!(Pc7, Port::C, 7);
171        pin_id!(Pc8, Port::C, 8);
172        pin_id!(Pc9, Port::C, 9);
173        pin_id!(Pc10, Port::C, 10);
174        pin_id!(Pc11, Port::C, 11);
175        pin_id!(Pc12, Port::C, 12);
176        #[cfg(not(feature = "va41628"))]
177        pin_id!(Pc13, Port::C, 13);
178        pin_id!(Pc14, Port::C, 14);
179        #[cfg(not(feature = "va41628"))]
180        pin_id!(Pc15, Port::C, 15);
181
182        #[cfg(not(feature = "va41628"))]
183        pin_id!(Pd0, Port::D, 0);
184        #[cfg(not(feature = "va41628"))]
185        pin_id!(Pd1, Port::D, 1);
186        #[cfg(not(feature = "va41628"))]
187        pin_id!(Pd2, Port::D, 2);
188        #[cfg(not(feature = "va41628"))]
189        pin_id!(Pd3, Port::D, 3);
190        #[cfg(not(feature = "va41628"))]
191        pin_id!(Pd4, Port::D, 4);
192        #[cfg(not(feature = "va41628"))]
193        pin_id!(Pd5, Port::D, 5);
194        #[cfg(not(feature = "va41628"))]
195        pin_id!(Pd6, Port::D, 6);
196        #[cfg(not(feature = "va41628"))]
197        pin_id!(Pd7, Port::D, 7);
198        #[cfg(not(feature = "va41628"))]
199        pin_id!(Pd8, Port::D, 8);
200        #[cfg(not(feature = "va41628"))]
201        pin_id!(Pd9, Port::D, 9);
202        pin_id!(Pd10, Port::D, 10);
203        pin_id!(Pd11, Port::D, 11);
204        pin_id!(Pd12, Port::D, 12);
205        pin_id!(Pd13, Port::D, 13);
206        pin_id!(Pd14, Port::D, 14);
207        pin_id!(Pd15, Port::D, 15);
208
209        pin_id!(Pe0, Port::E, 0);
210        pin_id!(Pe1, Port::E, 1);
211        pin_id!(Pe2, Port::E, 2);
212        pin_id!(Pe3, Port::E, 3);
213        pin_id!(Pe4, Port::E, 4);
214        pin_id!(Pe5, Port::E, 5);
215        pin_id!(Pe6, Port::E, 6);
216        pin_id!(Pe7, Port::E, 7);
217        pin_id!(Pe8, Port::E, 8);
218        pin_id!(Pe9, Port::E, 9);
219        #[cfg(not(feature = "va41628"))]
220        pin_id!(Pe10, Port::E, 10);
221        #[cfg(not(feature = "va41628"))]
222        pin_id!(Pe11, Port::E, 11);
223        pin_id!(Pe12, Port::E, 12);
224        pin_id!(Pe13, Port::E, 13);
225        pin_id!(Pe14, Port::E, 14);
226        pin_id!(Pe15, Port::E, 15);
227
228        pin_id!(Pf0, Port::F, 0);
229        pin_id!(Pf1, Port::F, 1);
230        #[cfg(not(feature = "va41628"))]
231        pin_id!(Pf2, Port::F, 2);
232        #[cfg(not(feature = "va41628"))]
233        pin_id!(Pf3, Port::F, 3);
234        #[cfg(not(feature = "va41628"))]
235        pin_id!(Pf4, Port::F, 4);
236        #[cfg(not(feature = "va41628"))]
237        pin_id!(Pf5, Port::F, 5);
238        #[cfg(not(feature = "va41628"))]
239        pin_id!(Pf6, Port::F, 6);
240        #[cfg(not(feature = "va41628"))]
241        pin_id!(Pf7, Port::F, 7);
242        #[cfg(not(feature = "va41628"))]
243        pin_id!(Pf8, Port::F, 8);
244        pin_id!(Pf9, Port::F, 9);
245        #[cfg(not(feature = "va41628"))]
246        pin_id!(Pf10, Port::F, 10);
247        pin_id!(Pf11, Port::F, 11);
248        pin_id!(Pf12, Port::F, 12);
249        pin_id!(Pf13, Port::F, 13);
250        pin_id!(Pf14, Port::F, 14);
251        pin_id!(Pf15, Port::F, 15);
252
253        pin_id!(Pg0, Port::G, 0);
254        pin_id!(Pg1, Port::G, 1);
255        pin_id!(Pg2, Port::G, 2);
256        pin_id!(Pg3, Port::G, 3);
257        pin_id!(Pg4, Port::G, 4);
258        pin_id!(Pg5, Port::G, 5);
259        pin_id!(Pg6, Port::G, 6);
260        pin_id!(Pg7, Port::G, 7);
261    }
262}
263
264/// Resource management singleton for GPIO PORT A.
265pub struct PinsA {
266    pub pa0: Pin<Pa0>,
267    pub pa1: Pin<Pa1>,
268    pub pa2: Pin<Pa2>,
269    pub pa3: Pin<Pa3>,
270    pub pa4: Pin<Pa4>,
271    pub pa5: Pin<Pa5>,
272    pub pa6: Pin<Pa6>,
273    pub pa7: Pin<Pa7>,
274    pub pa8: Pin<Pa8>,
275    pub pa9: Pin<Pa9>,
276    pub pa10: Pin<Pa10>,
277    pub pa11: Pin<Pa11>,
278    pub pa12: Pin<Pa12>,
279    pub pa13: Pin<Pa13>,
280    pub pa14: Pin<Pa14>,
281    pub pa15: Pin<Pa15>,
282    #[cfg(feature = "vor1x")]
283    pub pa16: Pin<Pa16>,
284    #[cfg(feature = "vor1x")]
285    pub pa17: Pin<Pa17>,
286    #[cfg(feature = "vor1x")]
287    pub pa18: Pin<Pa18>,
288    #[cfg(feature = "vor1x")]
289    pub pa19: Pin<Pa19>,
290    #[cfg(feature = "vor1x")]
291    pub pa20: Pin<Pa20>,
292    #[cfg(feature = "vor1x")]
293    pub pa21: Pin<Pa21>,
294    #[cfg(feature = "vor1x")]
295    pub pa22: Pin<Pa22>,
296    #[cfg(feature = "vor1x")]
297    pub pa23: Pin<Pa23>,
298    #[cfg(feature = "vor1x")]
299    pub pa24: Pin<Pa24>,
300    #[cfg(feature = "vor1x")]
301    pub pa25: Pin<Pa25>,
302    #[cfg(feature = "vor1x")]
303    pub pa26: Pin<Pa26>,
304    #[cfg(feature = "vor1x")]
305    pub pa27: Pin<Pa27>,
306    #[cfg(feature = "vor1x")]
307    pub pa28: Pin<Pa28>,
308    #[cfg(feature = "vor1x")]
309    pub pa29: Pin<Pa29>,
310    #[cfg(feature = "vor1x")]
311    pub pa30: Pin<Pa30>,
312    #[cfg(feature = "vor1x")]
313    pub pa31: Pin<Pa31>,
314}
315
316impl PinsA {
317    pub fn new(_port_a: pac::Porta) -> Self {
318        let syscfg = unsafe { pac::Sysconfig::steal() };
319        reset_peripheral_for_cycles(PeripheralSelect::PortA, 2);
320        syscfg.peripheral_clk_enable().modify(|_, w| {
321            w.porta().set_bit();
322            #[cfg(feature = "vor1x")]
323            w.gpio().set_bit();
324            w.ioconfig().set_bit()
325        });
326        Self {
327            pa0: Pin::__new(),
328            pa1: Pin::__new(),
329            pa2: Pin::__new(),
330            pa3: Pin::__new(),
331            pa4: Pin::__new(),
332            pa5: Pin::__new(),
333            pa6: Pin::__new(),
334            pa7: Pin::__new(),
335            pa8: Pin::__new(),
336            pa9: Pin::__new(),
337            pa10: Pin::__new(),
338            pa11: Pin::__new(),
339            pa12: Pin::__new(),
340            pa13: Pin::__new(),
341            pa14: Pin::__new(),
342            pa15: Pin::__new(),
343            #[cfg(feature = "vor1x")]
344            pa16: Pin::__new(),
345            #[cfg(feature = "vor1x")]
346            pa17: Pin::__new(),
347            #[cfg(feature = "vor1x")]
348            pa18: Pin::__new(),
349            #[cfg(feature = "vor1x")]
350            pa19: Pin::__new(),
351            #[cfg(feature = "vor1x")]
352            pa20: Pin::__new(),
353            #[cfg(feature = "vor1x")]
354            pa21: Pin::__new(),
355            #[cfg(feature = "vor1x")]
356            pa22: Pin::__new(),
357            #[cfg(feature = "vor1x")]
358            pa23: Pin::__new(),
359            #[cfg(feature = "vor1x")]
360            pa24: Pin::__new(),
361            #[cfg(feature = "vor1x")]
362            pa25: Pin::__new(),
363            #[cfg(feature = "vor1x")]
364            pa26: Pin::__new(),
365            #[cfg(feature = "vor1x")]
366            pa27: Pin::__new(),
367            #[cfg(feature = "vor1x")]
368            pa28: Pin::__new(),
369            #[cfg(feature = "vor1x")]
370            pa29: Pin::__new(),
371            #[cfg(feature = "vor1x")]
372            pa30: Pin::__new(),
373            #[cfg(feature = "vor1x")]
374            pa31: Pin::__new(),
375        }
376    }
377}
378
379/// Resource management singleton for GPIO PORT B.
380pub struct PinsB {
381    pub pb0: Pin<Pb0>,
382    pub pb1: Pin<Pb1>,
383    pub pb2: Pin<Pb2>,
384    pub pb3: Pin<Pb3>,
385    pub pb4: Pin<Pb4>,
386    #[cfg(not(feature = "va41628"))]
387    pub pb5: Pin<Pb5>,
388    #[cfg(not(feature = "va41628"))]
389    pub pb6: Pin<Pb6>,
390    #[cfg(not(feature = "va41628"))]
391    pub pb7: Pin<Pb7>,
392    #[cfg(not(feature = "va41628"))]
393    pub pb8: Pin<Pb8>,
394    #[cfg(not(feature = "va41628"))]
395    pub pb9: Pin<Pb9>,
396    #[cfg(not(feature = "va41628"))]
397    pub pb10: Pin<Pb10>,
398    #[cfg(not(feature = "va41628"))]
399    pub pb11: Pin<Pb11>,
400    pub pb12: Pin<Pb12>,
401    pub pb13: Pin<Pb13>,
402    pub pb14: Pin<Pb14>,
403    pub pb15: Pin<Pb15>,
404    #[cfg(feature = "vor1x")]
405    pub pb16: Pin<Pb16>,
406    #[cfg(feature = "vor1x")]
407    pub pb17: Pin<Pb17>,
408    #[cfg(feature = "vor1x")]
409    pub pb18: Pin<Pb18>,
410    #[cfg(feature = "vor1x")]
411    pub pb19: Pin<Pb19>,
412    #[cfg(feature = "vor1x")]
413    pub pb20: Pin<Pb20>,
414    #[cfg(feature = "vor1x")]
415    pub pb21: Pin<Pb21>,
416    #[cfg(feature = "vor1x")]
417    pub pb22: Pin<Pb22>,
418    #[cfg(feature = "vor1x")]
419    pub pb23: Pin<Pb23>,
420}
421
422impl PinsB {
423    pub fn new(_port_b: pac::Portb) -> Self {
424        let syscfg = unsafe { pac::Sysconfig::steal() };
425        reset_peripheral_for_cycles(PeripheralSelect::PortB, 2);
426        syscfg.peripheral_clk_enable().modify(|_, w| {
427            w.portb().set_bit();
428            #[cfg(feature = "vor1x")]
429            w.gpio().set_bit();
430            w.ioconfig().set_bit()
431        });
432        Self {
433            pb0: Pin::__new(),
434            pb1: Pin::__new(),
435            pb2: Pin::__new(),
436            pb3: Pin::__new(),
437            pb4: Pin::__new(),
438            #[cfg(not(feature = "va41628"))]
439            pb5: Pin::__new(),
440            #[cfg(not(feature = "va41628"))]
441            pb6: Pin::__new(),
442            #[cfg(not(feature = "va41628"))]
443            pb7: Pin::__new(),
444            #[cfg(not(feature = "va41628"))]
445            pb8: Pin::__new(),
446            #[cfg(not(feature = "va41628"))]
447            pb9: Pin::__new(),
448            #[cfg(not(feature = "va41628"))]
449            pb10: Pin::__new(),
450            #[cfg(not(feature = "va41628"))]
451            pb11: Pin::__new(),
452            pb12: Pin::__new(),
453            pb13: Pin::__new(),
454            pb14: Pin::__new(),
455            pb15: Pin::__new(),
456            #[cfg(feature = "vor1x")]
457            pb16: Pin::__new(),
458            #[cfg(feature = "vor1x")]
459            pb17: Pin::__new(),
460            #[cfg(feature = "vor1x")]
461            pb18: Pin::__new(),
462            #[cfg(feature = "vor1x")]
463            pb19: Pin::__new(),
464            #[cfg(feature = "vor1x")]
465            pb20: Pin::__new(),
466            #[cfg(feature = "vor1x")]
467            pb21: Pin::__new(),
468            #[cfg(feature = "vor1x")]
469            pb22: Pin::__new(),
470            #[cfg(feature = "vor1x")]
471            pb23: Pin::__new(),
472        }
473    }
474}
475
476cfg_if::cfg_if! {
477    if #[cfg(feature = "vor4x")] {
478        /// Resource management singleton for GPIO PORT C.
479        pub struct PinsC {
480            pub pc0: Pin<Pc0>,
481            pub pc1: Pin<Pc1>,
482            pub pc2: Pin<Pc2>,
483            pub pc3: Pin<Pc3>,
484            pub pc4: Pin<Pc4>,
485            pub pc5: Pin<Pc5>,
486            pub pc6: Pin<Pc6>,
487            pub pc7: Pin<Pc7>,
488            pub pc8: Pin<Pc8>,
489            pub pc9: Pin<Pc9>,
490            pub pc10: Pin<Pc10>,
491            pub pc11: Pin<Pc11>,
492            pub pc12: Pin<Pc12>,
493            #[cfg(not(feature = "va41628"))]
494            pub pc13: Pin<Pc13>,
495            pub pc14: Pin<Pc14>,
496            #[cfg(not(feature = "va41628"))]
497            pub pc15: Pin<Pc15>,
498        }
499
500        impl PinsC {
501            pub fn new(_port_c: pac::Portc) -> Self {
502                let syscfg = unsafe { pac::Sysconfig::steal() };
503                reset_peripheral_for_cycles(PeripheralSelect::PortC, 2);
504                syscfg.peripheral_clk_enable().modify(|_, w| {
505                    w.portc().set_bit();
506                    w.ioconfig().set_bit()
507                });
508                Self {
509                    pc0: Pin::__new(),
510                    pc1: Pin::__new(),
511                    pc2: Pin::__new(),
512                    pc3: Pin::__new(),
513                    pc4: Pin::__new(),
514                    pc5: Pin::__new(),
515                    pc6: Pin::__new(),
516                    pc7: Pin::__new(),
517                    pc8: Pin::__new(),
518                    pc9: Pin::__new(),
519                    pc10: Pin::__new(),
520                    pc11: Pin::__new(),
521                    pc12: Pin::__new(),
522            #[cfg(not(feature = "va41628"))]
523                    pc13: Pin::__new(),
524                    pc14: Pin::__new(),
525            #[cfg(not(feature = "va41628"))]
526                    pc15: Pin::__new(),
527                }
528            }
529        }
530
531        /// Resource management singleton for GPIO PORT D.
532        pub struct PinsD {
533            #[cfg(not(feature = "va41628"))]
534            pub pd0: Pin<Pd0>,
535            #[cfg(not(feature = "va41628"))]
536            pub pd1: Pin<Pd1>,
537            #[cfg(not(feature = "va41628"))]
538            pub pd2: Pin<Pd2>,
539            #[cfg(not(feature = "va41628"))]
540            pub pd3: Pin<Pd3>,
541            #[cfg(not(feature = "va41628"))]
542            pub pd4: Pin<Pd4>,
543            #[cfg(not(feature = "va41628"))]
544            pub pd5: Pin<Pd5>,
545            #[cfg(not(feature = "va41628"))]
546            pub pd6: Pin<Pd6>,
547            #[cfg(not(feature = "va41628"))]
548            pub pd7: Pin<Pd7>,
549            #[cfg(not(feature = "va41628"))]
550            pub pd8: Pin<Pd8>,
551            #[cfg(not(feature = "va41628"))]
552            pub pd9: Pin<Pd9>,
553            pub pd10: Pin<Pd10>,
554            pub pd11: Pin<Pd11>,
555            pub pd12: Pin<Pd12>,
556            pub pd13: Pin<Pd13>,
557            pub pd14: Pin<Pd14>,
558            pub pd15: Pin<Pd15>,
559        }
560
561        impl PinsD {
562            pub fn new(_port_d: pac::Portd) -> Self {
563                let syscfg = unsafe { pac::Sysconfig::steal() };
564                reset_peripheral_for_cycles(PeripheralSelect::PortD, 2);
565                syscfg.peripheral_clk_enable().modify(|_, w| {
566                    w.portd().set_bit();
567                    w.ioconfig().set_bit()
568                });
569                Self {
570                    #[cfg(not(feature = "va41628"))]
571                    pd0: Pin::__new(),
572                    #[cfg(not(feature = "va41628"))]
573                    pd1: Pin::__new(),
574                    #[cfg(not(feature = "va41628"))]
575                    pd2: Pin::__new(),
576                    #[cfg(not(feature = "va41628"))]
577                    pd3: Pin::__new(),
578                    #[cfg(not(feature = "va41628"))]
579                    pd4: Pin::__new(),
580                    #[cfg(not(feature = "va41628"))]
581                    pd5: Pin::__new(),
582                    #[cfg(not(feature = "va41628"))]
583                    pd6: Pin::__new(),
584                    #[cfg(not(feature = "va41628"))]
585                    pd7: Pin::__new(),
586                    #[cfg(not(feature = "va41628"))]
587                    pd8: Pin::__new(),
588                    #[cfg(not(feature = "va41628"))]
589                    pd9: Pin::__new(),
590                    pd10: Pin::__new(),
591                    pd11: Pin::__new(),
592                    pd12: Pin::__new(),
593                    pd13: Pin::__new(),
594                    pd14: Pin::__new(),
595                    pd15: Pin::__new(),
596                }
597            }
598        }
599
600        /// Resource management singleton for GPIO PORT E.
601        pub struct PinsE {
602            pub pe0: Pin<Pe0>,
603            pub pe1: Pin<Pe1>,
604            pub pe2: Pin<Pe2>,
605            pub pe3: Pin<Pe3>,
606            pub pe4: Pin<Pe4>,
607            pub pe5: Pin<Pe5>,
608            pub pe6: Pin<Pe6>,
609            pub pe7: Pin<Pe7>,
610            pub pe8: Pin<Pe8>,
611            pub pe9: Pin<Pe9>,
612            #[cfg(not(feature = "va41628"))]
613            pub pe10: Pin<Pe10>,
614            #[cfg(not(feature = "va41628"))]
615            pub pe11: Pin<Pe11>,
616            pub pe12: Pin<Pe12>,
617            pub pe13: Pin<Pe13>,
618            pub pe14: Pin<Pe14>,
619            pub pe15: Pin<Pe15>,
620        }
621
622        impl PinsE {
623            pub fn new(_port_e: pac::Porte) -> Self {
624                let syscfg = unsafe { pac::Sysconfig::steal() };
625                reset_peripheral_for_cycles(PeripheralSelect::PortE, 2);
626                syscfg.peripheral_clk_enable().modify(|_, w| {
627                    w.porte().set_bit();
628                    w.ioconfig().set_bit()
629                });
630                Self {
631                    pe0: Pin::__new(),
632                    pe1: Pin::__new(),
633                    pe2: Pin::__new(),
634                    pe3: Pin::__new(),
635                    pe4: Pin::__new(),
636                    pe5: Pin::__new(),
637                    pe6: Pin::__new(),
638                    pe7: Pin::__new(),
639                    pe8: Pin::__new(),
640                    pe9: Pin::__new(),
641                    #[cfg(not(feature = "va41628"))]
642                    pe10: Pin::__new(),
643                    #[cfg(not(feature = "va41628"))]
644                    pe11: Pin::__new(),
645                    pe12: Pin::__new(),
646                    pe13: Pin::__new(),
647                    pe14: Pin::__new(),
648                    pe15: Pin::__new(),
649                }
650            }
651        }
652
653        /// Resource management singleton for GPIO PORT F.
654        pub struct PinsF {
655            pub pf0: Pin<Pf0>,
656            pub pf1: Pin<Pf1>,
657            #[cfg(not(feature = "va41628"))]
658            pub pf2: Pin<Pf2>,
659            #[cfg(not(feature = "va41628"))]
660            pub pf3: Pin<Pf3>,
661            #[cfg(not(feature = "va41628"))]
662            pub pf4: Pin<Pf4>,
663            #[cfg(not(feature = "va41628"))]
664            pub pf5: Pin<Pf5>,
665            #[cfg(not(feature = "va41628"))]
666            pub pf6: Pin<Pf6>,
667            #[cfg(not(feature = "va41628"))]
668            pub pf7: Pin<Pf7>,
669            #[cfg(not(feature = "va41628"))]
670            pub pf8: Pin<Pf8>,
671            pub pf9: Pin<Pf9>,
672            #[cfg(not(feature = "va41628"))]
673            pub pf10: Pin<Pf10>,
674            pub pf11: Pin<Pf11>,
675            pub pf12: Pin<Pf12>,
676            pub pf13: Pin<Pf13>,
677            pub pf14: Pin<Pf14>,
678            pub pf15: Pin<Pf15>,
679        }
680
681        impl PinsF {
682            pub fn new(_port_f: pac::Portf) -> Self {
683                let syscfg = unsafe { pac::Sysconfig::steal() };
684                reset_peripheral_for_cycles(PeripheralSelect::PortF, 2);
685                syscfg.peripheral_clk_enable().modify(|_, w| {
686                    w.portf().set_bit();
687                    w.ioconfig().set_bit()
688                });
689                Self {
690                    pf0: Pin::__new(),
691                    pf1: Pin::__new(),
692                    #[cfg(not(feature = "va41628"))]
693                    pf2: Pin::__new(),
694                    #[cfg(not(feature = "va41628"))]
695                    pf3: Pin::__new(),
696                    #[cfg(not(feature = "va41628"))]
697                    pf4: Pin::__new(),
698                    #[cfg(not(feature = "va41628"))]
699                    pf5: Pin::__new(),
700                    #[cfg(not(feature = "va41628"))]
701                    pf6: Pin::__new(),
702                    #[cfg(not(feature = "va41628"))]
703                    pf7: Pin::__new(),
704                    #[cfg(not(feature = "va41628"))]
705                    pf8: Pin::__new(),
706                    pf9: Pin::__new(),
707                    #[cfg(not(feature = "va41628"))]
708                    pf10: Pin::__new(),
709                    pf11: Pin::__new(),
710                    pf12: Pin::__new(),
711                    pf13: Pin::__new(),
712                    pf14: Pin::__new(),
713                    pf15: Pin::__new(),
714                }
715            }
716        }
717
718        /// Resource management singleton for GPIO PORT G.
719        pub struct PinsG {
720            pub pg0: Pin<Pg0>,
721            pub pg1: Pin<Pg1>,
722            pub pg2: Pin<Pg2>,
723            pub pg3: Pin<Pg3>,
724            pub pg4: Pin<Pg4>,
725            pub pg5: Pin<Pg5>,
726            pub pg6: Pin<Pg6>,
727            pub pg7: Pin<Pg7>,
728        }
729
730        impl PinsG {
731            pub fn new(_port_g: pac::Portg) -> Self {
732                let syscfg = unsafe { pac::Sysconfig::steal() };
733                reset_peripheral_for_cycles(PeripheralSelect::PortG, 2);
734                syscfg.peripheral_clk_enable().modify(|_, w| {
735                    w.portg().set_bit();
736                    w.ioconfig().set_bit()
737                });
738                Self {
739                    pg0: Pin::__new(),
740                    pg1: Pin::__new(),
741                    pg2: Pin::__new(),
742                    pg3: Pin::__new(),
743                    pg4: Pin::__new(),
744                    pg5: Pin::__new(),
745                    pg6: Pin::__new(),
746                    pg7: Pin::__new(),
747                }
748            }
749        }
750    }
751}
vorago_shared_hal/pins.rs

vorago_shared_hal/
pins.rs
