Expand description

Volatile access to memory mapped hardware registers


use volatile_register::RW;

// Create a struct that represents the memory mapped register block
/// Nested Vector Interrupt Controller
pub struct Nvic {
    /// Interrupt Set-Enable
    pub iser: [RW<u32>; 8],
    reserved0: [u32; 24],
    /// Interrupt Clear-Enable
    pub icer: [RW<u32>; 8],
    reserved1: [u32; 24],
    // .. more registers ..

// Access the registers by casting the base address of the register block
// to the previously declared `struct`
let nvic = 0xE000_E100 as *const Nvic;
// Unsafe because the compiler can't verify the address is correct
unsafe { (*nvic).iser[0].write(1) }


  • Read-Only register
  • Read-Write register
  • Write-Only register